CN1322564C - 硅锗双极型晶体管 - Google Patents

硅锗双极型晶体管 Download PDF

Info

Publication number
CN1322564C
CN1322564C CNB018223753A CN01822375A CN1322564C CN 1322564 C CN1322564 C CN 1322564C CN B018223753 A CNB018223753 A CN B018223753A CN 01822375 A CN01822375 A CN 01822375A CN 1322564 C CN1322564 C CN 1322564C
Authority
CN
China
Prior art keywords
sige
source gas
collector region
bipolar transistor
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB018223753A
Other languages
English (en)
Other versions
CN1502124A (zh
Inventor
J·O·徐
D·D·库尔鲍格
J·S·顿恩
D·格林伯格
D·哈拉梅
B·杰甘内森
R·A·约翰逊
L·兰泽罗蒂
K·T·舍恩伯格
R·W·沃斯里奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1502124A publication Critical patent/CN1502124A/zh
Application granted granted Critical
Publication of CN1322564C publication Critical patent/CN1322564C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66242Heterojunction transistors [HBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/02447Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02579P-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors
    • H01L29/7378Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

提供一种在发射区和集电区之间基本没有位错缺陷的SiGe双极型晶体管和其制造方法。该SiGe双极型晶体管包括第一导电类型的集电区(52);在所述集电区(52)的一部分上形成的SiGe基区(54);和在所述SiGe基区(54)的一部分上形成的所述第一导电类型的发射区(56),其中所述集电区(52)和所述基区(54)包括其中连续的碳。该SiGe基区(54)进一步用硼掺杂。

Description

硅锗双极型晶体管
本发明涉及双极型晶体管,特别是,涉及硅锗(SiGe)双极型晶体管,它包括含有碳的轻掺杂Si集电区和SiGe基区,碳连续的加入整个集电区和SiGe基区。这里还公开了一种将碳连续地加入SiGe双极型晶体管的轻掺杂Si集电区和SiGe基区中的方法。术语SiGe在这里用来表示硅锗合金,即,Si1-xGex
高频率有线和无线市场的显著增长已经引发了新的机遇,对此,例如SiGe的化合物半导体与体互补金属氧化物半导体(CMOS)技术相比有着独一无二的优势。随着外延层假晶SiGe淀积工艺的快速发展,基于外延的SiGe异质结双极型晶体管已经与主流先进的CMOS研制结合在一起以用于可接受的广阔市场,为模拟和射频(RF)电路提供SiGe技术的优势,同时保持全面利用先进的CMOS技术基础用于数字逻辑电路。
SiGe异质结双极型晶体管器件正在取代硅双极结型器件作为整个模拟应用方面的首要元件。典型的现有技术SiGe异质结双极型晶体管如图1所示。具体来说,现有技术的异质结双极型晶体管包括n+子集电极层10,其上面形成有一层n-Si集电(即,轻掺杂)区12。该晶体管还包括在轻掺杂Si集电区上形成的p+SiGe基区14。基区14的一部分包括n+Si发射区16,和另一部分包括通过间距20与发射区隔开的基极电极18。在发射区16的上面是发射极电极22。
关于图1所示类型的双极型SiGe晶体管的一个主要问题是在集电区和发射区之间存在位错。当这些位错在集电区和发射区之间扩展时,会发生双极管道例如CE短路;管道短路是在SiGe双极技术中主要的产量降低因素。
在现有技术中,已知将碳加入双极结构中用于仅在SiGe区内的基极上面形成碳层。这样的结构如图2所示,其中标号24表示生长的碳层。在SiGe区内的基极上面形成碳层的现有技术方法由于妨碍了本征基区的扩散,从而导致了狭窄的基极宽度。该结果例如图3所示。
在现有技术中典型的使用碳结合来阻止硼外扩散进入基区。例如,众所周知,在富含碳的硅层中可以强烈抑制硼的瞬时增强扩散,可见H.J.Osten等人的“Carbon Doped SiGe Heter junction BipolarTransistors for High Frequency Applications(用于高频领域的掺碳的SiGe异质结双极型晶体管)”,IEEEBTCM 7.1,109。硅中的硼扩散是通过填隙式机理发生,并且与硅自身间隙浓度成比例。从富含碳的区中碳的扩散会引起硅自身间隙的欠饱和。因此,这些区中的硼的扩散就会被抑制。尽管能够抑制硼的扩散,这种仅在SiGe区内的基极上面形成碳的现有技术方法在减少管道短路方面是无效的。
根据上述的双极型管道短路问题,一直存在需要发展一种新的、改善的制造SiGe双极型晶体管的方法的要求,其中无需变窄基极宽度(如现有技术方法中出现的情况),就基本上消除在发射区和集电区之间的位错。
本发明的一个方面是提供了一种制造SiGe双极型晶体管的方法,其中基本抑制了在发射区和集电区之间形成位错,由此避免了双极管道例如CE短路的问题。
本发明的另一个方面是提供了一种制造SiGe双极型结构的方法,其中提高了外延生长硅/锗区的晶体管的产量。
本发明的再一个方面是提供了一种制造双极型SiGe晶体管的方法,其中碳可被加入该结构中而无需变窄基极宽度。
本发明的又一个方面是提供了制造双极型SiGe晶体管的方法,其中成本有效降低,还可以轻松的利用现有的SiGe双极型技术来实现。
本发明的各方面和优点可以通过将碳加入到轻掺杂Si层和SiGe基区中来获得。根据本发明,通过使用淀积工艺,例如超高真空化学汽相淀积(UHVCVD)、快速热化学汽相淀积(RTCVD)、分子束外延(MBE)、或等离子体增强化学汽相淀积(PECVD),在SiGe层的外延生产期间产生碳结合,其中使用碳源气体。通过使用本发明的方法,碳在整个Si集电区和SiGe基区中连续形成。而且,申请人已经发现,本发明的这种方法提高SiGe的增加的产量并且抑制引起双极型管道短路的位错。
在本发明的第一实施例中,提供了一种制造呈现基本没有管道短路的SiGe双极型晶体管的方法。具体而言,制造这种SiGe双极型晶体管的本发明的方法包括下列步骤:
(a)提供一种结构,其至少包括双极型器件区,所述双极型器件区至少包括在半导体衬底内形成的第一导电类型的集电区;
(b)在所述集电区上淀积SiGe基区,其中在所述淀积期间,碳穿过集电区和SiGe基区连续生长;和
(c)在所述SiGe基区上形成图形化的发射区。
更合适的集电极由以下步骤形成:在半导体衬底的一表面上外延生长Si层;在外延生长的Si层上形成氧化层;将第一导电类型的掺杂剂注入进Si层中;去除氧化层,更合适地通过HF刻蚀工艺来去除氧化层。步骤(b)的淀积工艺可以选自于由超高真空化学汽相淀积(UHVCVD)、分子束外延(MBE)、快速热化学汽相淀积(RTCVD)、和等离子体增强化学汽相淀积(PECVD)构成的组,并优选UHVCVD工艺,更优选在约650℃或更低的温度下和大约250毫托或更低的工作压力下执行。UHVCVD工艺优选在从大约500℃-约650℃的温度下并在从大约0.1-约20毫托的工作压力下执行,并且优选包括混合气体,该混合气体包含Si源气体,Ge源气体,B源气体和C源气体。Si源气体优选是硅烷,Ge源气体优选是锗烷,硼源气体优选是B2H6,C源气体优选是乙烯、甲基硅烷(methylsilane)或甲烷。这些源气体可以未稀释使用或是结合惰性气体使用,惰性气体可以是氦、氩、氮或氢。这些源气体可以预混合或作为分开的料流引入到外延反应器内。
适当的上述步骤(c)包括步骤:在SiGe基区上形成绝缘体;在绝缘体内开一个发射极窗口;在发射极窗口中形成多晶硅;刻蚀多晶硅。
本发明的另一实施例涉及一种将碳加入到双极型晶体管的集电区和SiGe基区内的方法。根据本发明的这个实施例,该方法包括在轻掺杂Si集电区上淀积SiGe基区的步骤,其中在淀积期间,碳穿过集电区和SiGe基区连续生长。更适合,淀积步骤包括从由超高真空化学汽相淀积(UHVCVD)、分子束外延(MBE)、快速热化学汽相淀积(RTCVD)、和等离子体增强化学汽相淀积(PECVD)构成的组选择的淀积工艺,最优选淀积工艺是UHVCVD工艺。UHVCVD工艺优选在约650℃或更低的温度下和大约250毫托(millitorr)或更低的工作压力下执行,更优选在从大约500℃-约650℃的温度下和从大约0.1-约20毫托的工作压力下执行。UHVCVD工艺可以包括混合气体,该混合气体包含Si源气体,Ge源气体,B源气体和C源气体,优选其中Si源气体是硅烷,Ge源气体是锗烷,硼源气体是B2H6,C源气体是乙烯、甲基硅烷或甲烷。这些源气体可以未稀释使用或是结合惰性气体使用,惰性气体优选是氦、氩、氮或氢。这些源气体可以预混合或作为分开的料流引入到外延反应器内。
本发明的另一个实施例涉及SiGe双极型晶体管,其在发射区和集电区之间基本没有位错缺陷,所述结构包括:
第一导电类型的集电区;
SiGe基区;和
在所述基区的一部分上形成的所述第一导电类型的发射区,其中所述集电区和所述基区包括在所述集电区和所述SiGe基区内连续存在的碳,并且所述SiGe基区进一步用B掺杂。在SiGe基区内的C优选的浓度是从大约5×1017-约1×1021cm-3,更合适C在SiGe基区中的浓度是从约1×1019-约1×1020cm-3
最合适的SiGe双极型晶体管是其中由掺杂的多晶硅构成发射极。
通过参考附图将更加具体地描述本发明,其中:
图1是现有技术的SiGe双极型晶体管的片段图示。
图2是包括仅在SiGe区内的基极上面生长的C层的现有技术的SiGe双极型晶体管的片段图示。
图3是对于其中在SiGe基区上面加入C的现有技术方法,硼(B)、锗(Ge)和碳(C)的浓度对深度()的曲线图。
图4是包括在集电区和SiGe基区内连续生长的C层的本发明SiGe双极型晶体管的片段图示。
图5-10示出根据本发明的基本工艺步骤的本发明的SiGe双极型晶体管。
图11-13是对于其中在集电区和SiGe基区内连续加入C的本发明方法,硼(B)、锗(Ge)和碳(C)的浓度对深度()的曲线图。
通过结合本发明的附图来更加详细地说明涉及在轻掺杂Si集电区和SiGe基极层内连续加入C的方法和由此产生的SiGe双极型结构的本发明。
首先参考图4,它是本发明SiGe双极型晶体管片段的截面图。具体而言,图4所示的SiGe双极型晶体管包括在衬底50上形成的第一导电类型(掺杂n或p型)的集电区52。在集电区52的一部分的顶部上是SiGe基区54,基区54包括发射区56和发射极扩散56d。区60表示绝缘体。SiGe基区的特征在于用B掺杂。应该注意,图4所示的双极型晶体管仅代表双极型晶体管的一个片段。出于简化目的,该图省略了在双极型晶体管结构中典型形成的其它区。
根据本发明,SiGe基区和集电区(即轻掺杂Si)包括贯穿该双极型晶体管的这些层连续分布(即生长)的C。强调一下,图4所示结构不同于图2所示的其中仅在SiGe基区上面生长C的现有技术SiGe双极型晶体管。
根据本发明,在SiGe基区和集电区内的C的浓度是在从大约5×1017-约1×1021原子cm-3的范围,更加优选的是C浓度范围从大约1×1019-大约1020原子cm-3
形成图4所示本发明结构所使用的方法将通过参考图5-10和下面的讨论做更加详细地描述。具体而言,图5示出在形成SiGe双极型晶体管的本发明中使用的初始结构。图5的结构包括Si衬底50,其包括在衬底50的表面上形成的第一导电类型的集电区52。图5中所示结构可以使用本领域的技术人员熟知的常规工艺来形成。例如,通过在衬底上外延生长Si层(未示出),在衬底10的表面上形成集电区。然后氧化层(该图没有示出)在外延Si层的表面上形成,之后n或p型掺杂剂注入进外延Si层内,通过常规的激活退火工艺来激活该区。离子注入和退火之后,在其上形成SiGe层之前从该结构表面去掉氧化层。上面的过程使得在衬底内形成集电区。去掉氧化层的优选方法是使用HF刻蚀工艺。在形成子集电区过程中本发明中使用的另一个方法是使用常规的高能量P注入工艺。
接下来,如图6所示,使用合适的淀积工艺在集电区上形成SiGe层54,该淀积工艺可以外延生长SiGe基区同时在该基区和集电区内连续生长C。在本发明中形成的SiGe基区典型具有从大约10-约200nm的厚度。更优选的是,该SiGe基区具有从大约50-约70nm的厚度。应该注意,在本发明中,SiGe基区在晶格中包括C和B。也就是,SiGe基区是其中包括SiGe、B和C的合金的SiGe区。
根据本发明,可以通过使用UHVCVD、MBE、RTCVD、PECVD或其它类似的可以外延形成这种SiGe层的淀积工艺来形成SiGe基区层。在这些淀积工艺中,优选使用UHVCVD工艺。
在形成SiGe基区的本发明中使用的UHCVD工艺在低温外延(LTE)反应器中执行,外延反应器在大约650℃或更低的温度下和大约250毫托或更低的工作压力下工作。更优选的,该UHVCVD工艺在从大约500℃-约650℃的温度下和从大约0.1-约20毫托的工作压力下工作的外延反应器中执行。在本发明中,UHVCVD工艺可以用混合气体执行,该混合气体包含Si源,Ge源,B源和C源。尽管在本发明中可以使用各种Si、Ge、B和C源,但是优选使用混合气体,该混合气体包括硅烷或其它类似的含Si的源气体作为Si源,锗烷、GeH4作为Ge源,乙硼烷、B2H6作为B源,和乙烯、甲基硅烷或甲烷作为C源。前面提及的C源中,最优选使用乙烯作为C源气体。
这些源气体可以未稀释使用或者源气体可以结合例如氦、氮、氩或氢的惰性气体使用。例如,Ge源气体可以包括5%惰性气体中的锗烷,C源气体可以包括惰性气体中的上述C源气体中的一种(约0.5-约2%)。而且,这些源气体可以在引入外延反应器内之前预混合,或者这些源气体可以作为分开的料流被引入。
在本发明中使用的Si和Ge的浓度对于本发明来说不是至关重要的,只要Si和Ge的浓度足够形成SiGe基区层即可。
注意,上述的UHVCVD工艺(或有关的淀积工艺)能够贯穿双极型结构的基区和SiGe基区连续生长C。而且,申请人已发现,上述的UHVCVD工艺改善了SiGe基极的产量并抑制了引起双极型管道短路的位错。而仅在SiGe基区上面生长C的现有技术工艺中没有报道这些发现。因此,本发明的工艺提供了一种形成SiGe双极型晶体管的改进方法,其中C基本形成一个本征沉(intrinsic sink)。
图11-13示出在UHVCVD淀积外延生长SiGe基区和Si集电区加入C的工艺的SiGe轮廓图。图11中,在隔开SiGe基区和轻掺杂Si层(即集电极)的离散间隔内生长碳;图12中,碳贯穿这些区连续地形成。轻掺杂的Si中低浓度的C用作减少位错形成的本征沉。C的加入限制了Ge轮廓,因此,如图13所示,Ge轮廓有坡度并且不是固定的。
返回来参看本发明的工艺,如图7所示,使用本领域公知的常规淀积工艺在SiGe膜的表面形成绝缘体60。适合的淀积工艺包括但不限于:CVD,等离子体增强CVD,溅射,化学溶液淀积,和其它类似的淀积工艺。绝缘体60可以包括单一的绝缘材料,或它也可以包括一种以上的绝缘材料的组合,即,介质叠层。在本发明的这个步骤中使用的绝缘体可以包括氧化物、氮化物或它们的组合。
图8示出了穿过绝缘体60形成发射极窗口62之后,露出SiGe膜表面的结构。使用常规的光刻和例如反应离子刻蚀(RIE)的刻蚀来形成发射极窗口。
图9示出了在发射极窗口内和绝缘体层上面形成本征多晶硅64层之后的结构。形成双极型SiGe晶体管的发射区的本征多晶硅可以由本领域的技术人员熟知的任何常规原位掺杂淀积工艺来形成。
在该结构中形成多晶硅层之后,用常规光刻和刻蚀对该多晶硅层进行构图,形成图10所示的结构。然后执行能够去掉部分绝缘体和部分SiGe层的选择性刻蚀工艺,以提供图4所示的结构。本发明的方法也可以应用于本领域公知的工艺,例如自对准双极型工艺。
尽管已经通过优选实施例具体示出和描述了本发明,但是本领域的技术人员都明白,在不脱离本发明的精神和范围的情况下可以进行形式和细节方面的前述和其它变化。因此,本发明并不局限于所描述和示出的具体的形式和细节,本发明由附属的权利要求所保护。

Claims (27)

1.一种制造SiGe双极型晶体管的方法,该SiGe双极型晶体管包括在集电区和SiGe基区中的碳,其方法包括下列步骤:
(a)提供一种结构,其至少包括一双极型器件区,所述双极型器件区至少包括在半导体衬底内形成的第一导电类型的集电区;
(b)在所述集电区上淀积SiGe基区,其中在所述淀积期间,碳穿过集电区和SiGe基区连续生长;和
(c)在所述SiGe基区上面形成图形化的发射区。
2.根据权利要求1的方法,其中通过以下步骤形成集电极:
在半导体衬底的一表面上外延生长Si层;
在外延生长的Si层上形成氧化层;
将第一导电类型的掺杂剂注入Si层中;和
去除氧化层。
3.根据权利要求2的方法,其中通过HF刻蚀工艺来去除氧化层。
4.根据权利要求1的方法,其中步骤(b)的淀积工艺选自于由超高真空化学汽相淀积、分子束外延、快速热化学汽相淀积、和等离子体增强化学汽相淀积构成的组。
5.根据权利要求4的方法,其中淀积工艺是超高真空化学汽相淀积工艺。
6.根据权利要求5的方法,其中所述超高真空化学汽相淀积工艺在650℃或更低的温度下和250毫托或更低的工作压力下执行。
7.根据权利要求6的方法,其中所述超高真空化学汽相淀积工艺在从500℃-650℃的温度下和从0.1-20毫托的工作压力下执行。
8.根据权利要求5的方法,其中所述超高真空化学汽相淀积工艺包括混合气体,该混合气体包含Si源气体,Ge源气体,B源气体和C源气体。
9.根据权利要求8的方法,其中所述Si源气体是硅烷,Ge源气体是锗烷,硼源气体是B2H6,和C源气体是乙烯、甲基硅烷或甲烷。
10.根据权利要求8的方法,其中所述源气体可以未稀释使用或是结合惰性气体使用。
11.根据权利要求10的方法,其中所述惰性气体是氦、氩或氮。
12.根据权利要求8的方法,其中所述源气体被预混合或作为分开的料流引入到外延反应器内。
13.根据权利要求1的方法,其中步骤(c)包括以下步骤:在SiGe基区上形成绝缘体;在绝缘体内开一发射极窗口;在发射极窗口中形成多晶硅;和刻蚀多晶硅。
14.一种将碳加入到双极型晶体管的集电区和SiGe基区内的方法,该方法包括在Si集电区上淀积SiGe基区,其中在淀积期间,碳穿过集电区和SiGe基区连续生长。
15.根据权利要求14的方法,其中所述淀积步骤包括选自由超高真空化学汽相淀积、分子束外延、快速热化学汽相淀积和等离子体增强化学汽相淀积构成的组中的淀积工艺。
16.根据权利要求15的方法,其中所述淀积工艺是超高真空化学汽相淀积工艺。
17.根据权利要求16的方法,其中所述超高真空化学汽相淀积工艺在650℃或更低的温度下和250毫托或更低的工作压力下执行。
18.根据权利要求17的方法,其中所述超高真空化学汽相淀积工艺在从500℃-650℃的温度下和从0.1-20毫托的工作压力下执行。
19.根据权利要求16的方法,其中所述超高真空化学汽相淀积工艺包括混合气体,该混合气体包含Si源气体,Ge源气体,B源气体和C源气体。
20.根据权利要求19的方法,其中所述Si源气体是硅烷,Ge源气体是锗烷,硼源气体是B2H6,和C源气体是乙烯、甲基硅烷或甲烷。
21.根据权利要求19的方法,其中所述源气体可以未稀释使用或是结合惰性气体使用。
22.根据权利要求21的方法,其中所述惰性气体是氦、氩或氮。
23.根据权利要求19的方法,其中所述源气体被预混合或作为分开的料流引入到外延反应器内。
24.一种SiGe双极型晶体管,所述结构包括:
第一导电类型的集电区;
在集电区的一部分上形成的SiGe基区;和
在所述基区的一部分上形成的第一导电类型的发射区,其中所述集电区和所述基区包括在所述集电区和SiGe基区内连续存在的碳,和所述SiGe基极进一步包括其中掺杂的硼。
25.根据权利要求24的SiGe双极型晶体管,其中在SiGe基区内的C的浓度是5×1017-1×1021cm-3
26.根据权利要求25的SiGe双极型晶体管,其中在SiGe基区内的C的浓度是1×1019-1×1020cm-3
27.根据权利要求24的SiGe双极型晶体管,其中发射极由掺杂的多晶硅构成。
CNB018223753A 2001-01-30 2001-11-23 硅锗双极型晶体管 Expired - Lifetime CN1322564C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/774,126 2001-01-30
US09/774,126 US6426265B1 (en) 2001-01-30 2001-01-30 Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology

Publications (2)

Publication Number Publication Date
CN1502124A CN1502124A (zh) 2004-06-02
CN1322564C true CN1322564C (zh) 2007-06-20

Family

ID=25100308

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018223753A Expired - Lifetime CN1322564C (zh) 2001-01-30 2001-11-23 硅锗双极型晶体管

Country Status (11)

Country Link
US (4) US6426265B1 (zh)
EP (1) EP1356504A1 (zh)
JP (2) JP4700897B2 (zh)
KR (1) KR100497103B1 (zh)
CN (1) CN1322564C (zh)
CZ (1) CZ20032066A3 (zh)
HU (1) HUP0302872A3 (zh)
IL (2) IL156930A0 (zh)
PL (1) PL203317B1 (zh)
TW (1) TW522494B (zh)
WO (1) WO2002061820A1 (zh)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426265B1 (en) * 2001-01-30 2002-07-30 International Business Machines Corporation Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
US6534371B2 (en) * 2001-06-11 2003-03-18 International Business Machines Corporation C implants for improved SiGe bipolar yield
US6649482B1 (en) * 2001-06-15 2003-11-18 National Semiconductor Corporation Bipolar transistor with a silicon germanium base and an ultra small self-aligned polysilicon emitter and method of forming the transistor
US6784065B1 (en) 2001-06-15 2004-08-31 National Semiconductor Corporation Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor
US7087979B1 (en) * 2001-06-15 2006-08-08 National Semiconductor Corporation Bipolar transistor with an ultra small self-aligned polysilicon emitter
WO2003012840A2 (de) * 2001-07-27 2003-02-13 Ihp Gmbh-Innovations For High Performance Microelectronics/Institut Für Innovative Mikroelektronik Verfahren und vorrichtung zum herstellen dünner epitaktischer halbleiterschichten
US6706583B1 (en) * 2001-10-19 2004-03-16 Lsi Logic Corporation High speed low noise transistor
KR20030035152A (ko) * 2001-10-30 2003-05-09 주식회사 하이닉스반도체 반도체웨이퍼 제조방법
US6870204B2 (en) * 2001-11-21 2005-03-22 Astralux, Inc. Heterojunction bipolar transistor containing at least one silicon carbide layer
DE10160509A1 (de) * 2001-11-30 2003-06-12 Ihp Gmbh Halbleitervorrichtung und Verfahren zu ihrer Herstellung
US20030111013A1 (en) * 2001-12-19 2003-06-19 Oosterlaken Theodorus Gerardus Maria Method for the deposition of silicon germanium layers
JP3914064B2 (ja) * 2002-02-28 2007-05-16 富士通株式会社 混晶膜の成長方法及び装置
US6593640B1 (en) * 2002-04-01 2003-07-15 Maxim Integrated Products, Inc. Bipolar transistor and methods of forming bipolar transistors
TWI284348B (en) * 2002-07-01 2007-07-21 Macronix Int Co Ltd Method for fabricating raised source/drain of semiconductor device
US6699765B1 (en) * 2002-08-29 2004-03-02 Micrel, Inc. Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer
US6972441B2 (en) * 2002-11-27 2005-12-06 Intel Corporation Silicon germanium heterojunction bipolar transistor with step-up carbon profile
US6995427B2 (en) * 2003-01-29 2006-02-07 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same
US7517768B2 (en) * 2003-03-31 2009-04-14 Intel Corporation Method for fabricating a heterojunction bipolar transistor
DE10316531A1 (de) * 2003-04-10 2004-07-08 Infineon Technologies Ag Bipolar-Transistor
US7157379B2 (en) * 2003-09-23 2007-01-02 Intel Corporation Strained semiconductor structures
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US20050114227A1 (en) * 2003-11-25 2005-05-26 Carter Craig M. Web-based tool for maximizing value from surplus assets
US7115955B2 (en) * 2004-07-30 2006-10-03 International Business Machines Corporation Semiconductor device having a strained raised source/drain
US7312128B2 (en) * 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
US7682940B2 (en) * 2004-12-01 2010-03-23 Applied Materials, Inc. Use of Cl2 and/or HCl during silicon epitaxial film formation
US7560352B2 (en) * 2004-12-01 2009-07-14 Applied Materials, Inc. Selective deposition
KR100833491B1 (ko) * 2005-12-08 2008-05-29 한국전자통신연구원 임베디드 상변화 메모리 및 그 제조방법
US7674337B2 (en) * 2006-04-07 2010-03-09 Applied Materials, Inc. Gas manifolds for use during epitaxial film formation
JP5175285B2 (ja) * 2006-07-31 2013-04-03 アプライド マテリアルズ インコーポレイテッド エピタキシャル層形成中の形態制御方法
CN103981568A (zh) * 2006-07-31 2014-08-13 应用材料公司 形成含碳外延硅层的方法
US8394196B2 (en) * 2006-12-12 2013-03-12 Applied Materials, Inc. Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon
US7960236B2 (en) * 2006-12-12 2011-06-14 Applied Materials, Inc. Phosphorus containing Si epitaxial layers in N-type source/drain junctions
JP2008235560A (ja) 2007-03-20 2008-10-02 Matsushita Electric Ind Co Ltd ヘテロ接合バイポーラトランジスタ
US8130737B2 (en) * 2008-03-12 2012-03-06 Samsung Electronics Co., Ltd. System and method for a multiple hop wireless network
US8476686B2 (en) * 2008-07-09 2013-07-02 Infineon Technologies Ag Memory device and method for making same
US8343825B2 (en) 2011-01-19 2013-01-01 International Business Machines Corporation Reducing dislocation formation in semiconductor devices through targeted carbon implantation
US9064796B2 (en) 2012-08-13 2015-06-23 Infineon Technologies Ag Semiconductor device and method of making the same
US10236282B2 (en) 2013-12-18 2019-03-19 Intel Corporation Partial layer transfer system and method
CN103943670B (zh) * 2014-04-12 2016-10-05 北京工业大学 超结集电区应变硅异质结双极晶体管
JP6473269B2 (ja) * 2016-02-29 2019-02-20 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置、およびプログラム
CN107046058A (zh) * 2017-04-13 2017-08-15 中国电子科技集团公司第二十四研究所 一种具有应变Si组合发射区的异质结双极晶体管及其制备方法
FR3115393A1 (fr) 2020-10-19 2022-04-22 Stmicroelectronics (Crolles 2) Sas Transistor bipolaire et procédé de fabrication

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19652423A1 (de) * 1996-12-09 1998-06-10 Inst Halbleiterphysik Gmbh Silizium-Germanium-Heterobipolartransistor und Verfahren zur Herstellung der epitaktischen Einzelschichten eines derartigen Transistors

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4887134A (en) 1986-09-26 1989-12-12 Canon Kabushiki Kaisha Semiconductor device having a semiconductor region in which either the conduction or valence band remains flat while bandgap is continuously graded
US5514885A (en) * 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
JP2569058B2 (ja) * 1987-07-10 1997-01-08 株式会社日立製作所 半導体装置
US5159424A (en) 1988-12-10 1992-10-27 Canon Kabushiki Kaisha Semiconductor device having a high current gain and a higher ge amount at the base region than at the emitter and collector region, and photoelectric conversion apparatus using the device
US5140400A (en) * 1989-03-29 1992-08-18 Canon Kabushiki Kaisha Semiconductor device and photoelectric converting apparatus using the same
US5316958A (en) * 1990-05-31 1994-05-31 International Business Machines Corporation Method of dopant enhancement in an epitaxial silicon layer by using germanium
US5321302A (en) 1990-07-25 1994-06-14 Nec Corporation Heterojunction bipolar transistor having base structure for improving both cut-off frequency and maximum oscillation frequency
JPH04106980A (ja) * 1990-08-24 1992-04-08 Fujitsu Ltd 半導体装置及びその製造方法
JPH05144834A (ja) 1991-03-20 1993-06-11 Hitachi Ltd バイポーラトランジスタ及びその製造方法
US5241214A (en) * 1991-04-29 1993-08-31 Massachusetts Institute Of Technology Oxides and nitrides of metastabale group iv alloys and nitrides of group iv elements and semiconductor devices formed thereof
JPH05102177A (ja) * 1991-10-02 1993-04-23 Hitachi Ltd 半導体集積回路装置及びこれを用いた電子計算機
EP0609351A4 (en) 1991-10-23 1995-01-04 Microunity Systems Eng BOPOLAR TRANSISTOR WITH IMPROVED CURRENT GAIN AND BREAKTHROUGH CHARACTERISTICS.
JPH05198787A (ja) * 1991-11-08 1993-08-06 Canon Inc 固体撮像装置及びその製造方法
JP3077841B2 (ja) * 1992-01-20 2000-08-21 日本電気株式会社 半導体装置およびその製造方法
JP2582519B2 (ja) 1992-07-13 1997-02-19 インターナショナル・ビジネス・マシーンズ・コーポレイション バイポーラ・トランジスタおよびその製造方法
US5272096A (en) * 1992-09-29 1993-12-21 Motorola, Inc. Method for making a bipolar transistor having a silicon carbide layer
US5523243A (en) * 1992-12-21 1996-06-04 International Business Machines Corporation Method of fabricating a triple heterojunction bipolar transistor
US5320972A (en) 1993-01-07 1994-06-14 Northern Telecom Limited Method of forming a bipolar transistor
JP3156436B2 (ja) * 1993-04-05 2001-04-16 日本電気株式会社 ヘテロ接合バイポーラトランジスタ
JPH0750410A (ja) 1993-08-06 1995-02-21 Hitachi Ltd 半導体結晶積層体及びその形成方法並びに半導体装置
JPH07115184A (ja) * 1993-08-24 1995-05-02 Canon Inc 積層型固体撮像装置及びその製造方法
US5360986A (en) * 1993-10-05 1994-11-01 Motorola, Inc. Carbon doped silicon semiconductor device having a narrowed bandgap characteristic and method
JPH07153928A (ja) * 1993-11-26 1995-06-16 Toshiba Corp 半導体基板およびその製造方法
US5422502A (en) * 1993-12-09 1995-06-06 Northern Telecom Limited Lateral bipolar transistor
US5734193A (en) * 1994-01-24 1998-03-31 The United States Of America As Represented By The Secretary Of The Air Force Termal shunt stabilization of multiple part heterojunction bipolar transistors
US5646073A (en) 1995-01-18 1997-07-08 Lsi Logic Corporation Process for selective deposition of polysilicon over single crystal silicon substrate and resulting product
KR970054343A (ko) * 1995-12-20 1997-07-31 이준 규소/규소게르마늄 쌍극자 트랜지스터 제조방법
US5846867A (en) * 1995-12-20 1998-12-08 Sony Corporation Method of producing Si-Ge base heterojunction bipolar device
US6800881B2 (en) * 1996-12-09 2004-10-05 Ihp Gmbh-Innovations For High Performance Microelectronics/Institut Fur Innovative Mikroelektronik Silicon-germanium hetero bipolar transistor with T-shaped implantation layer between emitter and emitter contact area
DE19755979A1 (de) * 1996-12-09 1999-06-10 Inst Halbleiterphysik Gmbh Silizium-Germanium-Heterobipolartransistor
US5963817A (en) 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6154475A (en) * 1997-12-04 2000-11-28 The United States Of America As Represented By The Secretary Of The Air Force Silicon-based strain-symmetrized GE-SI quantum lasers
EP1178537A3 (en) * 1998-02-20 2004-09-29 Matsushita Electric Industrial Co., Ltd. Bipolar transistor and semiconductor device
JPH11283993A (ja) * 1998-03-31 1999-10-15 Mitsubishi Heavy Ind Ltd 半導体装置の製造方法
US6815303B2 (en) * 1998-04-29 2004-11-09 Micron Technology, Inc. Bipolar transistors with low-resistance emitter contacts
FR2779571B1 (fr) * 1998-06-05 2003-01-24 St Microelectronics Sa Procede de dopage selectif du collecteur intrinseque d'un transistor bipolaire vertical a base epitaxiee
US6087683A (en) * 1998-07-31 2000-07-11 Lucent Technologies Silicon germanium heterostructure bipolar transistor with indium doped base
JP2000068284A (ja) * 1998-08-19 2000-03-03 Sharp Corp ヘテロ接合バイポーラトランジスタの製造方法及びパワーアンプ
JP3549408B2 (ja) * 1998-09-03 2004-08-04 松下電器産業株式会社 バイポーラトランジスタ
DE19857640A1 (de) * 1998-12-14 2000-06-15 Inst Halbleiterphysik Gmbh Bipolartransistor und Verfahren zu seiner Herstellung
EP1020900B1 (en) * 1999-01-14 2009-08-05 Panasonic Corporation Semiconductor device and method for fabricating the same
US6258695B1 (en) * 1999-02-04 2001-07-10 International Business Machines Corporation Dislocation suppression by carbon incorporation
DE60042045D1 (de) * 1999-06-22 2009-06-04 Panasonic Corp Heteroübergangsbipolartransistoren und entsprechende Herstellungsverfahren
US6169007B1 (en) * 1999-06-25 2001-01-02 Applied Micro Circuits Corporation Self-aligned non-selective thin-epi-base silicon germanium (SiGe) heterojunction bipolar transistor BicMOS process using silicon dioxide etchback
DE60036594T2 (de) * 1999-11-15 2008-01-31 Matsushita Electric Industrial Co., Ltd., Kadoma Feldeffekt-Halbleiterbauelement
US6461925B1 (en) * 2000-03-30 2002-10-08 Motorola, Inc. Method of manufacturing a heterojunction BiCMOS integrated circuit
US6316795B1 (en) * 2000-04-03 2001-11-13 Hrl Laboratories, Llc Silicon-carbon emitter for silicon-germanium heterojunction bipolar transistors
US6333235B1 (en) * 2000-04-12 2001-12-25 Industrial Technologyresearch Institute Method for forming SiGe bipolar transistor
US6417058B1 (en) * 2000-06-14 2002-07-09 Sony Corporation SiGe/poly for low resistance extrinsic base npn transistor
WO2002015560A2 (en) 2000-08-12 2002-02-21 Georgia Tech Research Corporation A system and method for capturing an image
US6894366B2 (en) * 2000-10-10 2005-05-17 Texas Instruments Incorporated Bipolar junction transistor with a counterdoped collector region
US6396107B1 (en) * 2000-11-20 2002-05-28 International Business Machines Corporation Trench-defined silicon germanium ESD diode network
US6440811B1 (en) * 2000-12-21 2002-08-27 International Business Machines Corporation Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme
US6509242B2 (en) * 2001-01-12 2003-01-21 Agere Systems Inc. Heterojunction bipolar transistor
US6674102B2 (en) * 2001-01-25 2004-01-06 International Business Machines Corporation Sti pull-down to control SiGe facet growth
US6465870B2 (en) * 2001-01-25 2002-10-15 International Business Machines Corporation ESD robust silicon germanium transistor with emitter NP-block mask extrinsic base ballasting resistor with doped facet region
US6426265B1 (en) * 2001-01-30 2002-07-30 International Business Machines Corporation Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
US6534371B2 (en) * 2001-06-11 2003-03-18 International Business Machines Corporation C implants for improved SiGe bipolar yield

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19652423A1 (de) * 1996-12-09 1998-06-10 Inst Halbleiterphysik Gmbh Silizium-Germanium-Heterobipolartransistor und Verfahren zur Herstellung der epitaktischen Einzelschichten eines derartigen Transistors

Also Published As

Publication number Publication date
US20020121676A1 (en) 2002-09-05
EP1356504A1 (en) 2003-10-29
TW522494B (en) 2003-03-01
JP2008153684A (ja) 2008-07-03
US6815802B2 (en) 2004-11-09
US7713829B2 (en) 2010-05-11
KR100497103B1 (ko) 2005-06-23
KR20030069215A (ko) 2003-08-25
US20050054171A1 (en) 2005-03-10
PL203317B1 (pl) 2009-09-30
HUP0302872A3 (en) 2004-07-28
CN1502124A (zh) 2004-06-02
US6426265B1 (en) 2002-07-30
WO2002061820A1 (en) 2002-08-08
HUP0302872A2 (hu) 2003-12-29
US20080124881A1 (en) 2008-05-29
US20020100917A1 (en) 2002-08-01
PL362710A1 (en) 2004-11-02
CZ20032066A3 (cs) 2003-11-12
JP4917051B2 (ja) 2012-04-18
JP2004520711A (ja) 2004-07-08
IL156930A0 (en) 2004-02-08
IL156930A (en) 2010-04-15
US7173274B2 (en) 2007-02-06
JP4700897B2 (ja) 2011-06-15

Similar Documents

Publication Publication Date Title
CN1322564C (zh) 硅锗双极型晶体管
US7605060B2 (en) Method of epitaxial deoposition of an n-doped silicon layer
JP4060580B2 (ja) ヘテロ接合バイポーラトランジスタ
US7183576B2 (en) Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
US5834800A (en) Heterojunction bipolar transistor having mono crystalline SiGe intrinsic base and polycrystalline SiGe and Si extrinsic base regions
US6218254B1 (en) Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices
US5620907A (en) Method for making a heterojunction bipolar transistor
US20010011729A1 (en) Self-aligned bipolar junction silicon carbide transistors
JP2004520711A5 (zh)
JP2003297844A (ja) 半導体装置,及び,半導体装置の製造方法
KR20030028483A (ko) 실리콘 바이폴라 트랜지스터, 실리콘 바이폴라트랜지스터의 회로 장치 및 제조 방법
JP3515944B2 (ja) ヘテロバイポーラトランジスタ
JP2000077425A (ja) バイポーラトランジスタ
US7012009B2 (en) Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process
EP0779652A2 (en) Method for making a heterojunction bipolar transistor
KR100518561B1 (ko) 단결정 실리콘층에의 저메인 가스 전처리를 포함하는바이폴라 소자 제조 방법 및 이에 의한 바이폴라 소자
JP4823154B2 (ja) へテロ接合バイポーラトランジスタ
WO2004077570A1 (ja) バイポーラトランジスタおよび集積回路装置
Oda et al. Ultra-Low-Power SiGe HBTs using High-Precision RT-CVD Epitaxial Growth
WO2003092079A1 (en) Enhanced cutoff frequency silicon germanium transistor
JPH021933A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171030

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171030

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20070620

CX01 Expiry of patent term