CN1324713C - Silicon nitride read only memory structure possessing protection diode and its operation method - Google Patents
Silicon nitride read only memory structure possessing protection diode and its operation method Download PDFInfo
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- CN1324713C CN1324713C CNB021074488A CN02107448A CN1324713C CN 1324713 C CN1324713 C CN 1324713C CN B021074488 A CNB021074488 A CN B021074488A CN 02107448 A CN02107448 A CN 02107448A CN 1324713 C CN1324713 C CN 1324713C
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- silicon nitride
- doped region
- substrate
- guard ring
- diode
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Abstract
The present invention relates to a silicon nitride read only memory structure provided with a protection diode. The structure is composed of a base, a silicon nitride read only memory unit, an N#+[+] doping region, an N#+[+] protection ring and a polysilicon protection ring, wherein the silicon nitride read only memory unit is positioned on the base, the N#+[+] doping region is positioned in the base and electrically contacts a character line of the silicon nitride read only memory unit, the N#+[+] protection ring is positioned in the base which surrounds the N#+[+] doping region, and the polysilicon protection ring is positioned on the base between the N#+[+] doping region and the N#+[+] protection ring.
Description
Technical field
The invention relates to the structure of a kind of non-voltile memory (Non-Volatile Memory) element, and particularly relevant for a kind of silicon nitride read only memory structure and method of operation thereof with protection diode.
Background technology
Erasable removing and programmable read only memory (ElectricallyErasable Programmable Read Only Memory in the non-voltile memory, EEPROM) has the actions such as depositing in, read, wipe that to carry out repeatedly data, and the advantage that the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of memory element of extensively adopting.
Typical erasable removing and the polysilicon making floating grid (Floating Gate) and control grid (Control Gate) of programmable read only memory to mix.When internal memory carried out sequencing (Program), the voltage of proper procedureization was added to respectively on source area, drain region and the control grid, and electronics will flow to the drain region via channel (Channel) by source area.In this process, to there be electronics partly can pass the tunnel oxide (Tunneling Oxide) of polysilicon floating gate layer below, and enter in the polysilicon floating gate layer, and can be uniformly distributed in the whole polysilicon floating gate layer, this kind electronics passes through the phenomenon that tunnel oxide enters the polysilicon floating gate layer, is called tunneling effect (Tunneling Effect).Erasable remove and the general operation mechanism of programmable read only memory is to carry out sequencing with above-mentioned channel hot electron (Channel Hot-Electron Injection) mechanism, and utilize Fowler-Nordheim tunnelling (F-N Tunneling) effect to wipe.But, if the tunnel oxide defectiveness (Defect) of polysilicon floating gate layer below exists, then cause the leakage current of element easily, influence the reliability of element.
Tradition is erasable to be removed and the problem of programmable read only memory element leakage current in order to solve, and known a kind of method is to utilize an electric charge capture layer to replace polysilicon floating gate at present, and the material of electric charge capture layer for example is a silicon nitride.And form a kind of EEPROM by silicon oxide/silicon nitride/silicon oxide (ONO) stacking-type (Stacked) grid structure that composite bed constituted.Because the material of electric charge capture layer is a silicon nitride, so this kind EEPROM is also referred to as silicon nitride ROM (NROM).Because silicon nitride layer has the effect of catching electric charge, can't be uniformly distributed in whole silicon nitride layer so inject the electronics of silicon nitride layer, but concentrate on the regional area of silicon nitride layer in the mode of Gaussian Profile.Only concentrate on local zone owing to flow into the electronics of silicon nitride layer, therefore less for the susceptibility of its defective of tunnel oxide, the phenomenon of element leakage current is difficult for taking place.
Yet, in the manufacture process of general silicon nitride ROM, because the influence of process environments, for example use plasma (Plasma) etc. will make electric charge move along metal, so-called antenna effect (Antenna Effect) takes place, the charge unbalance of moment, Partial charge will be absorbed in silicon oxide/silicon nitride/silicon oxide (ONO) composite bed, cause read-only memory element to form the phenomenon of uneven sequencing (Program), and then cause the excessive problem of distribution (0.3 volt to 0.9 volt) of start voltage.
In order to address the above problem, known a kind of method that antenna effect causes read-only memory element sequencing problem that solves is to form the diode (N that links to each other with the character line electricity in substrate
+Doped region), when the moment in the diode, electric charge reached certain value, then the mode by the electricity collapse was released into electric charge in the substrate.Yet the silicon nitride ROM element with this kind structure when carrying out sequencing or read operation, can be higher than diode (N owing to bestow the bias voltage of character line
+Doped region) puncture voltage, the bias voltage of therefore bestowing character line can be because of diode (N
+Doped region) electricity collapses and reduces, and then influences the speed of element operation (write/erase).
Summary of the invention
Therefore; a purpose of the present invention is to provide silicon nitride read only memory structure and the method for operation thereof with protection diode; by protection diode, with the phenomenon of damage of silicon oxide/silicon nitride/silicon oxide (ONO) composite bed that prevents silicon nitride ROM or sequencing with variable puncture voltage.
Another object of the present invention is to provide silicon nitride read only memory structure and method of operation thereof with protection diode; utilization has the protection diode of variable puncture voltage; make silicon nitride ROM when carrying out sequencing or read operation, can not reduce the voltage of input, and influence the speed of element operation (write/erase).
The invention provides a kind of silicon nitride read only memory structure with protection diode, this structure is by substrate, silicon nitride ROM memory cell, N
+Doped region, N
+Guard ring and polysilicon protection ring constitute, wherein substrate, N
+Doped region, N
+Guard ring and polysilicon protection ring constitute a protection diode.The silicon nitride ROM memory cell is positioned in the substrate.N
+Doped region is arranged in substrate, and N
+One character line of doped region and silicon nitride ROM memory cell electrically contacts.N
+Guard ring is positioned at around N
+In the substrate of doped region.The polysilicon protection ring is positioned at N
+Doped region and N
+In the substrate between the guard ring.
The present invention provides a kind of method of operation with silicon nitride ROM of protection diode in addition, and wherein protecting diode structure is by a N
+Doped region, a N
+A guard ring and a polysilicon protection ring constitute.N
+Doped region is arranged in substrate, and N
+Doping electrically contacts with a character line of silicon nitride ROM memory cell.N
+Guard ring is positioned at around N
+In the substrate of doped region.The polysilicon protection ring is positioned at N
+Doped region and N
+In the substrate between the guard ring.The method is when carrying out programming operations, applies one first positive voltage in character line, adds one second positive voltage in the polysilicon protection circulating application, and makes N
+Guard ring is floated.When carrying out read operation, apply one the 3rd positive voltage, add the 4th positive voltage in the polysilicon protection circulating application, and make N in character line
+Guard ring is floated.When carrying out erase operation, apply one the 5th positive voltage in a N-well of silicon nitride ROM memory cell.
The present invention imports diode (N by the metal interconnect with the electric charge that last part technology produced
+And diode (N doped region),
+Doped region) puncture voltage for example is 3 volts to 5 volts.Therefore, moment, unbalanced electric charge can be flowed away by substrate, can avoid being absorbed in the problem that is caused in the silicon nitride layer (electric charge capture layer) of silicon oxide/silicon nitride/silicon oxide (ONO) composite bed because of electric charge.
And the present invention is in diode (N
+Doped region) forms N around
+Guard ring, and in N
+Guard ring and diode (N
+Doped region) forms the polysilicon protection ring in the substrate between.When the sequencing of carrying out the silicon nitride ROM memory cell or read operation, on the polysilicon protection ring, apply a positive bias, make diode (N
+Doped region) meet the facial contour cunning that flattens, modulation diode (N
+Doped region) puncture voltage improves its puncture voltage.So the silicon nitride ROM of protection diode structure with variable puncture voltage of the present invention is in when operation, can't reduces the voltage of input and make sequencing or the speed that reads slack-off.
In addition, the present invention is with at diode (N
+Doped region) forms a N on every side
+Guard ring can certainly be in diode (N
+Doped region) forms plural N on every side
+Guard ring is so that diode (N
+The modulation scope of puncture voltage doped region) is more extensive.
Description of drawings
Fig. 1 is a kind of vertical view with protection diode of variable puncture voltage according to the embodiment of the invention illustrated;
Fig. 2 is a kind of profile with silicon nitride read only memory structure of variable puncture voltage protection diode according to the embodiment of the invention illustrated;
Fig. 3 is a kind of sequencing of the silicon nitride ROM with protection diode or the schematic diagram of read operation according to the embodiment of the invention illustrated; And
Fig. 4 is a kind of schematic diagram with erase operation of the silicon nitride ROM of protecting diode according to the embodiment of the invention illustrated.
Description of reference numerals:
100: substrate
The 102:N-well
The 104:P-well
106: electric charge capture layer
108: gate conductor layer (character line)
110: diode (N
+Doped region)
112: the polysilicon protection ring
114:N
+Guard ring
116,118,120: connector
122,124,128: lead
126: interlayer hole
C1, C2: connect facial contour
Embodiment
A kind of silicon nitride read only memory structure and method of operation thereof with variable puncture voltage protection diode that the present invention is illustrated please be simultaneously with reference to Fig. 1 and Fig. 2, in order to describe embodiments of the invention in detail.Fig. 1 is a kind of vertical view with protection diode of variable puncture voltage according to the embodiment of the invention illustrated.And Fig. 2 is a kind of profile with silicon nitride read only memory structure of variable puncture voltage protection diode according to the embodiment of the invention illustrated.
At first, please refer to Fig. 1 and Fig. 2, the silicon nitride read only memory structure with variable puncture voltage protection diode of the present invention comprises substrate 100, N-well 102, P-well 104, electric charge capture layer 106, gate conductor layer 108 (character line), diode (N
+Doped region) 110, polysilicon protection ring (Poly Guard Ring) 112, N
+Guard ring 114, connector 116, connector 118, connector 120, lead 122 and 124, interlayer hole 126 and lead 128 constitute.
The above-mentioned explanation structure with protection diode of variable puncture voltage of the present invention.Illustrate that then the present invention has the method for operation of structure of the protection diode of variable puncture voltage.
Please refer to Fig. 2, finish non-voltile memory contain the last part technology of plasma the time, can electric charge that technology produced imported diode (N by connector 116, lead 122 and connector 118
+Doped region) 110 (among the figure shown in the arrow), and diode (N
+Doped region) 110 puncture voltage for example is 3 volts to 5 volts.Therefore, electric charge when moment reaches certain value (3 volts to 5 volts), then the mode by the electricity collapse discharges electric charge, and electric charge is flowed into the substrate 100 from the joint wedge angle (Junction Comer) that meets facial contour C1, can avoid being absorbed in the problem that is caused in the electric charge capture layer 106 because of electric charge.
Please refer to Fig. 3, when the silicon nitride ROM memory cell is carried out programming operations, normally utilize channel hot electron to inject (Channel Hot Electron Injection, CHEI) effect is carried out, and need bestow gate conductor layer 108 (character line) positive bias, this positive bias for example is about 6 volts to 9 volts.Yet when to bestow gate conductor layer 108 for example be 6 volts to 9 volts positive bias, at diode (N
+Doped region) 110 puncture voltage must be adjusted to greater than the bias voltage of bestowing gate conductor layer 108, and it for example is about 7 volts to 10 volts, otherwise the electric current of bestowing gate conductor layer 108 is understood some and imported diode (N through lead 122 and connector 118
+Doped region) in 110, and imports in the substrate 100, cause the sequencing speed of silicon nitride ROM slack-off in electricity collapse mode.Therefore, bestow one by lead 124 and connector 120 and be biased on the polysilicon protection ring 112, this bias voltage for example is about 8 volts to 11 volts, and makes N
+Guard ring 114 is floated.So, diode (N
+Doped region) 110 meet facial contour C1 and can enlarge to become and meet facial contour C2 and make to engage the wedge angle cunning that flattens, diode (N
+Doped region) 110 puncture voltage will change over about 7 volts to 10 volts, and therefore when carrying out the silicon nitride ROM sequencing, the bias voltage of bestowing gate conductor layer 108 (character line) just can not be via diode (N
+Doped region) 110 flows in the substrate 100, can keep the sequencing speed of silicon nitride ROM.
When carrying out the read operation of silicon nitride ROM memory cell, need bestow gate conductor layer 108 (character line) positive bias usually, this positive bias for example is about 2 volts to 4 volts.Yet when to bestow gate conductor layer 108 for example be 2 volts to 4 volts positive bias, at diode (N
+Doped region) 110 puncture voltage must be adjusted to greater than the bias voltage of bestowing gate conductor layer 108, and it for example is about 7 volts to 10 volts, otherwise the electric current of bestowing gate conductor layer 108 can import diode (N through lead 122 and connector 118
+Doped region) in 110, and through the electricity collapse and import in the substrate 100, cause the reading speed of silicon nitride ROM slack-off.Therefore, bestow one by lead 124 and connector 120 and be biased on the polysilicon protection ring 112, this bias voltage for example is about 8 volts to 11 volts, and makes N
+Guard ring 114 is floated.So, diode (N
+Doped region) 110 meet facial contour C1 and can become to become greatly and meet facial contour C2 and make and engage the wedge angle cunning that flattens, diode (N
+Doped region) 110 puncture voltage will change over 7 volts about 10 volts, and therefore when carrying out the data read of silicon nitride ROM, the bias voltage of bestowing gate conductor layer 108 (character line) just can not be via diode (N
+Doped region) 110 flows in the substrate 100, can keep the data reading speed of silicon nitride ROM.
Please refer to Fig. 4, when carrying out the erase operation of silicon nitride ROM memory cell, normally utilize hot hole between valence band-conduction band (Band to Band Hot Hole) effect from bit line with data erase, and need bestow N-well 102 1 positive biases, this positive bias for example is about 5 volts, makes 104 in gate conductor layer 108 to P-wells produce a negative voltage.Because diode (N
+Doped region) 110 puncture voltage does not need to adjust, and therefore not needing to bestow one is biased into polysilicon protection ring 112.
Described according to the foregoing description, the present invention imports diode (N by the metal interconnect with the electric charge that technology produced in the last part technology that contains plasma
+And diode (N doped region),
+Doped region) puncture voltage for example is 3 volts to 5 volts.Therefore, moment, unbalanced electric charge can be flowed away by substrate 100, can avoid being absorbed in the problem that is caused in the silicon nitride layer (electric charge capture layer) of silicon oxide/silicon nitride/silicon oxide (ONO) composite bed 106 because of electric charge.
And the present invention is in diode (N
+Doped region) forms N around
+Guard ring, and in N
+Guard ring and diode (N
+Doped region) forms the polysilicon protection ring in the substrate between.When the sequencing of carrying out the silicon nitride ROM memory cell or read operation, on the polysilicon protection ring, apply a positive bias, make diode (N
+Doped region) connect the facial contour cunning that flattens, improve diode (N
+Doped region) puncture voltage.So the silicon nitride ROM of protection diode structure with variable puncture voltage of the present invention is in when operation, can't reduces the voltage of input and make sequencing or the speed that reads slack-off.
In addition, in the foregoing description with at diode (N
+Doped region) forms a N on every side
+Guard ring can certainly be in diode (N
+Doped region) forms plural N on every side
+Guard ring is so that diode (N
+Doped region) puncture voltage more improves.
Though the present invention with embodiment explanation as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claims.
Claims (11)
1. one kind has the silicon nitride read only memory structure of protecting diode, and it is characterized by: this structure comprises:
One substrate has a silicon nitride ROM memory cell in this substrate;
One N
+Doped region, this N
+Doped region is arranged in this substrate, and this N
+One character line of doped region and this silicon nitride ROM memory cell electrically contacts;
One the one N
+Guard ring, a N
+Guard ring is positioned at around this N
+In this substrate of doped region; And
One polysilicon protection ring, this polysilicon protection ring is positioned at this N
+A doped region and a N
+In this substrate between the guard ring.
2. the silicon nitride read only memory structure with protection diode as claimed in claim 1, it is characterized by: wherein this silicon nitride ROM memory cell comprises a silicon oxide/silicon nitride/silicon oxide composite bed.
3. the silicon nitride read only memory structure with protection diode as claimed in claim 1 is characterized by: wherein at least also comprise one the 2nd N
+Guard ring, the 2nd N
+Guard ring is positioned at around a N
+In this substrate of guard ring.
4. method of operation of silicon nitride ROM with protection diode, it is characterized by: this protection diode structure comprises a N
+Doped region, a N
+Guard ring and a polysilicon protection ring, wherein this N
+Doped region is arranged in a substrate, and this N
+One character line of a doped region and a silicon nitride ROM memory cell electrically contacts; This N
+Guard ring is positioned at around this N
+In this substrate of doped region; This polysilicon protection ring is positioned at this N
+Doped region and this N
+In this substrate between the guard ring; This method comprises:
When carrying out programming operations, apply one first positive voltage in this character line;
Add one second positive voltage in this polysilicon protection circulating application; And
Make this N
+Guard ring is floated.
5. the method for operation with silicon nitride ROM of protection diode as claimed in claim 4, it is characterized by: wherein this first positive voltage is 6 volts to 9 volts.
6. the method for operation with silicon nitride ROM of protection diode as claimed in claim 4, it is characterized by: wherein this second positive voltage is 8 volts to 11 volts.
7. method of operation of silicon nitride ROM with protection diode, it is characterized by: this protection diode structure comprises a N
+Doped region, a N
+Guard ring and a polysilicon protection ring, wherein this N
+Doped region is arranged in a substrate, and this N
+One character line of a doped region and a silicon nitride ROM memory cell electrically contacts; This N
+Guard ring is positioned at around this N
+In this substrate of doped region; This polysilicon protection ring is positioned at this N
+Doped region and this N
+In this substrate between the guard ring; This method comprises:
When carrying out read operation, apply one the 3rd positive voltage in this character line;
Add the 4th positive voltage in this polysilicon protection circulating application; And
Make this N
+Guard ring is floated.
8. the method for operation with silicon nitride ROM of protection diode as claimed in claim 7, it is characterized by: wherein the 3rd positive voltage is 2 volts to 4 volts.
9. the method for operation with silicon nitride ROM of protection diode as claimed in claim 7, it is characterized by: wherein the 4th positive voltage is 8 volts to 11 volts.
10. method of operation of silicon nitride ROM with protection diode, it is characterized by: this protection diode structure comprises a N
+Doped region, a N
+Guard ring and a polysilicon protection ring, wherein this N
+Doped region is arranged in a substrate, and this N
+One character line of a doped region and a silicon nitride ROM memory cell electrically contacts; This N
+Guard ring is positioned at around this N
+In this substrate of doped region; This polysilicon protection ring is positioned at this N
+Doped region and this N
+In this substrate between the guard ring; This method comprises:
When carrying out erase operation, the N-well in this silicon nitride ROM memory cell below applies one the 5th positive voltage.
11. the method for operation with silicon nitride ROM of protection diode as claimed in claim 10, it is characterized by: wherein the 5th positive voltage is 5 volts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021074488A CN1324713C (en) | 2002-03-19 | 2002-03-19 | Silicon nitride read only memory structure possessing protection diode and its operation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021074488A CN1324713C (en) | 2002-03-19 | 2002-03-19 | Silicon nitride read only memory structure possessing protection diode and its operation method |
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| Publication Number | Publication Date |
|---|---|
| CN1445857A CN1445857A (en) | 2003-10-01 |
| CN1324713C true CN1324713C (en) | 2007-07-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021074488A Expired - Fee Related CN1324713C (en) | 2002-03-19 | 2002-03-19 | Silicon nitride read only memory structure possessing protection diode and its operation method |
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|---|---|
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7755129B2 (en) * | 2005-08-15 | 2010-07-13 | Macronix International Co., Ltd. | Systems and methods for memory structure comprising a PPROM and an embedded flash memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5861347A (en) * | 1997-07-03 | 1999-01-19 | Motorola Inc. | Method for forming a high voltage gate dielectric for use in integrated circuit |
| US6030871A (en) * | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
-
2002
- 2002-03-19 CN CNB021074488A patent/CN1324713C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5861347A (en) * | 1997-07-03 | 1999-01-19 | Motorola Inc. | Method for forming a high voltage gate dielectric for use in integrated circuit |
| US6030871A (en) * | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
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| Publication number | Publication date |
|---|---|
| CN1445857A (en) | 2003-10-01 |
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