CN1326207C - 在具有均匀错配位错密度的弛豫SiGe膜上的应变硅 - Google Patents

在具有均匀错配位错密度的弛豫SiGe膜上的应变硅 Download PDF

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CN1326207C
CN1326207C CNB2004100581152A CN200410058115A CN1326207C CN 1326207 C CN1326207 C CN 1326207C CN B2004100581152 A CNB2004100581152 A CN B2004100581152A CN 200410058115 A CN200410058115 A CN 200410058115A CN 1326207 C CN1326207 C CN 1326207C
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D·奇丹巴尔拉奥
O·H·多库马奇
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

本发明提供一种形成半导体衬底结构的方法。在硅衬底上形成压应变的SiGe层。将原子离子注入SiGe层以引起排列末端损伤。进行退火以弛豫应变的SiGe层。退火期间，在SiGe层中形成均匀分布的填隙位错环。填隙位错环提供在SiGe层和硅衬底之间的错配位错的成核基础。由于填隙位错环均匀分布，因此错配位错也均匀分布，从而弛豫了SiGe层。在弛豫SiGe层上形成张应变的硅层。

Description

在具有均匀错配位错密度的弛豫SiGe膜上的应变硅
技术领域
本发明涉及具有改进的器件性能的半导体器件的制造方法，特别涉及弛豫SiGe膜的形成方法。
背景技术
对超大规模集成半导体器件的需求的不断提高，要求不断提高晶体管的性能和密度。随着器件小型化达到极限，现在的趋势是寻求增强器件性能的新材料和方法。提高性能的最直接方法之一是通过增强迁移率。现已知，施加到半导体晶格结构的应力或应变可以提高器件的性能。例如，在双轴应变的(例如扩展的晶格)硅衬底上形成的N型器件，显示出器件性能好于在没有应变(或者扩展的晶格结构)的硅衬底上形成的其它N型器件。同样，具有纵向(电流流动的方向)压应变的P型器件，显示出器件性能好于在没有这种应变的硅衬底上形成的其它P型器件。具有很大双轴张应变的P型器件也显示出增强的性能。
可选地，现已知，当在外延生长于已在硅衬底的顶部上弛豫的另一外延生长的SiGe层上的硅层(或帽盖)上形成器件时，器件显示出更好的性能特性。在该系统中，硅帽盖经受双轴张应变。当在硅上外延生长时，未弛豫SiGe层将具有适应于硅衬底的晶格常数。弛豫(例如通过高温工艺)时，SiGe的晶格常数接近它自身的晶格常数，该晶格常数大于硅的晶格常数。完全弛豫SiGe层具有接近它自身的值的晶格常数。当在其上外延生长硅层时，硅层适应于弛豫SiGe层的较大的晶格常数，并将物理双轴应力(例如扩展)施加到在其上形成的硅层。施加到硅层的该物理应力对在其上形成的器件(例如，CMOS器件)有利，因为扩展的硅层提高了N型器件性能，且SiGe层中较高的Ge浓度提高了P型器件性能。
通过形成错配位错引起硅衬底上SiGe的弛豫。对于完全弛豫衬底，可以想象等间距隔开的错配位错的栅格，释放了应力。通过在衬底中提供硅的额外半平面(extra half plane)，错配位错有助于SiGe层中的晶格常数寻求它自身的值。穿越SiGe/硅界面的失配应变被适应，且允许SiGe晶格常数变得更大。
然而，该常规措施的问题在于它要求很厚(例如，厚度为约5000到15000)的多层SiGe缓冲层，以在它的表面部分上获得错配位错，同时避免SiGe层和硅衬底层之间的螺旋位错，由此在多层SiGe层的表面上获得弛豫SiGe结构。同样，该措施显著地增加了制造时间和成本。而且，厚的分级的SiGe缓冲层不容易应用于衬底上硅(SOI)。这是由于为了有利于SOI有效，对于绝缘体上硅，硅的厚度必须低于1500。SiGe缓冲层结构太厚。
另一问题是在SiGe层和硅外延层之间形成的错配位错，是随机的且高度不均匀，并由于不容易控制的非均匀成核造成不容易控制。同样，各个不同位置处的错配位错密度也显著不同。由此，在硅外延层中由不均匀的错配位错产生的物理应力易于高度不均匀，且该不均匀的应力对性能产生不均匀的影响，使性能具有较大的易变性。而且，在错配密度很高的这些位置处，各种缺陷通过使器件端子短路和通过其它显著的泄露机制，而降低了器件性能。
因此，需要制造弛豫SiGe层的有效方法。
发明内容
在本发明的一个方案中，提供一种制造半导体器件的方法。首先，在硅衬底上形成压应变的SiGe层。离子注入原子以在SiGe层中形成均匀分布的填隙位错环。进行退火以在SiGe-硅界面形成均匀分布的错配位错。
在本发明的另一方案中，提供一种形成半导体衬底的方法。在硅衬底上形成压应变的SiGe层。将原子可控地离子注入SiGe层以在其中引起均匀分布的排列末端(end-of-range)损伤。进行退火以在SiGe层中形成均匀分布的填隙位错环。均匀分布的填隙位错环使SiGe层中均匀分布的错配位错成核。在SiGe层上形成张应变的硅层。
本发明的再一方案是具有硅衬底的半导体器件。在硅衬底上形成弛豫SiGe层，且SiGe层包括均匀分布的错配位错。在弛豫SiGe层上形成张应变的硅层。
附图说明
从下面参考附图的本发明的优选实施例的详细说明中，可以更好地理解以上和其它优点，其中：
图1到4示出了根据本发明的实施例的方法的顺序阶段；以及
图5示出了进行退火之后图3所示的半导体器件结构的侧视图。
具体实施方式
本发明提供了形成张应变的硅层的方法，改善了在其上形成的器件的性能。通过在弛豫SiGe层上外延生长硅形成应变的硅层。通过在形成于硅衬底之上的初始为压应变的SiGe层中形成均匀分布的错配位错，形成弛豫SiGe层。填隙位错环严重地影响了错配位错的成核。由此，在本发明中，在SiGe层中希望的位置，以希望的密度形成填隙位错环，以便控制SiGe层中错配位错成核的位置和密度。从而，通过错配位错的成核弛豫压应变的SiGe层。由于SiGe层被弛豫，因此在其上形成的硅层扩展地适应于弛豫SiGe层的较大晶格常数。结果，硅层为双轴张应变，由此提高了在其上形成的器件的性能。
图1示出了在硅衬底10上形成的SiGe层12。在一个实施例中，通过外延生长形成厚度为约100到10000的SiGe层12。由此，与现有技术相反，本发明不需要形成厚的多层SiGe层以获得弛豫SiGe层。硅衬底10具有小于自身的未弛豫SiGe层的晶格常数。由此，当外延生长SiGe层12时，SiGe层12为双轴压应变，因为下面的硅层限制了外延生长，以使SiGe层12的较大晶格结构适应于硅衬底10的较小晶格结构。
在图2中，以足以使SiGe层12的上表面部分非晶化的注入浓度和能量，将原子可控地离子注入SiGe层12，如箭头“A”所示。如Ge或Si的任何中性非晶化原子可以用做离子注入原子。由此，在SiGe层12的上表面区域形成非晶层14。在一个实施例中，形成的非晶层14的厚度为约30到300，约为SiGe层厚度的三分之一。也可以使用如He、Ar等的惰性气体代替Ge或Si，但是用量必须很高，会导致其它不希望的泄露问题。
离子注入期间，原子与SiGe层12的晶格结构碰撞并引起非晶化。在一个实施例中，为了非晶化，以约3×1014原子/cm2的杂质浓度离子注入Ge。退火非晶化的硅/SiGe材料时，形成了对SiGe层12的排列末端损伤。排列末端损伤由接合退火期间的损伤的填隙环组成。它们相对稳定并具有约100到500的尺寸，并具有相对均匀的密度。
从非晶区14和SiGe层12之间的界面向下到SiGe层12和硅衬底10之间的界面，在SiGe层12中嵌有排列末端损伤。通过控制离子注入浓度和能量可以准确地调制排列末端损伤的位置。由此，当离子注入原子形成非晶层14时，可控地选择注入浓度和能量，以使在SiGe层12中的排列末端损伤均匀分布。例如，以约1×1014原子/cm2到1×1016原子/cm2的注入浓度及约5KeV到100KeV的注入能量离子注入原子。下面将说明，排列末端损伤提供了错配位错的成核基础。
随后，进行退火，用于非晶层14的再结晶。在一个实施例中，在约500℃到1100℃的温度下进行约1秒到30分钟的退火。同样，可以通过峰值退火、快速热退火或其它退火技术进行退火。如图3所示，进行退火时，对应于排列末端损伤，形成排列末端填隙位错环16。在一个实施例中，排列末端填隙位错环16的密度为约1×105环/cm2到1×1012环/cm2。
在退火SiGe层12并再结晶非晶层14时，释放施加到SiGe层12的压应变，并使SiGe层12得到弛豫，如图3中的箭头“B”所示。当应变的SiGe层12得到弛豫时，SiGe层12的弛豫，在SiGe层12和硅衬底10之间的界面处引起错配位错。这里，当产生错配位错时，排列末端填隙位错环16提供了错配位错的成核基础。由此，在希望的位置并以希望的密度均匀分布的排列末端填隙位错环16的严重影响之下，使错配位错18成核。
在一个实施例中，SiGe层中的错配位错的密度为约1×105#/cm2到1×1012#/cm2。图4示出了一个例子，其中沿连接两个相邻的排列末端填隙位错环16的线，均匀形成错配位错18。图4还示出了形成均匀地弛豫压应力的栅格的错配位错18。根据本发明，通过产生更多的错配位错可以增加弛豫。这可以通过增加排列末端填隙位错环16的密度来实现，因为错配位错的成核主要受排列末端填隙位错环16的支配。
图5示出了在弛豫SiGe层12上形成的硅层20。在一个实施例中，通过在SiGe层12上外延生长形成硅层20。由于弛豫SiGe层12具有大于硅的晶格常数，因此在SiGe层12上形成的硅层20，适应于弛豫SiGe层12的较大的晶格常数。这将双轴张应变施加到硅层20。
虽然没有示出，但是进行常规的工艺步骤，在双轴张应变的硅层20上形成器件。例如，在硅层20上形成栅极结构，二者之间具有栅极氧化物。通过离子注入杂质原子在张应变的硅层20中形成源和漏区。张应变的硅层相当于衬底，并提高了器件性能。
在上述实施例中，在衬底10上形成SiGe层12之后离子注入原子。然而，可以在形成SiGe层12之前将原子离子注入硅衬底10。可选地，可以在SiGe层12上形成硅层20之后进行离子注入。在这些情况中，硅弛豫的程度仍然会增加硅弛豫。
如前所述，根据本发明，由于下层SiGe层12的弛豫，硅层20为张应变。通过在压应变的SiGe层12中形成均匀分布的错配位错引起弛豫。由于在排列末端填隙位错环16的严重影响下使错配位错成核，在本发明中，在希望的位置并以希望的密度形成了排列末端填隙位错环16。通过可控地离子注入原子实现填隙位错环16的均匀分布，以形成对SiGe层的均匀分布的排列末端损伤。同样，本发明不需要形成厚的多层SiGe层以避免螺旋位错。因此，本发明提供了制造张应变硅层的时间和成本有效的方法。
虽然借助实施例说明了本发明，但是本领域的技术人员应该认识到，在所附的权利要求书的精神和范围内，可以对本发明进行修改。

Claims (20)

1.一种制造半导体器件的方法，包括以下步骤：
在硅衬底上形成压应变的SiGe层；
离子注入原子以在SiGe层中形成均匀分布的填隙位错环；以及
退火以在SiGe层中形成均匀分布的错配位错。
2.根据权利要求1的方法，其中形成SiGe层的步骤包括在硅衬底上外延生长SiGe层的步骤。
3.根据权利要求2的方法，其中形成厚度为100到10000的SiGe层。
4.根据权利要求1的方法，还包括在SiGe层上形成张应变的硅层的步骤。
5.根据权利要求1的方法，其中离子注入原子的步骤引起在SiGe层中的排列末端损伤。
6.根据权利要求1的方法，其中离子注入原子的步骤引起在SiGe层的表面部分中形成非晶层。
7.根据权利要求1的方法，其中原子为Ge或Si。
8.根据权利要求1的方法，其中以1×1014原子/cm2到1×1016原子/cm2的注入浓度及5KeV到100KeV的注入能量离子注入原子。
9.根据权利要求1的方法，其中在500℃到1100℃的温度下进行1秒到30分钟的退火步骤。
10.根据权利要求1的方法，其中填隙位错环的密度为1×105环/cm2到1×1012环/cm2。
11.根据权利要求10的方法，其中错配位错的密度为1×105#/cm2到1×1012#/cm2。
12.一种形成半导体衬底的方法，包括以下步骤：
在硅衬底上形成压应变的SiGe层；
将原子可控地离子注入SiGe层，以在其中引起均匀分布的排列末端损伤；
退火以在SiGe层中形成均匀分布的填隙位错环，其中均匀分布的填隙位错环使SiGe层中均匀分布的错配位错成核；以及
在SiGe层上形成张应变的硅层。
13.根据权利要求12的方法，其中离子注入原子的步骤引起在SiGe层的表面部分中形成非晶层。
14.根据权利要求12的方法，其中原子为Ge或Si。
15.根据权利要求12的方法，其中以1×1014原子/cm2到1×1016原子/cm2的注入浓度及5KeV到100KeV的注入能量离子注入原子。
16.根据权利要求12的方法，其中在500℃到1100℃的温度下进行1秒到30分钟的退火步骤。
17.一种半导体器件，包括：
硅衬底；
在硅衬底上形成弛豫SiGe层，所述SiGe层包括均匀分布的错配位错；以及
在弛豫SiGe层上形成张应变的硅层。
18.根据权利要求17的方法，其中在SiGe层中错配位错的密度为1×105#/cm2到1×1012#/cm2。
19.根据权利要求17的方法，其中从上面看时，错配位错排列为栅格形状。
20.根据权利要求17的方法，其中形成厚度为100到10000的SiGe层。
CNB2004100581152A 2003-09-23 2004-08-13 在具有均匀错配位错密度的弛豫SiGe膜上的应变硅 Expired - Fee Related CN1326207C (zh)

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US10/667,603 US6872641B1 (en) 2003-09-23 2003-09-23 Strained silicon on relaxed sige film with uniform misfit dislocation density

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