CN1326225A - 芯片倒装型半导体器件及其制造方法 - Google Patents
芯片倒装型半导体器件及其制造方法 Download PDFInfo
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- CN1326225A CN1326225A CN01116178A CN01116178A CN1326225A CN 1326225 A CN1326225 A CN 1326225A CN 01116178 A CN01116178 A CN 01116178A CN 01116178 A CN01116178 A CN 01116178A CN 1326225 A CN1326225 A CN 1326225A
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Abstract
一种芯片倒装型半导体器件,其配备的半导体芯片的表面上有多个焊盘电极。焊料电极与各个焊盘电极连接,金属芯柱与各个焊料电极连接。在半导体芯片中含有焊盘电极的一侧表面上涂覆绝缘树脂层,焊盘电极和焊料电极的全部以及金属芯柱的一部分埋入该绝缘树脂层内。金属芯柱的其余部分从绝缘树脂层伸出以形成凸起。形成外层焊料电极以覆盖此凸起。使凸起的高度为外层焊料电极的一端与绝缘树脂层表面之间距离的7%到50%。
Description
本发明涉及一种芯片倒装型半导体器件及其制造方法。具体来说,本发明涉及一种能够回收利用半导体芯片且具有极好的安装可靠性的芯片倒装型半导体器件以及其制造方法。
在芯片倒装型半导体器件中,凸出的凸起由一种如焊料、Au、Sn-Ag合金或类似材料的金属材料形成,它形成于在半导体芯片周围中形成的外部端子或者在有源区域的一个预定区域阵列中形成的外部端子上。这种芯片倒装型半导体器件被最终用户安装在一个多层布线板上,其中在此多层布线板上电极焊点被按照与芯片倒装型半导体器件上的凸起一样的图案排列。当采用焊料作为一种凸起材料以用于将芯片倒装型半导体器件安装在多层布线板上时,键合工作通常是由一种IR(红外线)软熔过程来实现的,在此过程中使用了焊剂,并且凸起被加热到一预定的温度。
但是,当芯片倒装型半导体器件被安装在多层布线板上时,由于多层布线板与芯片倒装型半导体器件的线性膨胀系数不同,所以会出现应力扭曲。因此,在芯片倒装型半导体器件与凸起之间的接口上就会发生断裂。这样,安装可靠性、尤其是芯片倒装型半导体器件的温度循环特性就会变差。另外,在安装时,由于半导体芯片上还被施加了热应力和机械应力,所以半导体芯片、尤其是钝化膜及钝化膜下的有效区域表面将受到破坏。
为了解决这些问题,曾有这样一种技术被提出,即,采用AlN(氮化铝)、高铝红柱石、玻璃陶瓷或类似物作为多层布线板的材料以使多层布线板的材料与硅的线性膨胀系数之间的差异最小化,从而使应力扭曲最小化,这样,提高了安装的可靠性。
虽然这种技术提高了安装可靠性,但是,它的一个问题在于成本太高,因为它采用了昂贵的玻璃陶瓷材料来作为多层布线板的材料。所以,在一般情况下,这种技术的应用只限于昂贵的超级计算机或大规模计算机的制造当中。
另一方面,近年来,有一种技术正在得到广泛采用,在这种技术中,一种具有高线性膨胀系数且价格相对便宜的有机材料被用作多层布线板的材料,然后一种未充满的树脂被置于此多层布线板与一个半导体芯片之间。在此技术中,将未充满的树脂置入半导体芯片与由有机材料构成的多层布线板之间可以分散在半导体芯片和多层布线板之间的凸起键合部分施加的剪切应力。籍此就可提高安装的可靠性。这种技术允许使用由便宜的有机材料构成的多层布线板。
但是,上述使用未充满的树脂的技术具有以下问题。
首先,它很难重新利用半导体芯片。由于高性能LSI(大规模集成电路)通常都被用作芯片倒装型半导体芯片,而半导体芯片本身较贵。因此,如果一个半导体芯片被安装在多层布线板上,随后在电子筛选过程中检测到该半导体芯片以外的一个其它部分中存在缺陷,则需要回收和重新使用此无缺陷的半导体芯片。例如,如果在焊料凸出部分中检测到有缺陷的键合,则需剥离此半导体芯片并再次进行键合。但是,在芯片倒装型半导体器件的上述结构中,回收半导体芯片在技术上是困难的,因为在半导体芯片与安装板之间已经注入了未充满的树脂。
图1A和1B的截面图显示出了一种在多层布线板上安装传统半导体器件的方法。如图1A所示,外层焊料电极13被形成在半导体芯片24的底面上。图1B显示了半导体芯片24的一种安装状态。如图1B所示,半导体芯片24通过焊料凸起的熔化而被安装和键合在安装板25上,同时外层焊料电极13被置于安装板25的电极部分(未示出)上。一种未充满的树脂26被注入到半导体芯片24与安装板25之间。即,外层焊料电极13被埋设在此未充满的树脂26当中。
图1C的截面图显示出了一种半导体芯片24的回收方法。为了回收半导体芯片24,如图1C所示,半导体芯片24的后表面受到一个用于修理的加热/抽吸工具27的抽吸并且同时受到加热。然后,当凸起键合部分熔化时,就可将半导体芯片24拔起。这样,就可将无缺陷的半导体芯片24从安装板25中移走。
图2的截面图显示出了当传统芯片倒装型半导体器件中的半导体芯片被从安装板25中移走以后的情况。如图2所示,当芯片被从具有未充满的树脂的半导体器件中移走时就会出现问题,即,外层焊料电极13仍被埋设在未充满的树脂26中,未充满的树脂26和安装板25也受到了损坏。因此,该无缺陷的半导体芯片24就不能够被重新利用。由于上述原因,所以用常规技术很难对无缺陷的芯片倒装型半导体芯片进行重新利用。
其次,如果在未充满的树脂26中存在气隙或者未充满的树脂26与半导体芯片24之间的接口和未充满的树脂26与安装板25之间的接口的键合特性不良,则在产品的吸湿回熔过程中将会引发脱落现象,因此无缺陷的产品就变成了有缺陷的。
第三,由于当半导体芯片24被回收时经历了一个高温加热过程,因而被移走的半导体芯片24的阻挡层金属键合部分和外层焊料电极13以及钝化膜(未示出)都将受到破坏。所以,一个无缺陷的半导体芯片也可能变成有缺陷的。形成钝化膜的目的是为了保护半导体芯片24的有效区域,该钝化膜由PI(聚酰亚胺)有机材料或诸如SiO材料的无机材料(如SiO、SiO2)等构成。另外,由于施加到外层焊料电极13上的热负载和机械负荷被传输到半导体芯片24,所以一个无缺陷的半导体芯片24也可能变成有缺陷的。在这种情况下,包括安装板25在内的外围器件也有可能变得有缺陷。
因此,实际上,使用有机材料作为多层布线板的材料并不能降低成本。
当采用一种陶瓷多层布线板时,回收一个无缺陷的半导体芯片就相对容易一些,因为从优化陶瓷材料的线性膨胀系数的角度考虑,它不需要使用未充满的树脂。
本发明的一个目的是提供一种低成本的芯片倒装型半导体器件及其制造方法,这种器件无需使用未充满的树脂,由于它能够防止因半导体芯片与焊料凸起之间的交界处的热应力而造成的断裂,所以其安装可靠性极好,而且在这种器件中,半导体芯片也能得到回收。
根据本发明所述的芯片倒装型半导体器件包括:带有焊盘电极的半导体芯片,覆盖在半导体芯片表面带有焊盘电极的一侧上的绝缘树脂层;穿透绝缘树脂层并与焊盘电极相连的金属芯柱以及位于绝缘树脂层表面上并与金属芯柱相连的电极。上述金属芯柱具有一个埋设在绝缘树脂层之中的第一部分,以及一个从绝缘树脂层凸出的第二部分。注意,本发明中所提到的“金属”不仅仅是纯金属,也包括合金。
在本发明中,因为没有使用未充满的树脂,所以可对已安装的半导体芯片进行回收。另外,由于没有使用未充满的树脂,所以就不会出现因未充满的树脂的气隙或未充满的树脂与半导体芯片或安装板之间有缺陷的键合而造成的脱落现象。还有,绝缘树脂层和金属芯柱被置于半导体芯片的焊盘电极与暴露在外部的电极之间。金属芯柱的端头从绝缘树脂层表面向外伸出。因此,由金属芯柱和绝缘树脂层组成的层就可作为一个应力缓解层,从而防止了外露的电极上所承受的热负载和机械负荷传递到芯片上。另外,由于金属芯柱和与其相接触的外层焊料电极之间的接触面积较大,而且因水平应力及其传播所造成的断裂而使外层焊料电极产生的损坏也可得到防止,所以金属芯柱与外层焊料电极之间的键合强度就可增加。这样也使芯片倒装型半导体器件的安装可靠性得到提高。因此,本发明提供了一种能够在不使用昂贵的陶瓷衬底情况下回收利用半导体芯片且具有极好的安装可靠性的芯片倒装型半导体器件。
在这种芯片倒装型半导体器件中,上述第一和第二部分的质心在平面图中被相互分开。因此,金属芯柱可被分成两个部分。所以,通过金属芯柱传递给半导体芯片的热量和机械负荷就可得到进一步的减小,并且上述效果将得到进一步的增强。
在根据本发明所述的一种用于制造芯片倒装型半导体器件的方法中,在金属衬底的表面上形成多个凹槽部分,并且在各个凹槽部分的表面上形成有金属芯柱。然后,该金属芯柱与半导体芯片的一个焊盘电极连接起来,通过在金属衬底与半导体芯片之间的空间内注入一种绝缘树脂,就可形成一个绝缘树脂层,然后金属衬底被移走并且电极就形成在金属芯柱上。
在根据本发明所述的另一种用于制造芯片倒装型半导体器件的方法中,金属衬底的第一表面上形成有多个凸出部分,与形成在第一表面上的凸出部分相对应的多个凸出部分被形成在金属衬底的第二表面上,并且形成在第一表面的多个凸出部分与半导体芯片的焊盘电极相互连接起来。然后,通过在金属衬底与半导体芯片之间的空间内注入一种绝缘树脂,就可形成绝缘树脂层,通过去除凸出部分以外的金属衬底,就可分出凸出部分,并且电极被在形成于金属衬底的第二表面上的凸出部分之上形成。
这样,可以有效地制造上述芯片倒装型半导体器件。
可通过在待形成凸出部分的位置上形成一层用于遮掩区域的抗蚀剂,并利用此抗蚀剂作为一个掩模来对金属衬底进行腐蚀,从而形成上述多个凸出部分。
图1A和1B的截面图显示了一种在多层布线板上安装一个传统半导体器件的方法;
图1C的截面图显示了一种回收半导体芯片的传统方法;
图2的截面图显示了当传统芯片倒装型半导体器件中的半导体芯片被从安装板中移走以后的情况;
图3是根据本发明第一实施例的一种芯片倒装型半导体器件的截面图;
图4是从外层焊料电极一侧看去所得到的根据第一实施例的芯片倒装型半导体器件的平面图;
图5A至5K的截面图按照制造过程的步骤显示了根据本发明第一实施例的一种用于制造芯片倒装型半导体器件的方法;
图6是根据本发明第二实施例的一种芯片倒装型半导体器件的截面图;
图7A至7F的截面图按照制造过程的步骤显示了根据本发明第二实施例的一种用于制造芯片倒装型半导体器件的方法;
图8是根据本发明第三实施例的一种芯片倒装型半导体器件的截面图;
图9A和9B的截面图按照制造过程的步骤显示了根据本发明第三实施例的一种用于制造芯片倒装型半导体器件的方法;
图10是根据本发明第四实施例的一种芯片倒装型半导体器件的截面图;
图11是从外层焊料电极侧看去所得到的根据第四实施例的芯片倒装型半导体器件的平面图;
图12A至12G的截面图按照制造过程的步骤显示了根据本发明第四实施例的一种用于制造芯片倒装型半导体器件的方法;
图13是根据本发明第五实施例的一种芯片倒装型半导体器件的截面图;
图14A至14C的截面图按照制造过程的步骤显示了根据本发明第五实施例的一种用于制造芯片倒装型半导体器件的方法;
图15是根据本发明第六实施例的一种芯片倒装型半导体器件的截面图;
图16是从外层焊料电极侧看去所得到的根据第六实施例的芯片倒装型半导体器件的平面图;
图17A至17F的截面图按照制造过程的步骤显示了根据本发明第六实施例的一种用于制造芯片倒装型半导体器件的方法;
图18A至18F的截面图按照制造过程的步骤显示了根据本发明第七实施例的一种用于制造芯片倒装型半导体器件的方法;
图19A和19B的截面图按照制造过程的步骤显示了根据本发明第八实施例的一种用于制造芯片倒装型半导体器件的方法;
下面将参考附图对本发明的各个实施例进行详细说明。根据第一实施例所述的芯片倒装型半导体器件的构成、制造方法及效果将在以下得到说明。首先,先对根据第一实施例的芯片倒装型半导体器件的构成进行说明。
图3是根据本发明第一实施例的一种芯片倒装型半导体器件的截面图。在根据本实施例的芯片倒装型半导体器件中,半导体芯片10的一个表面上配有多个焊盘电极31,并且焊料电极9被与各个焊盘电极31相连接。各个焊料电极9上还连接有一个金属芯柱8。绝缘树脂层11被涂覆在半导体芯片形成有焊盘电极31的一侧表面上。而且焊盘电极31和焊料电极9的全部以及金属芯柱8的一部分被埋设在绝缘树脂层11内。金属芯柱8的剩余部分从绝缘树脂层11凸出,从而形成了一个凸起12。在金属芯柱8的凸起12上涂有第二层镀膜7和第一层镀膜6。外层焊料电极13与第一层镀膜6连接。形成外层焊料电极13覆盖凸起12。
图4是从外层焊料电极13一侧观察到的根据第一实施例所述的芯片倒装型半导体器件的平面图。如图4所示,在这种芯片倒装型半导体器件中,外层焊料电极13被以阵列的形式排列在绝缘树脂层11上。
在本实施例中,例如,焊料电极9的高度被做成约为100μm,金属芯柱8的高度被做成约为100μm,金属芯柱埋设在绝缘树脂层11之内部分的高度被做成约为80μm,其从绝缘树脂层11表面凸出部分的高度被做成约为20μm。外层焊料电极13高度被做成约为100μm,并且金属芯柱的直径被做成约为(例如)150μm。另外,半导体芯片10的厚度被做成约为(例如)50至725μm。
以下将对根据本实施例所述的一种用于制造芯片倒装型半导体器件的方法进行说明。图5A至5K的截面图按照制造过程的步骤显示了一种用于制造根据本发明第一实施例所述的芯片倒装型半导体器件的方法。如图5A和5B所示,在金属衬底1a的一个表面上形成有一层抗蚀剂2a。金属衬底1a的材料不受特殊限制,但最好采用铜、镍、金、锡、铅、含有这些元素的42号合金等易于在以后被腐蚀的材料。金属衬底1a的厚度也没有特殊限制,但最好采用能够尽量小地影响腐蚀并且易于控制的厚度。接下来,如图5C所示,抗蚀剂2a受到曝光并被显影以形成一个具有预定孔径的经过构图的抗蚀剂层4a。然后,如图5D所示,通过利用此抗蚀剂层4a作为一个掩模来有选择性地执行半腐蚀,就可在将于以后形成镀层和凸起的位置上形成凹槽部分30a。凹槽部分30a的尺寸须足够大,以用于在后面容纳一个外层芯柱结构。
接下来,如图5E所示,第一层镀膜6被形成在凹槽部分30a中。此时,在上述半腐蚀中所使用的腐蚀机4a被用作一个与其本身一样的掩模。作为第一层镀膜6的材料,可以使用这样一种金属(例如,Au),利用它可使金属衬底1a被有选择性地腐蚀,从而甚至在当金属衬底1a在以后的过程中受到腐蚀时,仍然能保留第一层镀膜6。如图5F所示,可以在第一层镀膜6上形成一个第二层镀膜7。形成此第二层镀膜7的目的是为了(例如)在下一个过程中形成金属芯柱8时提高镀膜的稳定性。
接下来,如图5G所示,通过利用抗蚀剂4a作为掩模进行电镀,从而形成了金属芯柱8。金属芯柱8的材料没有特殊限制,但最好采用与在后面过程中要被固定在金属芯柱8上的芯片具有良好键合特性并且具有良好导电性的材料,例如,可以采用Cu作为其材料。或者,也可在金属芯柱8上形成焊料镀层。
然后,如图5H和5I所示,焊料电极9被设置在半导体芯片10的焊盘电极31上,并且半导体芯片10被一个芯片键合机(未示出)以及一个回熔设备(未示出)或类似设备安装在金属芯柱8上。之后,通过热处理,金属芯柱8和焊料电极9通过金属键合而被键合在一起。但是,如果金属芯柱8上形成有焊料镀层,则半导体芯片10的焊盘电极就不需要配上焊料电极9。之后,如图5J所示,一种绝缘树脂被注入到半导体芯片10与金属衬底1a之间以形成一个将金属芯柱8覆盖于内的绝缘树脂层11。注入绝缘树脂的方法包括利用毛细现象的方法、转移一密封方法,等等。绝缘树脂可以采用环氧树脂、硅树脂、聚酰亚胺树脂、聚烯烃树脂、氰酸酯树脂、酚醛树脂、萘树脂、芴树脂或类似材料。随后,如图5K所示,只有金属衬底1a通过腐蚀被除去。
然后,如图3所示,一个焊料球被安装在金属芯柱8的凸起12之上并通过一种方法(如软熔处理或类似方法)被与金属芯柱8键合在一起,从而形成了一个外层焊料电极13。通过上述过程,就可得到如图3和图4所示的这种芯片倒装型半导体器件。
以下将对第一实施例的效果进行说明。在本实施例中,由于金属芯柱8具有从绝缘树脂层11表面凸出的凸起12,因而它能够在当从水平方向上有一个剪切应力施加到外层焊料电极13上时,可靠地防止外层焊料电极13像未设置有凸起12的情况那样从金属芯柱8上脱落。就是说,当超过一定水平的剪切应力被施加到外层焊料电极13上时,第一层镀膜6与外层焊料电极13之间的交界处就会出现断裂。如果金属芯柱8没有凸起12,则断裂将迅速传播并使外层焊料电极13从金属芯柱8上脱落下来。另一方面,在本实施例中,由于金属芯柱8具有凸起12,因而就防止了断裂的传播。另外,由于第一层镀膜6与外层焊料电极13之间的接触面积因凸起12的出现而增大,这样就提高了焊料的键合强度。因此,金属芯柱8与外层焊料电极13之间的键合强度也得到了提高,进而使芯片倒装型半导体器件的安装可靠性也得到提高。
为了获得上述效果,金属芯柱8暴露在绝缘树脂层11表面之外的部分的高度(即,凸起12的高度)最好为外层焊料电极高度(即,从外层焊料电极13外部端子到绝缘树脂层11表面的距离)的7%至50%。比值小于7%会导致对施加在金属芯柱8与外层焊料电极13之间的接口上的剪切应力的承受能力和防止断裂在接口上传播的效果不够。另一方面,如果比值超过了50%,由于安装板与焊料之间的接触面积减小,所以键合强度也将不良地降低。使比值在20%值50%之间则更好。
另外,由于有金属芯柱8和绝缘树脂层11,所以本实施例所述的芯片倒装型半导体器件中的外部端子被做得较高。因此,当根据本实施例所述的芯片倒装型半导体器件在终端用户方被安装在多层布线板上时,多层布线板与半导体芯片之间的距离高度也相应地增加。这样,就可对因多层布线板与芯片倒装型半导体器件之间热膨胀系数的差异而产生的应力起到缓冲效果,从而提高芯片倒装型半导体器件的安装可靠性。还有,钝化膜及钝化膜之下的半导体芯片10的有效区域表面也可得到保护,以防止在回收半导体芯片10时所产生的热量和机械负荷。为了获得上述效果,金属芯柱的高度最好为100μm或更高一些。
另外,由于金属芯柱8和绝缘树脂层11可以作为本实施例所述的芯片倒装型半导体器件的应力缓解层,因而就不需要在半导体芯片与传统器件中的多层布线板之间注入未充满的(underfill)树脂。因此,如果半导体芯片10已被安装并且随后发现除半导体芯片10以外的其它部分中存在缺陷,则可以从安装板上剥离、回收并重新使用半导体芯片10。
另外,由于本实施例所述的芯片倒装型半导体器件中没有使用未充满的树脂,所以就不会出现因未充满的树脂中的气隙或未充满的树脂与半导体芯片或安装板之间的键合缺陷而造成的脱落现象。
还有,在制造根据本实施例所述半导体器件的方法中,很容易在金属芯柱的暴露部分上提供金属镀层。而提供金属镀层的优点包括:通过提供采用非氧化性的金属(如Au等)的镀层,就可防止在金属芯柱表面上形成一层绝缘氧化膜,而且通过提供采用高硬度的金属(如Ni等),也可保护金属芯柱不受施加在其暴露部分之上的热应力的损坏。因此,半导体器件的安装可靠性进一步得到提高。
以下将对本发明的第二实施例进行说明。图6是根据本发明第二实施例所述的一种芯片倒装型半导体器件的截面图。在根据本实施例所述的芯片倒装型半导体器件中,半导体芯片10的一个表面上配置有多个焊盘电极31,并且各个焊盘电极31都与焊料电极9相连接。另外,各个焊料电极9还与金属芯柱16b相连接。在半导体芯片形成有焊盘电极31的一侧表面上涂有一层绝缘树脂层11。而且焊盘电极31和焊料电极9的全部以及金属芯柱16b的一部分被埋设在绝缘树脂层11内。金属芯柱16b的剩余部分从绝缘树脂层11伸出以形成凸起。形成外层焊料电极13以覆盖上述凸起。从外层焊料电极13看去所得到的这种芯片倒装型半导体器件的平面图与图4中所示的完全相同。
图7A至7F的截面图按照制造过程的步骤显示了一种用于制造根据本发明第二实施例所述的芯片倒装型半导体器件的方法。首先,如图7A所示,一个金属衬底1b被与第一实施例的情况一样制备出来。可以采用如Cu来作为这种金属衬底1b的金属材料。该金属衬底1b的厚度最好为100μm或更大。接下来,金属衬底1b的前表面和后表面被分别涂以抗蚀剂2b和3b。然后,如图7B所示,抗蚀剂2b和3b被曝光并演变形成经构图的抗蚀剂4b和5b。
接下来,如图7C所示,金属衬底1b的两个表面受到腐蚀。这样就形成了一个临时衬底14b。此时的腐蚀量没有特殊限制,但是,正面的腐蚀量(抗蚀剂4b一侧)决定了金属芯柱部分被要在以后形成的绝缘树脂层覆盖的高度。背面(抗蚀剂5b一侧)的腐蚀量则决定了金属芯柱部分从绝缘树脂层表面凸出的高度。因此,需根据这些高度来决定腐蚀的量。
接下来,如图7D所示,只清除掉正面的抗蚀剂4b,或者是清除掉两个表面上的抗蚀剂4b和5b,从而暴露出临时衬底14b的表面部分。
然后,半导体芯片10被装在此临时衬底14b上,从而使半导体芯片10的焊盘电极31上配有的焊料电极9与临时衬底14b的凸出部分15b相接触,而且焊料电极9和凸出部分15b利用软熔或热处理等方法,通过金属键合而被键合在一起。
接下来,如图7E所示,将一种绝缘树脂注入到临时衬底14b与半导体芯片10之间,以形成一个绝缘树脂层11。然后,如图7F所示,临时衬底14b的后表面通过利用抗蚀剂5b作为掩模而受到腐蚀以除去临时衬底14b的凸出部分15b之间的金属,并形成金属芯柱16b。但是,这种操作不适用于在图7D的过程中将两侧的抗蚀剂都除去的情况。在这种情况下,金属芯柱16b之间的金属部分通过对整个后表面进行腐蚀而被除去。
接下来,如图6所示,通过对焊料膏或焊料球等进行软熔处理就可在金属芯柱16b的凸起上形成一个外层焊料电极13。这样就得到了根据第二实施例所述的芯片倒装型半导体器件。
以下将对第二实施例的效果进行说明。根据此实施例所述,除了能够获得第一实施例所述的效果以外,由于其金属芯柱16b的一端可以从绝缘树脂层11的表面高高凸起。因此,就可获得一个能够对在将器件安装在多层布线板上时因热负载和机械负荷而造成的焊球断裂、破裂或类似情况起到阻止作用的结构。另外,在第一实施例中,当金属芯柱通过镀膜被形成时,金属芯柱是从实施例中所述的金属衬底中形成的。因此就很容易防止出现各种高度的金属芯柱,而且较高的金属芯柱可通过利用诸如腐蚀法的方法而形成,这种方法相对简单且成本不高。
以下将对本发明的第三实施例进行说明。图8是根据本发明第三实施例所述的一种芯片倒装型半导体器件的截面图。在根据本实施例所述的芯片倒装型半导体器件中,半导体芯片10的一个表面上配有多个焊盘电极31,并且焊料电极9与各个焊盘电极31相连接。另外,各个焊料电极9还通过一金属镀膜层17与金属芯柱16c相连接。在半导体芯片形成有焊盘电极31的一侧表面上涂有一层绝缘树脂层11。而且焊盘电极31和焊料电极9的全部以及金属芯柱16c的一部分被埋设在绝缘树脂层11内。金属芯柱16c的剩余部分从绝缘树脂层11凸出以形成一个凸起。此凸起被涂覆以金属镀膜层17,而且一个外层焊料电极13被形成以覆盖上述金属镀膜层17。从外层焊料电极13看去所观察到的这种芯片倒装型半导体器件的平面图与图4所示的完全相同。
图9A和9B的截面图按照制造过程的步骤显示了一种用于制造根据本发明第三实施例的芯片倒装型半导体器件的方法。首先,如图9A所示,金属衬底1c的前表面和后表面都被覆盖一层抗蚀剂,而且抗蚀剂受到曝光和显影以形成抗蚀剂层4c和5c,抗蚀剂层4c和5c的图案与第二实施例中所述的抗蚀剂层4b和5b的图案正好相反。然后,利用抗蚀剂层4c和5c作为掩模将一个金属镀膜层17形成在没有抗蚀剂4c和5c的部分上。选择能够抵抗对金属衬底1c的腐蚀的金属作为构成此金属镀膜层17的金属。
接下来,如图9B所示,清除掉抗蚀剂层4c和5c,并且金属衬底1c的两个表面都通过利用金属镀膜层17作为掩模而受到腐蚀。利用上述过程,就可形成一个与图7C所示第二实施例中的临时衬底14b一样的临时衬底14c,而且在其凸出部分表面之上还形成有一个金属镀膜层17。
接下来,通过利用与图7D至7F以及第二实施例中的图6相同的过程就可获得此芯片倒装型半导体器件。即,半导体芯片10被装在该临时衬底14c上,从而使半导体芯片10的焊盘电极31上所配有的焊料电极9与临时衬底14c的凸出部分15c相接触,而且焊料电极9和凸出部分15c利用软熔或热处理等方法,通过金属键合而被键合在一起。接着,将一种绝缘树脂注入到临时衬底14c与半导体芯片10之间以形成一个绝缘树脂层11。然后,临时衬底14c的后表面通过利用金属镀膜层17作为掩模而受到腐蚀,以除去临时衬底14c的凸出部分15c之间的金属,并进而形成金属芯柱16c。接下来,通过对焊料膏或焊料球等进行软熔处理就可在金属芯柱16b的凸起上形成外层焊料电极13。这样就得到了如图8所示的根据第三实施例所述的芯片倒装型半导体器件。
以下将对第三实施例的效果进行说明。根据本实施例所述,抗蚀剂可在与第二实施例相比更早的制造过程中被清除掉。因此,临时衬底可被保存较长一段时间,而且临时衬底也易于控制。另外,金属镀膜层17也可容易地被形成在金属芯柱16c的表面上。
以下将对本发明的第四实施例进行说明。图10是根据本发明第四实施例所述的一种芯片倒装型半导体器件的截面图。如图10所示,根据本实施例所述的这种芯片倒装型半导体器件具有这样一种结构,在此结构中,金属芯柱16d埋设在绝缘树脂层11内的部分18d与从绝缘树脂层11表面凸出的部分19d是相互分开的。
图11是从外层焊料电极一侧看去所得到的根据第四实施例所述的芯片倒装型半导体器件的平面图。金属芯柱16d的部分18d(见图10)被以阵列的形式埋设在绝缘树脂层11的表面之内。而且,外层焊料电极13也被置于与部分18d相对应的阵列之中。各个部分18d和各个外层焊料电极13被相互分开。除了上述结构以外,根据本实施例所述的芯片倒装型半导体器件与根据第二实施例所述的芯片倒装型半导体器件的结构一样。
图12A至12G的截面图按照制造过程的步骤显示了一种用于制造根据本发明第四实施例所述的芯片倒装型半导体器件的方法。首先,如图12A所示,金属衬底1d的前表面和后表面都被涂覆一层抗蚀剂,而且抗蚀剂受到曝光和显影形成经构图的抗蚀剂层4d和5d。此时,前表面与后表面中的抗蚀剂层的开孔被相互分开。抗蚀剂层5d的开孔位置需与抗蚀剂层4d的开孔位置相对应,但可任意设定它们之间分开的方向和距离。
接下来,通过利用抗蚀剂4d和5d作为掩模而对金属衬底1d的前表面和后表面分别进行有选择地腐蚀,就可获取一个如图12B所示的临时衬底14d。
接下来的过程与第二和第三实施例中的过程完全相同。即,如图12C所示,形成于临时衬底14d的前表面上的抗蚀剂层4d被清除掉,以暴露出临时衬底14d的表面部分。接下来,半导体芯片10被装在该临时衬底14d上,从而使半导体芯片10的焊盘电极31上所形成的焊料电极9与临时衬底14d的凸出部分15d相接触。然后如图12D所示,利用软熔或热处理等方法,将焊料电极9和临时衬底14d通过金属键合而键合在一起。接着,如图12E所示,将一种绝缘树脂注入到临时衬底14d与半导体芯片10之间,以形成一个绝缘树脂层11。然后,如图12F所示,利用抗蚀剂层5d作为掩模,对临时衬底14d的后表面进行腐蚀,以除去临时衬底14d的凸出部分15d之间的金属,并进而形成金属芯柱16d。接下来,如图12G所示,清除掉抗蚀剂层5d。
接下来,如图10所示,通过对焊料膏或焊料球等进行软熔处理就可在金属芯柱16d的暴露部分上形成一个外层焊料电极13。这样就得到了根据第四实施例所述的芯片倒装型半导体器件。
以下将对第四实施例的效果进行说明。在根据本实施例所述的芯片倒装型半导体器件中,金属芯柱16d由被相互分开的18d和19d两部分组成。因此,进行软熔或类似处理时的应力缓解特性将得到提高。这样,就可防止施加在金属芯柱16d的暴露部分上的热和机械应力传播给半导体芯片10。
另外,在本实施例中,图12A和12B中所示的一直到临时衬底14d被形成之前的处理过程可由图9A和9B所示的过程来替代,在后者中,金属镀膜层先被形成然后再受到腐蚀以形成第三实施例中的临时衬底。
以下将对本发明的第五实施例进行说明。图13是根据本发明第五实施例所述的一种芯片倒装型半导体器件的截面图。在根据本实施例所述的这种芯片倒装型半导体器件20e中,半导体芯片10的一个表面上配有多个焊盘电极31,并且焊料电极9与各个焊盘电极31相连接。金属芯柱16b的一端与各个焊料电极9相连接,而金属芯柱16e则通过焊料32与金属芯柱16b的另一端相连接。在半导体芯片10形成有焊盘电极31的一侧表面上涂有一层绝缘树脂层11,而且焊盘电极31和焊料电极9的全部以及金属芯柱16e的一部分被埋设在绝缘树脂层11内。金属芯柱16e的剩余部分从绝缘树脂层11伸出以形成一个凸起。另外,形成外层焊料电极13以覆盖此凸起。就是说,焊盘电极31、焊料电极9、金属芯柱16b、金属芯柱16e以及外层焊料电极13被按照上述顺序串联在一起。由于金属芯柱16e被形成为叠置于芯片倒装型半导体器件20e内的金属芯柱16b之上,所以焊料电极9与外层焊料电极13之间的距离被加大。另一方面,从外层焊料电极13看去所得到的这种芯片倒装型半导体器件的平面图与图4完全相同。
图14A至14C的截面图按照制造过程的步骤显示了一种用于制造根据本发明第五实施例所述的芯片倒装型半导体器件的方法。首先,一个如第二实施例所述的芯片倒装型半导体器件被制备出来。即,如图7A所示,金属衬底1b的前表面和后表面被分别涂以抗蚀剂2b和3b,并且如图7B所示,抗蚀剂2b和3b被曝光并显影为经构图的抗蚀剂层4b和5b。接下来,如图7C所示,金属衬底1b的两个表面都受到腐蚀以形成一个临时衬底14b。然后,如图7D所示,前表面上的抗蚀剂4b被清除掉,从而暴露出临时衬底14b的表面部分。接着,安装半导体芯片10,从而使芯片一侧的焊料电极以及临时衬底14b的凸出部分15b相接触,并利用软熔或热处理等方法,通过金属键合将它们键合在一起。然后,如图7E所示,将一种绝缘树脂被入到临时衬底14b与半导体芯片10之间,以形成一个绝缘树脂层11。接下来,如图7F所示,临时衬底14b的后表面通过利用抗蚀剂5b作为掩模而受到腐蚀,以形成金属芯柱16b。然后,如图8所示,通过对焊料膏或焊料球等进行软熔处理,就可以在金属芯柱16b的暴露部分上形成外层焊料电极13,这样就得到了一个芯片倒装型的半导体器件20b。
接下来如图14A和14B所示,临时衬底1b通过利用构成外层焊料电极13的焊料32被与芯片倒装型半导体器件20b键合在一起。然后,一种绝缘树脂被注入到芯片倒装型半导体器件20b与临时衬底14b之间,以形成绝缘树脂层11。之后,如图14C所示,腐蚀操作从临时衬底14b一侧开始执行以形成金属芯柱16e。另外,临时衬底14b上的抗蚀剂5b也被消除掉。
接下来,如图13所示,通过对焊料膏或焊料球等进行软熔处理,就可在金属芯柱16e的凸起上形成外层焊料电极13。这样就得到了根据第五实施例所述的芯片倒装型半导体器件20e。
以下将对第五实施例的效果进行说明。根据本实施例所述,由于半导体芯片一侧上的焊料电极9与外层焊料电极13之间的距离可被增大,所以对应力(如热应力等)的分散效果就可得到提高,进而使安装可靠性得到了进一步提高。
另外,可以通过重复根据第五实施例所述的制造过程来进一步提高金属芯柱的高度。本实施例中,芯片倒装型半导体器件20b首先是按照第二实施例中所述的方法被制备出来,但是也可按照第一、第三、第四或者将在后面得到说明的第六或第七实施例中所述的方法来制备该芯片倒装型半导体器件。在本实施例中,形成临时衬底14b的过程也可由图9A和9B中所示的第三实施例中的过程(在此过程中,金属镀膜层被形成并且受到腐蚀以形成一个临时衬底)代替。
以下将对本发明的第六实施例进行说明。图15是根据本发明第六实施例所述的一种芯片倒装型半导体器件的截面图。如图15所示,在根据第六实施例所述的这种芯片倒装型半导体器件中,金属芯柱16f由埋设在绝缘树脂层11内的部分18f、从绝缘树脂层11表面凸出的部分19f以及置于绝缘树脂层11表面上的金属导线23构成。在平面图中,部分18f的侧面位于部分19f的侧面之外,同时部分18f通过金属导线23与部分19f相连接。另外,形成外层焊料电极13以覆盖部分19f。
图16是从外层焊料电极13一侧看去所得到的根据本发明的第六实施例所述的芯片倒装型半导体器件的平面图。如图16所示,有多个外层焊料电极13按照阵列形式排列在本实施例所述的芯片倒装型半导体器件内的绝缘树脂层11上。金属导线23与各个外层焊料电极13相连接。除了上述结构以外,根据本实施例所述的芯片倒装型半导体器件与根据上述第二实施例所述的芯片倒装型半导体器件的结构是一样的。
以下将对一种用于制造根据本发明第六实施例所述的芯片倒装型半导体器件的方法进行说明。图17A至17F的截面图按照制造过程的步骤顺序显示了一种用于制造根据本发明第六实施例所述的芯片倒装型半导体器件的方法。金属衬底1f的前表面和后表面都被涂以抗蚀剂,并且如图17A所示,对抗蚀剂进行曝光和显影,形成经构图的抗蚀剂层4f和5f,然后,如图17B所示,利用抗蚀剂层5f作为掩模,对衬底的后表面进行腐蚀。这样,就形成了这样一种形状的金属衬底1f,即,在其后表面上形成了一个岛状凸出部分33。之后,抗蚀剂层5f被清除掉。
或者,也可通过形成一个与抗蚀剂层5f的图案相反的抗蚀剂层、在后表面上执行电镀、清除后表面上的抗蚀剂、并且利用镀膜层作为掩模进行腐蚀,来获得相同的结构。
接下来,如图17C所示,在形成于后表面的岛状凸出部分33上、并与抗蚀剂4f分开的位置形成抗蚀剂层21。然后,如图17D所示,利用抗蚀剂层4f和21作为掩模腐蚀前表面和后表面上的区域22,从而形成了一个临时衬底14f。
接下来,如图17E所示,半导体芯片10被安装在临时衬底14f上,而且半导体芯片10被与临时衬底14f键合在一起。接下来,如图17F所示,在半导体芯片10与临时衬底14f之间提供一个绝缘树脂层。然后,如图15所示,利用抗蚀剂层21作为掩模有选择性地腐蚀临时衬底14f的后表面,从而分出金属芯柱16f。进一步,去掉抗蚀剂21。然后,形成外层焊料电极13以覆盖金属芯柱16f从绝缘树脂层11凸出的部分19f,这样就得到了第六实施例所述的芯片倒装型半导体器件20f。
以下将对第六实施例的效果进行说明。根据本实施例所述,金属芯柱16f暴露在外的部分19f以及埋设在绝缘树脂之内的部分18f是通过金属导线23相连接的。因此,对软熔处理或类似处理时所产生的热应力的缓解效果可得到进一步提高。而且防止施加到暴露在外部分的热和机械应力直接传到半导体芯片10上的效果也得到进一步提高。
以下将对用于制造根据第七实施例所述的芯片倒装型半导体器件的方法进行说明。图18A至18F的截面图按照制造过程的步骤显示了一种用于制造根据本发明第七实施例所述的芯片倒装型半导体器件的方法。根据本实施例的方法所述,它可以制备出各种形式的芯片倒装型半导体器件。对制造根据第七实施例所述芯片倒装型半导体器件的方法的说明是以第二实施例中所示的芯片倒装型半导体器件20b的制备情况为参考进行的。首先,如图18A所示,与第二实施例中的情况一样,抗蚀剂4g和5g被形成在金属衬底1g的两则。接下来,只有金属衬底1g的一个表面利用抗蚀剂4g作为掩模得到半腐蚀处理,这样就制备出了如图18B所示的其表面上形成有一个凸出部分15g的临时衬底14g。然后,如图18C所示,半导体芯片10被放置在临时衬底14g的表面上,以使半导体芯片10与凸出部分15g相互接触。之后,将焊料电极9进行加热,从而使半导体芯片10与临时衬底14g键合在一起。
然后,如图18D所示,在半导体芯片10与临时衬底14g之间形成绝缘树脂层11。接着,如图18E所示,利用抗蚀剂5层作为掩模的腐蚀处理从后表面开始进行。因此,金属被从金属衬底1g的凸出部分15g以外的部分中清除掉,从而形成金属芯柱16g。然后,如图18F所示,抗蚀剂层5g被清除掉,以形成外层焊料电极13,这样就获得了芯片倒装型半导体器件20b。通过本实施例而得到的芯片倒装型半导体器件,其结构与通过第二实施例所获得的半导体器件的结构完全相同。
以下将对本发明第七实施例的效果进行说明。在本实施例中,临时衬底14g的后表面是在安装半导体芯片10并且形成绝缘树脂层11的过程之后才得到腐蚀的。因此,临时衬底14g的强度可一直保持到绝缘树脂层11形成为止。结果,对临时衬底14g的控制可得到提高。另外,无需对形成临时衬底14g时的腐蚀量进行精确控制。结果,芯片倒装型半导体器件的制备将变得十分简单,并且制备时间也可以被缩短。
本实施例是以第二实施例中所示的芯片倒装型半导体器件的制备过程作为范例的,但是,本实施例所述的方法可以适用于第三至第六实施例中的芯片倒装型半导体器件的制备情况。
以下将对一种用于制造根据第八实施例所述的芯片倒装型半导体器件的方法进行说明。图19A至19B的截面图按照制造过程的步骤显示了一种用于制造根据本发明第八实施例所述的芯片倒装型半导体器件的方法。以下将参考第二实施例中所示的芯片倒装型半导体器件的制备情况,以示例形式对根据第八实施例所述的芯片倒装型半导体器件的制造方法进行说明。首先,如图19A所示,金属衬底1h的表面受到一个含有一凹槽部分的模子的按压。这样,如图19B所示,一个具有一凸出部分15h的临时衬底14h就被制备出来。然后,半导体芯片被放置在临时衬底14h的表面上、在受到加热后与临时衬底14h键合在一起、并且将一种绝缘树脂注入到半导体芯片与临时衬底14h之间以形成一个绝缘树脂层。接下来,在整个后表面上执行腐蚀,从而使金属被从衬底1h的凸出部分15h以外的其它部分清除掉,以形成金属芯柱。然后,形成外层焊料电极,从而获得了这种芯片倒装型半导体器件。
通过本实施例所得到的芯片倒装型半导体器件,其结构与通过图6所示第二实施例所获得的器件的结构完全相同。
以下将对第八实施例的效果进行说明。根据本实施例所述的制造方法,形成抗蚀剂图案以及腐蚀的过程可在形成临时衬底时被省略。结果,制造时间就可得到缩短。
Claims (19)
1.一种芯片倒装型半导体器件,包括:
带有焊盘电极的半导体芯片;
覆盖在所述半导体芯片带有焊盘电极一侧的表面上的绝缘树脂层;
穿透所述绝缘树脂层并与所述焊盘电极相连的金属芯柱,所述金属芯柱包括:
埋设在所述绝缘树脂层之中的第一部分;
从所述绝缘树脂层凸出的第二部分;以及
与所述绝缘树脂层表面上的所述金属芯柱相连的电极。
2.如权利要求1所述的芯片倒装型半导体器件,其特征在于从所述绝缘树脂层表面到所述第二部分之间的高度为从所述绝缘树脂层表面到所述电极之间高度的7%到50%。
3.如权利要求1所述的芯片倒装型半导体器件,其特征在于所述第一和第二部分的中心在平面图上被相互分开。
4.如权利要求3所述的芯片倒装型半导体器件,其特征在于所述第二部分具有:
一柱状部分,其侧面位于所述第一部分侧面的外侧;以及
一连接部分,用于连接所述柱状部分与所述第一部分。
5.如权利要求1所述的芯片倒装型半导体器件,其特征在于所述金属芯柱将多个导电层叠加起来而被形成的。
6.如权利要求1所述的芯片倒装型半导体器件,其特征在于还包括一个或多个形成在所述金属芯柱与所述电极之间的金属镀膜层。
7.如权利要求1所述的芯片倒装型半导体器件,其特征在于所述绝缘树脂层的主要成份至少含有从环氧树脂、硅树脂、聚酰亚胺树脂、聚烯烃树脂、氰酸酯树脂、酚醛树脂、萘树脂以及芴树脂这组材料中选择出来的一种树脂。
8.如权利要求1所述的芯片倒装型半导体器件,其特征在于所述金属芯柱由从Cu,Ni,Fe,Au,Sn和Pb这组材料中选择出来的至少一种金属或其合金构成。
9.如权利要求6所述的芯片倒装型半导体器件,其特征在于与所述电极相互接触的所述金属镀膜层由从Cu,Ni,Au,Sn和Pb这材料中选择出来的至少一种金属或其合金构成。
10.一种用于制造芯片倒装型半导体器件的方法,包括以下步骤:
在金属衬底的表面上形成多个凹槽部分;
在各个凹槽部分的表面上都形成金属芯柱;
将各金属芯柱分别与半导体芯片的焊盘电极连接起来;
在所述金属衬底与所述半导体芯片之间注入一种绝缘树脂以形成绝缘树脂层;
去除所述金属衬底;并且
在所述金属芯柱上形成电极。
11.如权利要求10所述的用于制造芯片倒装型半导体器件的方法,其中所述凹槽部分是通过以下步骤而形成的:
在所述金属衬底的第一表面上形成具有多个开口的抗蚀剂层;和
利用所述抗蚀剂层作为掩模对所述金属衬底进行腐蚀,形成凹槽部分;并且通过利用所述抗蚀剂层作为掩模在所述凹槽部分上形成金属镀膜层,以形成所述金属芯柱。
12.一种用于制造芯片倒装型半导体器件的方法,包括以下步骤:
在金属衬底的第一表面上形成多个凸出部分;
在所述金属衬底的第二表面上形成与形成于所述第一表面上的凸出部分相对应的多个凸出部分;
将形成在所述第一表面上的所述凸出部分与半导体芯片的焊盘电极连接在一起;
在所述金属衬底与所述半导体芯片之间注入一种绝缘树脂以形成绝缘树脂层;
去除所述金属衬底的所述凸出部分以外的其它部分,以分出所述凸出部分;以及
在形成于所述金属衬底的第二表面之上的凸出部分上形成多个电极。
13.如权利要求12所述的用于制造芯片倒装型半导体器件的方法,其中所述多个凸出部分是通过以下步骤而形成的:
形成一层抗蚀剂以遮蔽住其上要形成所述凸出部分的区域;以及
利用所述抗蚀剂层作为掩模对所述金属衬底进行腐蚀。
14.如权利要求12所述的用于制造芯片倒装型半导体器件的方法,其中所述多个凸出部分是通过以下步骤而形成的:
在要形成所述凸出部分的区域中形成具有多个开口的抗蚀剂层;
在从所述开口露出的所述金属衬底的表面上形成金属镀膜层;和
利用所述金属镀膜层作为掩模对所述金属衬底进行腐蚀。
15.如权利要求12所述的用于制造芯片倒装型半导体器件的方法,其中所述多个凸出部分是通过对所述金属衬底进行压模成型处理以在所述金属衬底的表面上形成凹入部分和凸出部分而形成的。
16.如权利要求12所述的用于制造芯片倒装型半导体器件的方法,其中在第一表面上的形成凸出部分的区域被与在第二表面上形成凸出部分的区域分开。
17.如权利要求12所述的用于制造芯片倒装型半导体器件的方法,其中所述多个凸出部分是通过以下步骤而形成的:
对所述金属衬底的所述第二表面进行有选择性地腐蚀;
利用第一抗蚀剂层作为掩模对所述第二表面进行腐蚀,该抗蚀剂层遮掩了所述第二表面中不受腐蚀的部分;以及
利用第二抗蚀剂层作为掩模对所述第一表面进行腐蚀,该抗蚀剂层遮掩了所述第一表面的一个区域,该区域位于所述第二表面中未被第一次腐蚀处理腐蚀掉的区域上,并且在平面图上是与未被第二腐蚀处理腐蚀掉的区域分开的。
18.如权利要求12所述的用于制造芯片倒装型半导体器件的方法,其中形成所述绝缘树脂层,然后再在所述第二表面上形成多个凸出部分。
19.如权利要求12所述的用于制造芯片倒装型半导体器件的方法,还包括如下步骤:
在形成所述电极后,将所述电极与设置在第二金属衬底上的第二凸出部分键合;
通过将绝缘树脂注入到所述第二金属衬底与所述绝缘树脂层之间,形成第二绝缘树脂层;
通过去除所述第二金属衬底中除所述第二凸出部分以外的其它部分,以分出所述第二凸出部分;和
将第二电极形成在所述第二凸出部分上。
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US6238952B1 (en) * | 2000-02-29 | 2001-05-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
EP1143509A3 (en) * | 2000-03-08 | 2004-04-07 | Sanyo Electric Co., Ltd. | Method of manufacturing the circuit device and circuit device |
US6348399B1 (en) * | 2000-07-06 | 2002-02-19 | Advanced Semiconductor Engineering, Inc. | Method of making chip scale package |
US6762118B2 (en) * | 2000-10-10 | 2004-07-13 | Walsin Advanced Electronics Ltd. | Package having array of metal pegs linked by printed circuit lines |
US20020094683A1 (en) * | 2001-01-17 | 2002-07-18 | Walsin Advanced Electronics Ltd | Method for manufacturing chip size package and its structure |
US6380062B1 (en) * | 2001-03-09 | 2002-04-30 | Walsin Advanced Electronics Ltd. | Method of fabricating semiconductor package having metal peg leads and connected by trace lines |
-
2000
- 2000-05-26 JP JP2000157432A patent/JP2001338947A/ja active Pending
-
2001
- 2001-05-25 US US09/866,404 patent/US6503779B2/en not_active Expired - Fee Related
- 2001-05-25 CN CN01116178A patent/CN1326225A/zh active Pending
- 2001-05-25 KR KR10-2001-0029044A patent/KR100432643B1/ko not_active IP Right Cessation
- 2001-05-25 TW TW090112749A patent/TW494557B/zh not_active IP Right Cessation
- 2001-05-26 SG SG200103185A patent/SG87930A1/en unknown
- 2001-05-28 EP EP01113016A patent/EP1160856A3/en not_active Withdrawn
-
2002
- 2002-08-29 US US10/233,219 patent/US6759271B2/en not_active Expired - Fee Related
- 2002-11-12 US US10/292,201 patent/US20030057568A1/en not_active Abandoned
Cited By (24)
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US7749888B2 (en) | 2002-02-07 | 2010-07-06 | Nec Corporation | Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same |
US7268438B2 (en) | 2002-02-07 | 2007-09-11 | Nec Corporation | Semiconductor element including a wet prevention film |
US7449406B2 (en) | 2002-02-07 | 2008-11-11 | Nec Corporation | Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same |
US7135770B2 (en) | 2002-02-07 | 2006-11-14 | Nec Corporation | Semiconductor element with conductive columnar projection and a semiconductor device with conductive columnar projection |
CN100461354C (zh) * | 2004-09-28 | 2009-02-11 | 相丰科技股份有限公司 | 适用集成电路及发光二极管的封装方法 |
CN100513037C (zh) * | 2004-12-05 | 2009-07-15 | 国际商业机器公司 | 改进的焊料互连结构和使用注入模制焊料的方法 |
CN101976663A (zh) * | 2010-09-27 | 2011-02-16 | 清华大学 | 一种无基板的倒装芯片的芯片尺寸封装结构 |
CN101976662A (zh) * | 2010-09-27 | 2011-02-16 | 清华大学 | 一种无基板的输出端扇出型倒装芯片封装结构 |
CN101976662B (zh) * | 2010-09-27 | 2012-07-25 | 清华大学 | 一种无基板的输出端扇出型倒装芯片封装结构 |
CN103378038A (zh) * | 2012-04-13 | 2013-10-30 | 拉碧斯半导体株式会社 | 半导体装置 |
US10424537B2 (en) | 2012-04-13 | 2019-09-24 | Lapis Semiconductor Co., Ltd. | Device with pillar-shaped components |
CN103378038B (zh) * | 2012-04-13 | 2017-06-30 | 拉碧斯半导体株式会社 | 半导体装置 |
US9721879B2 (en) | 2012-04-13 | 2017-08-01 | Lapis Semiconductor Co., Ltd. | Device with pillar-shaped components |
US10957638B2 (en) | 2012-04-13 | 2021-03-23 | Lapis Semiconductor Co., Ltd. | Device with pillar-shaped components |
CN103515330A (zh) * | 2012-06-14 | 2014-01-15 | 矽品精密工业股份有限公司 | 封装基板暨半导体封装件及其制法 |
CN104425396A (zh) * | 2013-09-02 | 2015-03-18 | 日月光半导体制造股份有限公司 | 半导体封装结构及其制造方法 |
CN105097758A (zh) * | 2014-05-05 | 2015-11-25 | 日月光半导体制造股份有限公司 | 衬底、其半导体封装及其制造方法 |
US10879159B2 (en) | 2014-05-05 | 2020-12-29 | Advanced Semiconductor Engineering, Inc. | Substrate, semiconductor package thereof and process of making same |
CN105097758B (zh) * | 2014-05-05 | 2018-10-26 | 日月光半导体制造股份有限公司 | 衬底、其半导体封装及其制造方法 |
CN111725146A (zh) * | 2019-03-18 | 2020-09-29 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
CN112786530A (zh) * | 2019-11-01 | 2021-05-11 | 美光科技公司 | 封装焊料tsv插入互连 |
US11587912B2 (en) | 2019-11-01 | 2023-02-21 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
US11631644B2 (en) | 2019-11-01 | 2023-04-18 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
US11973062B2 (en) | 2023-02-15 | 2024-04-30 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
Also Published As
Publication number | Publication date |
---|---|
SG87930A1 (en) | 2002-04-16 |
EP1160856A2 (en) | 2001-12-05 |
JP2001338947A (ja) | 2001-12-07 |
TW494557B (en) | 2002-07-11 |
EP1160856A3 (en) | 2003-02-12 |
US6503779B2 (en) | 2003-01-07 |
US20020195720A1 (en) | 2002-12-26 |
US20010048166A1 (en) | 2001-12-06 |
KR100432643B1 (ko) | 2004-05-22 |
KR20010107767A (ko) | 2001-12-07 |
US6759271B2 (en) | 2004-07-06 |
US20030057568A1 (en) | 2003-03-27 |
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