CN1326233C - Multi-element vertical memory and its manufacture - Google Patents
Multi-element vertical memory and its manufacture Download PDFInfo
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- CN1326233C CN1326233C CNB031558089A CN03155808A CN1326233C CN 1326233 C CN1326233 C CN 1326233C CN B031558089 A CNB031558089 A CN B031558089A CN 03155808 A CN03155808 A CN 03155808A CN 1326233 C CN1326233 C CN 1326233C
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- memory cell
- layer
- vertical memory
- bit line
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Abstract
The present invention provides a multi-element vertical memory unit and a manufacturing method for the multi-element vertical memory unit. The multi-element vertical memory unit comprises a semiconductor substrate, wherein the semiconductor substrate is provided with at least a groove; a plurality of bit lines are respectively formed in the semiconductor substrate which is adjacent to the surface of the semiconductor substrate and the bottom of the groove; a plurality of bit line insulated layers are arranged above each bit line; a silicon-rich oxide layer is used for storing electric charges partially and is conformably arranged on the side wall of the groove and the surface of each bit line insulated layer; a character line is arranged above the silicon-rich oxide layer and is filled into the groove.
Description
Technical field
The invention relates to a kind of rectilinear memory cell, particularly relevant for a kind of store more than at least two multidigit unit vertical memory cell with and manufacture method.
Background technology
In the semiconductor memory assembly, behind power-off, still preserve data person, be referred to as " non-volatility memorizer (nonvolatile memory, NVM) ", for example the electronic type programmable read-only memory (EEPROM) etc. of can erasing.Wherein, known flash memory is when carrying out the sequencing step, and hot carrier (hotelectrons) can inject float gate and be uniformly distributed in whole float gate.Yet, repeat to write, read and erase step after, the passage oxide layer (tunneloxide layer) that is positioned at float gate below can be because hot carrier penetrating number of times and damage repeatedly, make the stored carrier of float gate omit (leak out) easily, and cause the reliability of storage device to descend.
For the leakage current that prevents EEPROM and other problem, (nitride ROM, structure NROM) is suggested a kind of nitride ROM.When the control grid of NROM and source drain area are subjected to bias voltage respectively when carrying out sequencing, hot carrier can produce at the passage near the drain area side, and iunjected charge trap layer (charge trapping layer) is just in the nitration case, the carrier of these injections will be stored in this charge trap layer locally, and can not distribute equably.Because the zone that these localities store is quite little,, and the leakage current of storage device is reduced so the zone that the channel oxide layer can be damaged also is restricted.
Please refer to Fig. 1, Fig. 1 is the tangent plane schematic diagram that shows known formation nitride read-only memory unit.
This memory cell comprises a Si semiconductor substrate 100, it has the two bit lines 102 that separate that can be used as the source drain area, two bit line insulating layers 104 are the tops that respectively are arranged at two bit lines 102, and an ONO layer 112 is the tops, the semiconductor-based ends 100 that are arranged between the two bit lines 102.This ONO layer 112 be by a bottom silicon oxide layer 106, a silicon nitride layer 108, and a upper strata silicon oxide layer 110 in regular turn storehouse form.One gate conducting layer (character line) the 114th is arranged at bit line insulating layer 104 and ONO layer 112 top.
Silicon nitride layer 112 in ONO layer 112 has two charge storaging areas 107,109, and in order to come store charge during the memory cell sequencing, it is adjacent to bit line 102.When the bit on the sequencing left side was charge storaging area 107, the bit line 102 on the left side was as drain and receives a high sequencing voltage that simultaneously, the bit line 102 on the right is as source electrode and ground connection.
In like manner, when the bit on sequencing the right was charge storaging area 109, the bit line 102 on the right was as drain and receives a high sequencing voltage that simultaneously, the bit line 102 on the left side is as source electrode and ground connection.Moreover when the bit that reads the left side (charge storaging area 107), the bit line 102 on the left side is as drain as the bit line 102 on source electrode and the right.In like manner, when reading the bit (charge storaging area 109) on the right, the bit line 102 on the right is as drain as the bit line 102 on the source electrode and the left side.In addition, when erasing, the relative position of its source drain is identical when carrying out sequencing.
In order to increase density of memory cells, mainly be by the width of area that dwindles the bit line or ONO layer method with the spacing that reduces by two character lines to promote the integration of integrated circuit.Yet when dwindling the area of bit line, the resistance value of bit line can be enhanced and cause the service speed of storage device to reduce; On the other hand, if dwindle the width of ONO layer, then easily sequencing, erase or read during the situation of two charge storaging area phase mutual interference (cell disturbance) in the memory cell takes place.Particularly when the width of ONO layer less than 10 how during rice (nm).Therefore, density of memory cells can be because of above-mentioned former thereby limited, and can't increase the integration of integrated circuit.
Summary of the invention
The object of the present invention is to provide a kind of method that forms rectilinear memory cell, and this rectilinear memory cell can store at least two data.
According to above-mentioned purpose, the invention provides the manufacture method of the first vertical memory cell of a kind of multidigit, comprise the following steps: to provide the semiconductor substrate, the semiconductor-based end, have at least one groove; In the semiconductor-based end of contiguous semiconductor-based basal surface and channel bottom, respectively form a doped region with as the bit line; Respectively form a bit line insulating layer in each doped region top; Sidewall and bit line insulating layer surface compliance formation one in groove are rich in the silicon insulating barrier with the local storage electric charge; And above insulating barrier, form a conductive layer and insert groove.
Another object of the present invention is to provide a kind of rectilinear memory cell that stores the multidigit metadata.
According to above-mentioned purpose, the invention provides the first vertical memory cell of a kind of multidigit, comprising: the semiconductor substrate, the semiconductor-based end, have at least one groove; Plural number bit line is formed at respectively at the semiconductor-based end and channel bottom of contiguous semiconductor-based basal surface; Plural number bit line insulating layer is arranged at each bit line top; One is rich in silicon oxide layer, in order to the local storage electric charge, is arranged to compliance trenched side-wall and bit line insulating layer surface; And a character line, be arranged at and be rich in the silicon oxide layer top and insert groove.
Description of drawings
Fig. 1 is the tangent plane schematic diagram that shows known formation nitride read-only memory unit;
Fig. 2 a to Fig. 2 g is the tangent plane schematic diagram that shows the first vertical memory cell of formation multidigit of the present invention;
Fig. 3 is the vertical view of a storage array;
Fig. 4 a and Fig. 4 b show respectively according to the schematic diagram that the multidigit unit vertical memory cell of the embodiment of the invention is carried out the sequencing step.
Symbol description:
100～semiconductor-based the end
102～bit line
104～bit line insulating layer
106,110～silicon oxide layer
107,109～charge storaging area
108～silicon nitride layer
112～ONO layer
114～character line
B1～first bit
B2～second bit
200～semiconductor-based the end
202～pad silicon oxide layer
204,211～silicon nitride layer
205～cover curtain layer
206～photoresist layer
207～opening
208～groove
210～silicon oxide layer
212～clearance wall
214～bit line
216～bit line insulating layer
218～brake-pole dielectric layer
220～be rich in silicon oxide layer
222～brake-pole dielectric layer
223～stack layer
224～conductive layer
226～oxide layer
228～boron-phosphorosilicate glass layer
230～tetraethyl orthosilicate oxide layer
The contact of 232～character line
234,236～bit line contact
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Please refer to Fig. 2 a to Fig. 2 g, Fig. 2 a to Fig. 2 g is the tangent plane schematic diagram that shows the first vertical memory cell of formation multidigit of the present invention.
Please refer to Fig. 3 simultaneously, Fig. 3 is the vertical view of a storage array, and Fig. 2 a to Fig. 2 g is the AA ' tangent plane and the BB ' sectional drawing of displayed map 3.
At first, please refer to Fig. 2 a, semiconductor substrate 200 is provided, for example a Silicon Wafer.Form a cover curtain layer 205 on surface, the semiconductor-based ends 200, it can be the stack architecture of single layer structure or several layers.As shown in FIG., cover curtain layer 205 is preferably by the thicker silicon nitride layer 204 of one deck pad silicon oxide layer 202 and one deck and is formed.Wherein, pad silicon oxide layer 202 can by thermal oxidation method or (low pressure chemicalvapor deposition, LPCVD) deposition forms with known normal pressure (atmospheric) or Low Pressure Chemical Vapor Deposition.Silicon nitride layer 204 on pad silicon oxide layer 202 can utilize Low Pressure Chemical Vapor Deposition, with dichlorosilane (SiCl
2H
2) and ammonia (NH
3) form for reaction raw materials deposits.Then, on cover curtain layer 205 surfaces, form one deck photoresist layer 206.Afterwards, form plural opening 207 in 206 by known micro-photographing process in photoresist layer.
Next, please refer to Fig. 2 b, by photoresist layer 206 with opening 207 as etch mask, cover curtain layer 205 is carried out the anisotropic etching processing procedure, reactive ion etching (reactiveion etching for example, RIE) or electric paste etching (plasma etching), with opening 207 design transfer of photoresist layer 206 to cover curtain layer 205.
Then, remove after the photoresist layer 206 with suitable etching solution or ashing treatment, by cover curtain layer 205 as etch mask, carry out the anisotropic etching processing procedure, for example reactive ion etching or electric paste etching were etched to a desired depth and form the plural groove 208 that the degree of depth is about 1400～1600 with the semiconductor-based end 200 with the opening below of cover curtain layer 205.
Next, please refer to Fig. 2 c, cover curtain layer 205 is divested.Wherein, the method that divests silicon nitride layer 204 is a wet etching, for example is with hot phosphoric acid (H
3PO
4) for etching solution soaks it is removed, the method that divests pad silicon oxide layer 202 is a wet etching, it for example is to be that etching solution soaks with hydrofluoric acid (HF).Afterwards, above the semiconductor-based end 200, reach groove 208 surperficial compliances by the CVD method and form one silica layer 210, about about 100 of its thickness.Then, compliance deposits a silicon nitride layer 211 above silicon oxide layer 210.Similarly, silicon nitride layer 211 can utilize Low Pressure Chemical Vapor Deposition, with dichlorosilane (SiCl
2H
2) and ammonia (NH
3) form for reaction raw materials deposits.
Next, please refer to Fig. 2 d, anisotropic etching silicon nitride layer 211, for example reactive ion etching or electric paste etching are to form a clearance wall 212 on the sidewall of each groove 208.Afterwards, utilize clearance wall 212 to implant at the bottom and surface enforcement one ion of the semiconductor-based ends 200 of groove 208 as the cover curtain, for example use phosphonium ion, so as in the semiconductor-based end 200 of groove 208 bottoms and surface, the contiguous semiconductor-based ends 200, respectively forming doped region 214, with as the bit line.
Then, please refer to Fig. 2 e, above each doped region 214, form bit line insulating layer 216, for example silicon oxide layer by thermal oxidation method or other deposition technique.Bit line insulating layer 216 is very thick usually, in order to reduce formed capacitance between bit line and character line.In the present embodiment, the thickness of bit line insulating layer 216 is about the scope of 300 to 2000 .Afterwards, remove clearance wall 212 and silicon oxide layer 210 in regular turn by wet etching.
Next, carry out a characterization step of the present invention.
Please refer to Fig. 2 f, compliance forms a brake-pole dielectric layer 218, and is rich in silicon oxide layer (silicon rich oxide) 220, an and brake-pole dielectric layer 222, three and the common stack layer 223 that forms in regular turn on groove 208 sidewalls and bit line insulating layer 216 surfaces.Be rich in the usefulness of silicon oxide layer 220 as the local storage electric charge, its function is similar to known float gate, and thickness is about about 50 to 110 , can be formed by chemical vapour deposition (CVD) (chemical vapor deposition) method.The thickness of brake-pole dielectric layer 218,222 is about respectively about 50 , can form by thermal oxidation (thermaloxidation) method.As discussed previously, this is rich in silicon oxide layer 220 is as the usefulness of store charge during memory cell is carried out sequencing, therefore charge storaging area will be arranged in and be rich in silicon oxide layer 220 on groove 208 sidewalls, and can be adjacent to the doped region 214 of groove 208 tops or bottom.Be that the present invention is with the semiconductor-based end 200 of the groove 208 sidewalls channel as memory cell and be different from the known techniques part.That is the manufacture method according to the first vertical memory cell of multidigit of the present invention can form a rectilinear passage, and be different from the horizontal passage in the known techniques.
Please refer to Fig. 2 f, form a conductive layer 224 in stack layer 223 tops, for example is polysilicon layer, and conductive layer 224 can fill up groove 208.In the present embodiment, the thickness of conductive layer 224 is about about 1500 to 2000 , can form by chemical vapour deposition technique.Afterwards, can (chemical mechanic polishing CMP) carries out planarization to conductive layer 224 by chemical mechanical milling method.
Then, on conductive layer 224, apply one and have the photoresist layer (not shown) of character line pattern, and by known little shadow and etching program to define the character line that is constituted by conductive layer 224, shown in Fig. 2 f (a); And the conductive layer of part can be removed to and exposes stack layer 223, shown in Fig. 2 f (b).
Please refer to Fig. 2 g, follow-up oxide layer 226, boron-phosphorosilicate glass (BPSG) layer 228 and tetraethyl orthosilicate (TEOS) oxide layer 230 of can forming on being formed with as the conductive layer 224 of character line and stack layer 223 is used as dielectric layer between metal layers, utilize patterned light blockage layer to form character line contact hole and bit line contact hole more in regular turn in the correspondence position of dielectric layer between metal layers, after then in contact hole, inserting the tungsten metal level again, promptly finish character line contact 232 and bit line contact 234,236 respectively.Character line contact 232 with link to each other in order to conductive layer 224 as character line; Bit line contact 234,236 then links to each other with doped region 214 respectively, and bit line contact 234,236 is crisscross arranged with the situation of avoiding being short-circuited.
Please refer to Fig. 4 a and Fig. 4 b, Fig. 4 a and Fig. 4 b show respectively according to the schematic diagram that the multidigit unit vertical memory cell of the embodiment of the invention is carried out the sequencing step.
This memory cell comprises one and has the semiconductor-based end 200 of plural groove 208, and is formed at the plural bit line 214 at the semiconductor-based end 200 that is close to surface, the semiconductor-based ends 200 and groove 208 bottoms.In the present embodiment, bit line 214 is formed at the top at the semiconductor-based end 200 and the bottom of groove respectively, mainly is to form by the phosphonium ion implantation; Bit line insulating layer 216 is to be arranged at each bit line 214 top, and its thickness is about about 300 to 2000 ; One brake-pole dielectric layer 218, is rich in silicon oxide layer 220 and the common stack layers 223 that form of a brake-pole dielectric layer 222, is arranged to compliance on groove 208 sidewalls and bit line insulating layer 216 surfaces, is rich in silicon oxide layer 220 in order to as charge storaging area.
Please refer to Fig. 4 a, when will be to being formed at first B near the groove top
1When carrying out the sequencing step, the bit line 214 of channel bottom is as source electrode, and the bit line 214 at groove top then applies suitable bias voltage again as drain, and electronics promptly can inject the first bit B according to the direction that arrow is advanced
1, and because be one to contain the cause of the oxide layer of a large amount of silicon as the silicon oxide layer 220 that is rich in of charge storaging area, electronics can by local storage in this position and not evenly branch be rich in the middle of the silicon oxide layer 220 in whole.
Please refer to Fig. 4 b, when will be to being formed at the second bit B near channel bottom
2When carrying out the sequencing step, the bit line 214 at groove top is as source electrode, and the bit line 214 of channel bottom then applies suitable bias voltage again as drain, and electronics promptly can inject the second bit B according to the direction that arrow is advanced
2, and because be one to contain the cause of the oxide layer of a large amount of silicon as the silicon oxide layer 220 that is rich in of charge storaging area, electronics can by local storage in this position and not evenly branch be rich in the middle of the silicon oxide layer 220 in whole.Thus, can utilize vertical memory cell provided by the present invention to reach the purpose that stores the multidigit metadata.
Compared to known techniques, the first vertical memory cell of multidigit of the present invention has a rectilinear channel, and it can adjust suitable channel length and prevent the memory cell interference, and is as discussed previously.That is the length of passage is the degree of depth that depends on groove.As long as the degree of depth of groove is enough dark, the situation that just can avoid memory cell to disturb.Moreover because the channel of vertical memory cell is arranged in the semiconductor-based end of trenched side-wall, therefore the usefulness that forms the bit line can be implanted for ion in whole semiconductor-based baseplane.That is, can increase the area of bit line and reduce its resistance, so as to increasing the service speed of vertical memory cell.Simultaneously, the method that silicon oxide layer is used as charge storaging area is rich in utilization provided by the present invention, and effectively the local storage electronics does not make its even distribution, therefore can carry out the storage of multidigit metadata, effectively increases the density of memory cell.
Claims (19)
1. the manufacture method of a multidigit unit vertical memory cell comprises the following steps:
The semiconductor substrate is provided, and this semiconductor-based end, have at least one groove;
In this semiconductor-based end of contiguous this semiconductor-based basal surface and this channel bottom, respectively form a doped region with as the bit line;
Respectively form a bit line insulating layer in each this doped region top;
Sidewall and this bit line insulating layer surface compliance formation one in this groove are rich in silicon oxide layer with the local storage electric charge;
Be rich in the silicon oxide layer top in this and form a dielectric layer; And
Form a conductive layer and insert this groove in this dielectric layer top.
2. the manufacture method of the first vertical memory cell of multidigit according to claim 1 wherein forms this doped region and more comprises the following steps:
Form a clearance wall at this trenched side-wall;
Utilize this clearance wall as a cover curtain and to implementing an ion implant procedure in this semiconductor-based end; And this clearance wall of removal.
3. the manufacture method of the first vertical memory cell of multidigit according to claim 2, wherein this clearance wall is made of silicon nitride.
4. the manufacture method of the first vertical memory cell of multidigit according to claim 2 is wherein carried out this ion implant procedure by phosphonium ion.
5. the manufacture method of the first vertical memory cell of multidigit according to claim 1 wherein forms this bit line insulating layer by thermal oxidation method.
6. the manufacture method of the first vertical memory cell of multidigit according to claim 1, wherein the thickness of this bit line insulating layer is 300 to 2000 .
7. the manufacture method of the first vertical memory cell of multidigit according to claim 1, wherein this thickness that is rich in silicon oxide layer is 50 to 110 .
8. the manufacture method of the first vertical memory cell of multidigit according to claim 1, wherein this is rich between silicon oxide layer and this groove and more comprises a brake-pole dielectric layer.
9. the manufacture method of the first vertical memory cell of multidigit according to claim 8, wherein this brake-pole dielectric layer is a gate pole oxidation layer.
10. the manufacture method of the first vertical memory cell of multidigit according to claim 8, wherein the thickness of this brake-pole dielectric layer is 50 .
11. the manufacture method of the first vertical memory cell of multidigit according to claim 1, wherein this conductive layer is a polysilicon layer.
12. a multidigit unit vertical memory cell is characterized in that described memory cell comprises:
The semiconductor substrate, this semiconductor-based end, have at least one groove;
Plural number bit line was formed at respectively in this semiconductor-based end and this channel bottom of contiguous this semiconductor-based basal surface;
Plural number bit line insulating layer is arranged at each this bit line top;
One is rich in silicon oxide layer, in order to the local storage electric charge, is arranged to compliance this trenched side-wall and this bit line insulating layer surface;
One dielectric layer is arranged at this and is rich in the silicon oxide layer top; And
One character line is arranged at this dielectric layer top and inserts this groove.
13. the first vertical memory cell of multidigit according to claim 12, it is characterized in that: this bit line is the phosphonium ion implantation region.
14. the first vertical memory cell of multidigit according to claim 12, it is characterized in that: the thickness of this bit line insulating layer is 300 to 2000 .
15. the first vertical memory cell of multidigit according to claim 12, it is characterized in that: this bit line insulating layer is an oxide layer.
16. the first vertical memory cell of multidigit according to claim 12, it is characterized in that: this thickness that is rich in silicon oxide layer is 50 to 110 .
17. the first vertical memory cell of multidigit according to claim 12, it is characterized in that: this is rich between silicon oxide layer and this groove and more comprises a brake-pole dielectric layer.
18. the first vertical memory cell of multidigit according to claim 17, it is characterized in that: the thickness of this brake-pole dielectric layer is 50 .
19. the first vertical memory cell of multidigit according to claim 12, it is characterized in that: this character line is a polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031558089A CN1326233C (en) | 2003-08-22 | 2003-08-22 | Multi-element vertical memory and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031558089A CN1326233C (en) | 2003-08-22 | 2003-08-22 | Multi-element vertical memory and its manufacture |
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| Publication Number | Publication Date |
|---|---|
| CN1585111A CN1585111A (en) | 2005-02-23 |
| CN1326233C true CN1326233C (en) | 2007-07-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031558089A Expired - Lifetime CN1326233C (en) | 2003-08-22 | 2003-08-22 | Multi-element vertical memory and its manufacture |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5049956A (en) * | 1989-07-13 | 1991-09-17 | Kabushiki Kaisha Toshiba | Memory cell structure of semiconductor memory device |
| US5315142A (en) * | 1992-03-23 | 1994-05-24 | International Business Machines Corporation | High performance trench EEPROM cell |
| CN1189919A (en) * | 1995-07-05 | 1998-08-05 | 西门子公司 | Method of producing a read-only storage cell arrangement |
| CN1210339A (en) * | 1997-06-06 | 1999-03-10 | 西门子公司 | Dynamic random access memory unit device and manufacture thereof |
| CN1221222A (en) * | 1997-12-22 | 1999-06-30 | 西门子公司 | EEPROM device and manufacture method thereof |
| CN1407626A (en) * | 2001-09-06 | 2003-04-02 | 旺宏电子股份有限公司 | Vertical nitride read out-only memory unit |
| CN1420551A (en) * | 2001-11-21 | 2003-05-28 | 旺宏电子股份有限公司 | Method for mfg. vertical nitride read-only memory unit |
| CN1433079A (en) * | 2002-01-10 | 2003-07-30 | 旺宏电子股份有限公司 | Vertical ROM and its making process |
-
2003
- 2003-08-22 CN CNB031558089A patent/CN1326233C/en not_active Expired - Lifetime
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5049956A (en) * | 1989-07-13 | 1991-09-17 | Kabushiki Kaisha Toshiba | Memory cell structure of semiconductor memory device |
| US5315142A (en) * | 1992-03-23 | 1994-05-24 | International Business Machines Corporation | High performance trench EEPROM cell |
| CN1189919A (en) * | 1995-07-05 | 1998-08-05 | 西门子公司 | Method of producing a read-only storage cell arrangement |
| CN1210339A (en) * | 1997-06-06 | 1999-03-10 | 西门子公司 | Dynamic random access memory unit device and manufacture thereof |
| CN1221222A (en) * | 1997-12-22 | 1999-06-30 | 西门子公司 | EEPROM device and manufacture method thereof |
| CN1407626A (en) * | 2001-09-06 | 2003-04-02 | 旺宏电子股份有限公司 | Vertical nitride read out-only memory unit |
| CN1420551A (en) * | 2001-11-21 | 2003-05-28 | 旺宏电子股份有限公司 | Method for mfg. vertical nitride read-only memory unit |
| CN1433079A (en) * | 2002-01-10 | 2003-07-30 | 旺宏电子股份有限公司 | Vertical ROM and its making process |
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| Publication number | Publication date |
|---|---|
| CN1585111A (en) | 2005-02-23 |
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