CN1328793C - Structure of discontinuous nitride ROM memory cell - Google Patents
Structure of discontinuous nitride ROM memory cell Download PDFInfo
- Publication number
- CN1328793C CN1328793C CNB021411832A CN02141183A CN1328793C CN 1328793 C CN1328793 C CN 1328793C CN B021411832 A CNB021411832 A CN B021411832A CN 02141183 A CN02141183 A CN 02141183A CN 1328793 C CN1328793 C CN 1328793C
- Authority
- CN
- China
- Prior art keywords
- coating
- oxide skin
- layer
- substrate
- discontinuous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to a memory unit of a discontinuous nitride read-only memory (NROM), which at least comprises a substrate, a first and a second ONO laminated grids which are formed on the substrate, an oxidation layer, a polycrystalline silicon layer formed on the oxidation layer, and a source/drain electrode, wherein the ONO laminated grid is formed by that a nitride layer is clamped between two oxide layers, and the oxidation layer is formed on the substrate for covering the first and the second ONO laminated grids; the source/drain electrode is formed in the substrate and is near to the first and the second ONO laminated grids. The structure of the discontinuous NROM unit of the present invention can solve the problem of trapping electrons into the nitride layer and can exactly control the relevant positions of the source/drain electrode and the ONO layer.
Description
Technical field
The invention relates to a kind of structure of nitride read only storage storage location, and particularly about a kind of discontinuous nitride read only storage storage location made from autoregistration process (self-aligned process).
Background technology
Can store the storage device of non-volatile information, for example read-only memory (ROM), programmable read-only memory (prom) and Erasable Programmable Read Only Memory EPROM (EPROM) reach other more senior storage devices and are used for global industry at large.Compared with general storage device, the advanced storage device involves more complicated making and test program usually.The advanced storage device comprises Electrically Erasable Read Only Memory (EEPROM), quickflashing EEPROM and nitride ROM.These advanced storage devices can finish general ROM the work that can not finish, for example, use the circuit of EERPOM device to utilize and be built in wiping and write-in functions in the EEPROM device.
The key property of nitride ROM is that it is to belong to the dibit memory cell, and the dibit memory cell has the multiple-threshold voltages level, per 2 threshold voltage levels store different bits together, and other threshold voltage levels will be stored the side of a bit in memory cell.Wherein, the manufacture method of the memory cell of nitride ROM and general structure see in many documents and the reference.
Please refer to Fig. 1, express the profile of the memory cell of general nitride ROM.At first, provide a substrate 10, and implant source electrode 12 and drain 14 in substrate 10.Then, on substrate 10, form the ONO structure, comprising: go up between oxide skin(coating) 16 and a following oxide skin(coating) 18 for one and clip a nitride layer 17.Then, between the ONO structure, form a plurality of flush types diffusion regions (BD) oxide 20, isolate adjoining ONO structure to form passage 22.In the structure of the memory cell of nitride ROM, each memory cell has dibit, as shown in Figure 1.The memory cell 30 of big zone (scope that big dotted line is irised out among the figure) the single nitride ROM of expression, and less two zones (scope that less dotted line is irised out among the figure) expression first bit 32 and second bit 34.
In the memory cell 30 of nitride ROM, but nitride layer 17 provides the electric charge in the write storage unit to keep mechanism.Under general situation, electronics is to be imported into nitride layer 17 during memory cell writes, yet the electronics that is introduced into nitride layer 17 is absorbed in nitride and can't moves freely, and the hole is to be imported into nitride layer 17 with neutralization or in conjunction with electronics during cell erase.
In addition, inject phenomenon according to hot electron, some hot electrons can penetrate down oxide skin(coating) 18, and concentrate on nitride layer 17, particularly instantly during the very thin thickness of oxide skin(coating) 18, owing to the partial charge that hot electron produced, the part threshold voltage that makes energising back passage 22 is higher than the threshold voltage of passage 22 other parts.When memory cell was carried out write operation, the threshold voltage that partial charge and rising can occur entered conducting state with disable memory cells.Under general state, when promptly partial charge does not occur, read the threshold voltage that voltage can overcome passage 22, and make the passage 22 can conducting.
In addition, utilize the memory cell of conventional nitride read-only memory of the several steps manufacturing of photolithography (photolithography) to have some defectives.For example, implant and bit are not easy to form in correct position and be shifted, cause nitride ROM usefulness reduce widely.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of structure of memory cell of discontinuous nitride ROM, makes the relevant position of source/drain and NO structure to control easily and exactly.
According to purpose of the present invention, a kind of structure of memory cell of discontinuous nitride ROM is proposed, comprise at least: a substrate; A plurality of NO stacked gates are formed on this substrate with separating, and wherein each NO stacked gate is stacked in down on the oxide skin(coating) by nitride layer and forms, and each NO stacked gate has bottom width d; Oxide layer is formed on this substrate to fill the space between the described NO stacked gate and to cover described NO stacked gate, and wherein this thickness of oxide layer is greater than the height of described NO stacked gate; Polysilicon layer is formed on this oxide layer; And a plurality of source/drains, be formed in this substrate and close described NO stacked gate.
According to purpose of the present invention, a kind of memory cell of discontinuous nitride ROM is proposed, comprise at least: a substrate; The one NO stacked gate and the 2nd NO stacked gate are formed on the substrate with separating, and wherein this first, second NO stacked gate is stacked in down on the oxide skin(coating) by nitride layer respectively and forms, and this first, second NO piled grids has bottom width d respectively; Oxide layer is formed on the substrate to fill the space between first, second NO stacked gate and to cover a NO stacked gate and the 2nd NO stacked gate, and wherein this thickness of oxide layer is greater than the height of this first, second NO stacked gate; Polysilicon layer is formed on the oxide layer; And source/drain, be formed in the substrate and a close NO stacked gate and the 2nd NO stacked gate.
According to purpose of the present invention, a kind of manufacture method of memory cell structure of discontinuous nitride ROM is proposed, may further comprise the steps: a substrate is provided, has following oxide skin(coating) on this substrate, be formed on the nitride layer on this time oxide skin(coating) and be formed on last oxide skin(coating) on this nitride layer; On this, form the patterning photoresist layer on the oxide skin(coating), and should go up oxide skin(coating) to form the discontinuous oxide skin(coating) of going up, remove this patterning photoresist layer then according to this patterning photoresist layer etching; The both sides of oxide skin(coating) form at interval on discontinuous, and each is every having bottom width d, and a distance is separated at two adjacent intervals; In substrate, implant source/drain with self-registered technology; Order is removed and should be gone up oxide skin(coating) and this nitride layer, and the nitride layer that is covered by described interval is stayed on this time oxide skin(coating); Remove described interval, and remove this time oxide skin(coating) according to the nitride layer that stays, forming a plurality of stacked gates of being made up of this nitride layer and this time oxide skin(coating) on this substrate, and each stacked gate has this bottom width d; Forming oxide layer on this substrate to fill the space between the described stacked gate and to cover described stacked gate, wherein this thickness of oxide layer is greater than the height of described stacked gate; And on this oxide layer, form polysilicon layer.
According to purpose of the present invention, a kind of manufacture method of memory cell structure of discontinuous nitride ROM is proposed, may further comprise the steps: a substrate is provided, have following oxide skin(coating) on this substrate, be formed on nitride layer on this time oxide skin(coating), be formed on the last oxide skin(coating) on this nitride layer, and be formed on the patterning photoresist layer on the oxide skin(coating) on this; According to this patterning photoresist layer, etching should be gone up oxide skin(coating); In substrate, implant source/drain with self-registered technology; The patterning photoresist layer of truncated section is to expose the last oxide skin(coating) with width d; According to the patterning photoresist layer after pruning, etching should be gone up oxide skin(coating) to form the discontinuous oxide skin(coating) of going up, and removed this patterning photoresist layer then; The both sides of oxide skin(coating) form at interval on discontinuous, and each is every having bottom width d, and a distance is separated at two adjacent intervals; Order is removed and should be gone up oxide skin(coating) and this nitride layer, and the nitride layer that is covered by described interval is stayed on this time oxide skin(coating); Remove described interval, and remove this time oxide skin(coating) according to the nitride layer that stays, with a plurality of stacked gates of being made up of this nitride layer and this time oxide skin(coating) of formation on this substrate, and each stacked gate has this bottom width d; Forming oxide layer on this substrate to fill the space between the described stacked gate and to cover described stacked gate, wherein this thickness of oxide layer is greater than the height of described stacked gate; And on this oxide layer, form polysilicon layer.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, hereinafter the spy also elaborates in conjunction with the accompanying drawings with preferred embodiment.
Description of drawings
Fig. 1 represents the profile of the memory cell of general nitride ROM;
Fig. 2 A～2F represents that the autoregistration process of embodiments of the invention one makes the manufacture method of the memory cell of discontinuous nitride ROM;
Fig. 2 G represents the profile of memory cell of the discontinuous nitride ROM of the embodiment of the invention one;
Fig. 3 A～3F represents the manufacture method of memory cell of the discontinuous nitride ROM made from the autoregistration process of embodiments of the invention two; And
Fig. 3 G represents the profile of memory cell of the discontinuous nitride ROM of the embodiment of the invention two.
Embodiment
The present invention is a memory cell of making discontinuous nitride ROM with the autoregistration process.Below enumerate two kinds of processes and make the memory cell of discontinuous nitride ROM of the present invention.In addition, for clearer understanding the present invention, do not have directly related element with the present invention and will repeat no more at this.Therefore, embodiment that is set forth and accompanying drawing are just in order to explanation, and unrestricted practical ranges of the present invention.
Embodiment one: the method one of making the memory cell of nitride ROM
What Fig. 2 A～2F represented embodiments of the invention one makes the manufacture method of the memory cell of discontinuous nitride ROM with the autoregistration process.At first, in Fig. 2 A, provide substrate 210, and form the ONO layer on substrate 210.Wherein the ONO layer comprises that oxide skin(coating) 218, nitride layer 217 reach upward oxide skin(coating) 216 down.Following oxide skin(coating) 218 is formed on the substrate 210, be called tunnel oxide (tunneling oxide layer) again, and nitride layer 217 is formed on down on the oxide skin(coating) 218, is formed on the nitride layer 217 and go up oxide skin(coating) 216.Then, on last oxide skin(coating) 216, form patterned light blockage layer (patterned PR) 219.
Wherein, the thickness of following oxide skin(coating) 218 and preferably is about 70 between 50 ～150 scopes.The thickness of nitride layer 217 is between 20 ～150 scopes.Because last oxide skin(coating) 216 will be removed in follow-up making, so the thickness of last oxide skin(coating) 216 is not particularly limited.In addition, each layer thickness of ONO layer is independently not have to be mutually related, and can change thickness range according to its practical application.
Then, according to oxide skin(coating) 216 in patterned light blockage layer 219 etchings.Keep the last oxide skin(coating) 216 of photoresist layer 219 coverings that are patterned, and remove the last oxide skin(coating) 216 that other are not capped.Afterwards, remove patterned light blockage layer 219, shown in Fig. 2 B.
Then, shown in Fig. 2 C, with a film uniform deposition on last oxide skin(coating) 216 and part nitride layer 217.Utilize the film of such as non-grade again, form at interval 221 with the both sides of oxide skin(coating) 216 on discontinuous to the etching program etching part.Wherein, film can be any material that is different from nitride, for example oxide or polysilicon.It should be noted that 221 bottom width is prior set point d at interval.
Then, implant source/drain 222 with the autoregistration process, implant impurity for example is N type alloy phosphorus or arsenic ion, or P type dopant boron (B) or boron fluoride ion (BF
2 +).
Then, order is removed and is gone up oxide skin(coating) 216 and nitride layer 217, shown in Fig. 2 D.After the etching, be not spaced apart 221 217 of nitride layers that cover and be removed, other is spaced apart 221 217 of nitride layers that cover and stays down on the oxide skin(coating) 218.Then, remove interval 221.Remove oxide skin(coating) 218 down according to residual nitride layer 217 again, shown in Fig. 2 E.
So far step has formed a plurality of NO stacked gates of being made up of nitride layer 217 and following oxide skin(coating) 218 on the substrate 210.Then, shown in Fig. 2 F, forming oxide layer 226 on the substrate 210 to fill space and the cover nitride layer 217 between the adjacent NO stacked gate.Wherein, the thickness of oxide layer 226 is greater than the height of NO stacked gate.
Then, on oxide layer 226, cover polysilicon layer 228 with as word line (wordline).Wherein, polysilicon layer 228 can be amorphous silicon or doped polycrystalline silicon, but wherein polysilicon layer is Doping Phosphorus or arsenic ion.In addition, in some special process, can on polysilicon layer 228, deposit one deck tungsten silicide (WSi again
x) (not being shown among Fig. 2 F), with the making of the memory cell of finishing discontinuous nitride ROM.
The structure of the memory cell of nitride ROM among the embodiment one:
Fig. 2 G represents the profile of memory cell of the discontinuous nitride ROM of the embodiment of the invention one.Implant source/drain 222 at substrate 210.And the narrow stacked gate of a plurality of regular shape of formation on the substrate 210, each stacked gate is the NO structure, comprising: following oxide skin(coating) 218 and nitride layer 217.Oxide layer 226 is separated the NO structure, and forms the memory cell structure of discontinuous nitride ROM.Oxide layer 226 tops also cover polysilicon layer 228.Among Fig. 2 G, the memory cell 230 of a nitride ROM is represented in big zone (scope of great circle among the figure), and two less peak widths are d (scope of ringlet among the figure) expression first bit 232 and second bit 233.In addition, source/drain 222 is to implant with self-aligned manner, and step is afterwards also carried out with self-aligned manner.Therefore, the relevant position of source/drain 222 and NO structure can be controlled easily and exactly.
Embodiment two: the method two of making the memory cell of nitride ROM
What Fig. 3 A～3F represented embodiments of the invention two makes the manufacture method of the memory cell of discontinuous nitride ROM with the autoregistration process.Wherein, embodiment two is roughly the same with the manufacture method of embodiment one, only does a little correction or improvement in part steps.
Fig. 3 A is identical with Fig. 2 A.Among Fig. 3 A, form the ONO layer on substrate 310, wherein, the ONO layer comprises that oxide skin(coating) 316, nitride layer 317 reach oxide skin(coating) (tunnel oxidation layer) 318 down.Then, utilize photolithography to make, on last oxide skin(coating) 316, form patterned light blockage layer (PR) 319.Same, each layer thickness of ONO layer is independent and do not have interrelatedly, and can change thickness range according to its practical application.
According to oxide skin(coating) 316 in patterned light blockage layer 319 etchings.Then, implant source/drain 322 with the autoregistration process.Source/drain 322 for example is boron (B) or boron fluoride ion (BF2+).Then, (de-scummed) the patterning photoresist layer 319 partly of pruning is to expose the last oxide skin(coating) 316 with preset width d, shown in Fig. 3 B.
Then, according to oxide skin(coating) 316 in patterning photoresist layer 319 etchings after pruning.Remove patterning photoresist layer 319 again, shown in Fig. 3 C.
Then, with a film uniform deposition above last oxide skin(coating) 316 and part nitride layer 317, shown in Fig. 3 D.To etching program film is carried out etching with non-grade again, form at interval 321 with the both sides of oxide skin(coating) 316 on discontinuous.Wherein film can be any material that is different from nitride.In addition, 321 bottom width is controlled at predetermined value d at interval.
Then, remove the discontinuous oxide skin(coating) 316 of going up, make at interval 321 to be exposed on the nitride layer 317.According to interval 321 nitride etching layers 317, the nitride layers 317 that are not spaced apart 321 coverings are removed again, other is spaced apart 321 317 of nitride layers that cover and stays down on the oxide skin(coating) 318.Then, will 321 remove at interval, shown in Fig. 3 E.Remove according to 317 pairs of following oxide skin(coating)s 318 of residual nitride layer again, to form a plurality of NO stacked gates.
Then, forming oxide layer 326 on the substrate 310 to cover the NO stacked gate and to fill space between the adjacent NO stacked gate.Wherein, the thickness of oxide layer 326 is greater than the height of NO stacked gate.Then, above oxide layer 326, cover polysilicon layer 328, shown in Fig. 3 F.
The structure of the memory cell of nitride ROM among the embodiment two
Fig. 3 G represents the profile of memory cell of the discontinuous nitride ROM of the embodiment of the invention two.Implant source/drain 322 at substrate 310 places.And the narrow stacked gate of a plurality of regular shape is also arranged on substrate 310, each stacked gate is the NO structure, comprising: following oxide skin(coating) 318 and nitride layer 317.Oxide layer 326 is separated the NO structure, and forms the memory cell structure of discontinuous nitride ROM.Above oxide layer 326, also cover polysilicon layer 328.Among Fig. 3 G, big zone (scope of great circle among the figure) is the memory cell 330 of a nitride ROM of expression, and two less peak widths are that d (scope of ringlet among the figure) is expression first bit 332 and second bit 333.In addition, source/drain 322 is to implant with self-aligned manner, and step is afterwards also carried out with self-aligned manner.Therefore, the relevant position of source/drain 322 and NO structure can be controlled easily and exactly.
In sum; though the present invention has still described with preferred embodiment; but it is not in order to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make various changes and improvement, so protection scope of the present invention is that scope with claims of the application is limited.
Claims (10)
1. the manufacture method of the memory cell structure of a discontinuous nitride ROM may further comprise the steps:
A substrate is provided, has following oxide skin(coating) on this substrate, be formed on the nitride layer on this time oxide skin(coating) and be formed on last oxide skin(coating) on this nitride layer;
On this, form the patterning photoresist layer on the oxide skin(coating), and should go up oxide skin(coating) to form the discontinuous oxide skin(coating) of going up, remove this patterning photoresist layer then according to this patterning photoresist layer etching;
The both sides of oxide skin(coating) form at interval on discontinuous, and each is every having bottom width d, and a distance is separated at two adjacent intervals;
In substrate, implant source/drain with self-registered technology;
Order is removed and should be gone up oxide skin(coating) and this nitride layer, and the nitride layer that is covered by described interval is stayed on this time oxide skin(coating);
Remove described interval, and remove this time oxide skin(coating) according to the nitride layer that stays, forming a plurality of stacked gates of being made up of this nitride layer and this time oxide skin(coating) on this substrate, and each stacked gate has this bottom width d;
Forming oxide layer on this substrate to fill the space between the described stacked gate and to cover described stacked gate, wherein this thickness of oxide layer is greater than the height of described stacked gate; And
On this oxide layer, form polysilicon layer.
2. manufacture method according to claim 1 is characterized in that the step that forms described interval comprises:
Uniform deposition film above the oxide skin(coating) on discontinuous, and cover the part surface of this nitride layer;
To etching program this film is carried out etching by non-grade, form described interval with the both sides of oxide skin(coating) on discontinuous, and each is every have this bottom width d on this nitride layer.
3. manufacture method according to claim 1 is characterized in that this polysilicon layer Doping Phosphorus or arsenic ion.
4. manufacture method according to claim 1 is characterized in that very P type alloy of this source/drain.
5. manufacture method according to claim 1 is characterized in that very N type alloy of this source/drain.
6. the manufacture method of the memory cell structure of a discontinuous nitride ROM may further comprise the steps:
A substrate is provided, has following oxide skin(coating) on this substrate, be formed on nitride layer on this time oxide skin(coating), be formed on the last oxide skin(coating) on this nitride layer, and be formed on the patterning photoresist layer on the oxide skin(coating) on this;
According to this patterning photoresist layer, etching should be gone up oxide skin(coating);
In substrate, implant source/drain with self-registered technology;
The patterning photoresist layer of truncated section is to expose the last oxide skin(coating) with width d;
According to the patterning photoresist layer after pruning, etching should be gone up oxide skin(coating) to form the discontinuous oxide skin(coating) of going up, and removed this patterning photoresist layer then;
The both sides of oxide skin(coating) form at interval on discontinuous, and each is every having bottom width d, and a distance is separated at two adjacent intervals;
Order is removed and should be gone up oxide skin(coating) and this nitride layer, and the nitride layer that is covered by described interval is stayed on this time oxide skin(coating);
Remove described interval, and remove this time oxide skin(coating) according to the nitride layer that stays, with a plurality of stacked gates of being made up of this nitride layer and this time oxide skin(coating) of formation on this substrate, and each stacked gate has this bottom width d;
Forming oxide layer on this substrate to fill the space between the described stacked gate and to cover described stacked gate, wherein this thickness of oxide layer is greater than the height of described stacked gate; And
On this oxide layer, form polysilicon layer.
7. manufacture method according to claim 6 is characterized in that the step that forms described interval comprises:
Uniform deposition film above the oxide skin(coating) on discontinuous, and cover the part surface of this nitride layer;
To etching program this film is carried out etching by non-grade, form described interval with the both sides of oxide skin(coating) on discontinuous, and each is every have this bottom width d on this nitride layer.
8. manufacture method according to claim 6 is characterized in that this polysilicon layer Doping Phosphorus or arsenic ion.
9. manufacture method according to claim 6 is characterized in that very P type alloy of this source/drain.
10. manufacture method according to claim 6 is characterized in that very N type alloy of this source/drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021411832A CN1328793C (en) | 2002-07-09 | 2002-07-09 | Structure of discontinuous nitride ROM memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021411832A CN1328793C (en) | 2002-07-09 | 2002-07-09 | Structure of discontinuous nitride ROM memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1467855A CN1467855A (en) | 2004-01-14 |
| CN1328793C true CN1328793C (en) | 2007-07-25 |
Family
ID=34147735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021411832A Expired - Fee Related CN1328793C (en) | 2002-07-09 | 2002-07-09 | Structure of discontinuous nitride ROM memory cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1328793C (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796140A (en) * | 1994-08-23 | 1998-08-18 | Nippon Steel Corporation | Nonvolatile semiconductor memory device and a method of making the same |
| US5877523A (en) * | 1996-12-02 | 1999-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-level split- gate flash memory cell |
| US6261904B1 (en) * | 2000-02-10 | 2001-07-17 | Advanced Micro Devices, Inc. | Dual bit isolation scheme for flash devices |
| US6269023B1 (en) * | 2000-05-19 | 2001-07-31 | Advanced Micro Devices, Inc. | Method of programming a non-volatile memory cell using a current limiter |
| US6303439B1 (en) * | 1999-11-24 | 2001-10-16 | United Microelectronics Corp. | Fabrication method for a two-bit flash memory cell |
| US20020041526A1 (en) * | 2000-07-03 | 2002-04-11 | Yasuhiro Sugita | Nonvolatile semiconductor memory device, process of manufacturing the same and method of operating the same |
-
2002
- 2002-07-09 CN CNB021411832A patent/CN1328793C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796140A (en) * | 1994-08-23 | 1998-08-18 | Nippon Steel Corporation | Nonvolatile semiconductor memory device and a method of making the same |
| US5877523A (en) * | 1996-12-02 | 1999-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-level split- gate flash memory cell |
| US6303439B1 (en) * | 1999-11-24 | 2001-10-16 | United Microelectronics Corp. | Fabrication method for a two-bit flash memory cell |
| US6261904B1 (en) * | 2000-02-10 | 2001-07-17 | Advanced Micro Devices, Inc. | Dual bit isolation scheme for flash devices |
| US6269023B1 (en) * | 2000-05-19 | 2001-07-31 | Advanced Micro Devices, Inc. | Method of programming a non-volatile memory cell using a current limiter |
| US20020041526A1 (en) * | 2000-07-03 | 2002-04-11 | Yasuhiro Sugita | Nonvolatile semiconductor memory device, process of manufacturing the same and method of operating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1467855A (en) | 2004-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5705415A (en) | Process for forming an electrically programmable read-only memory cell | |
| US20210210623A1 (en) | Methods Of Forming NAND Cell Units | |
| US5776787A (en) | Spacer flash cell process | |
| US6818944B2 (en) | Nonvolatile memory devices and methods of fabricating the same | |
| US20050269622A1 (en) | Semiconductor memory array of floating gate memory cells with program/erase and select gates, and methods of making and operating same | |
| CN100533743C (en) | Nonvolatile memory devices and methods of fabricating the same | |
| US7563676B2 (en) | NOR-type flash memory cell array and method for manufacturing the same | |
| US20100323511A1 (en) | Nonvolatile memories with laterally recessed charge-trapping dielectric | |
| US5409854A (en) | Method for forming a virtual-ground flash EPROM array with floating gates that are self aligned to the field oxide regions of the array | |
| US7238974B2 (en) | Semiconductor device and method of producing a semiconductor device | |
| US20090026573A1 (en) | Semiconductor memory device and method for manufacturing the same | |
| JP2007142468A (en) | Semiconductor device | |
| US7539065B2 (en) | Method of programming non-volatile memory | |
| JP2003282745A (en) | Semiconductor memory device | |
| US20090251972A1 (en) | Nonvolatile memory arrays with charge trapping dielectric and with non-dielectric nanodots | |
| CN1328793C (en) | Structure of discontinuous nitride ROM memory cell | |
| US7145802B2 (en) | Programming and manufacturing method for split gate memory cell | |
| EP0612108B1 (en) | Double polysilicon EEPROM cell and corresponding manufacturing process | |
| US10916558B2 (en) | NOR flash memory and method of fabricating the same | |
| US6093603A (en) | Fabricating semiconductor memory devices with improved cell isolation | |
| US5151760A (en) | Integrated circuit with improved capacitive coupling | |
| US11088156B2 (en) | Memory cells with extended erase gate, and process of fabrication | |
| US6670672B1 (en) | Structure of discrete NROM cell | |
| US20060073702A1 (en) | Memory structure and manufacturing as well as programming method thereof | |
| JPH0786439A (en) | Nonvolatile semiconductor storage device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070725 Termination date: 20190709 |