CN1333454C - 具有应变膜的绝缘体上硅装置及用于形成应变膜的方法 - Google Patents
具有应变膜的绝缘体上硅装置及用于形成应变膜的方法 Download PDFInfo
- Publication number
- CN1333454C CN1333454C CNB03813263XA CN03813263A CN1333454C CN 1333454 C CN1333454 C CN 1333454C CN B03813263X A CNB03813263X A CN B03813263XA CN 03813263 A CN03813263 A CN 03813263A CN 1333454 C CN1333454 C CN 1333454C
- Authority
- CN
- China
- Prior art keywords
- silicon
- oxide layer
- buried oxide
- groove
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012212 insulator Substances 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 74
- 239000010703 silicon Substances 0.000 claims abstract description 74
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 150000003376 silicon Chemical class 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 25
- 230000001419 dependent effect Effects 0.000 claims description 8
- 230000008676 import Effects 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000969 carrier Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 9
- 239000010409 thin film Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 4
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Abstract
Description
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/178,542 | 2002-06-25 | ||
US10/178,542 US6680240B1 (en) | 2002-06-25 | 2002-06-25 | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1659696A CN1659696A (zh) | 2005-08-24 |
CN1333454C true CN1333454C (zh) | 2007-08-22 |
Family
ID=29999123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB03813263XA Expired - Lifetime CN1333454C (zh) | 2002-06-25 | 2003-06-04 | 具有应变膜的绝缘体上硅装置及用于形成应变膜的方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6680240B1 (zh) |
EP (1) | EP1516362A2 (zh) |
JP (1) | JP4452883B2 (zh) |
KR (1) | KR100996725B1 (zh) |
CN (1) | CN1333454C (zh) |
AU (1) | AU2003238916A1 (zh) |
TW (1) | TWI289895B (zh) |
WO (1) | WO2004001798A2 (zh) |
Families Citing this family (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004507084A (ja) * | 2000-08-16 | 2004-03-04 | マサチューセッツ インスティテュート オブ テクノロジー | グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス |
WO2002082514A1 (en) * | 2001-04-04 | 2002-10-17 | Massachusetts Institute Of Technology | A method for semiconductor device fabrication |
WO2003079415A2 (en) * | 2002-03-14 | 2003-09-25 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
US7074623B2 (en) * | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US7307273B2 (en) * | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
US7335545B2 (en) * | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US6946373B2 (en) * | 2002-11-20 | 2005-09-20 | International Business Machines Corporation | Relaxed, low-defect SGOI for strained Si CMOS applications |
FR2847715B1 (fr) * | 2002-11-25 | 2005-03-11 | Commissariat Energie Atomique | Circuit integre comportant des sous-ensembles connectes en serie |
US6717216B1 (en) * | 2002-12-12 | 2004-04-06 | International Business Machines Corporation | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device |
US7157774B2 (en) * | 2003-01-31 | 2007-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained silicon-on-insulator transistors with mesa isolation |
US6870179B2 (en) * | 2003-03-31 | 2005-03-22 | Intel Corporation | Increasing stress-enhanced drive current in a MOS transistor |
US7081395B2 (en) * | 2003-05-23 | 2006-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7105390B2 (en) * | 2003-12-30 | 2006-09-12 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US7268058B2 (en) * | 2004-01-16 | 2007-09-11 | Intel Corporation | Tri-gate transistors and methods to fabricate same |
US20050186722A1 (en) * | 2004-02-25 | 2005-08-25 | Kuan-Lun Cheng | Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions |
US7154118B2 (en) * | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US20050266632A1 (en) * | 2004-05-26 | 2005-12-01 | Yun-Hsiu Chen | Integrated circuit with strained and non-strained transistors, and method of forming thereof |
US7579280B2 (en) * | 2004-06-01 | 2009-08-25 | Intel Corporation | Method of patterning a film |
US7042009B2 (en) * | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US6991998B2 (en) * | 2004-07-02 | 2006-01-31 | International Business Machines Corporation | Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7135372B2 (en) * | 2004-09-09 | 2006-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained silicon device manufacturing method |
US7071064B2 (en) * | 2004-09-23 | 2006-07-04 | Intel Corporation | U-gate transistors and methods of fabrication |
US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
US7422946B2 (en) * | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
JP4603845B2 (ja) * | 2004-10-12 | 2010-12-22 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7306997B2 (en) | 2004-11-10 | 2007-12-11 | Advanced Micro Devices, Inc. | Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor |
US20060113603A1 (en) * | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid semiconductor-on-insulator structures and related methods |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US7193279B2 (en) * | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
US7518196B2 (en) * | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) * | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
US7563701B2 (en) * | 2005-03-31 | 2009-07-21 | Intel Corporation | Self-aligned contacts for transistors |
US7858481B2 (en) * | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7402875B2 (en) * | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US20070090416A1 (en) * | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7479421B2 (en) * | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US20070090408A1 (en) * | 2005-09-29 | 2007-04-26 | Amlan Majumdar | Narrow-body multiple-gate FET with dominant body transistor for high performance |
US7759739B2 (en) * | 2005-10-27 | 2010-07-20 | International Business Machines Corporation | Transistor with dielectric stressor elements |
DE102005052055B3 (de) | 2005-10-31 | 2007-04-26 | Advanced Micro Devices, Inc., Sunnyvale | Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben |
GB2445511B (en) * | 2005-10-31 | 2009-04-08 | Advanced Micro Devices Inc | An embedded strain layer in thin soi transistors and a method of forming the same |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US7396711B2 (en) * | 2005-12-27 | 2008-07-08 | Intel Corporation | Method of fabricating a multi-cornered film |
US7449373B2 (en) * | 2006-03-31 | 2008-11-11 | Intel Corporation | Method of ion implanting for tri-gate devices |
US7670928B2 (en) * | 2006-06-14 | 2010-03-02 | Intel Corporation | Ultra-thin oxide bonding for S1 to S1 dual orientation bonding |
US7544594B2 (en) * | 2006-06-28 | 2009-06-09 | Intel Corporation | Method of forming a transistor having gate protection and transistor formed according to the method |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
KR100835413B1 (ko) * | 2006-12-05 | 2008-06-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 미세 비아홀 형성방법 |
US20080157225A1 (en) * | 2006-12-29 | 2008-07-03 | Suman Datta | SRAM and logic transistors with variable height multi-gate transistor architecture |
US8558278B2 (en) * | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
KR101052868B1 (ko) * | 2008-02-29 | 2011-07-29 | 주식회사 하이닉스반도체 | Soi 소자 및 그의 제조방법 |
US7943961B2 (en) * | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US20100019322A1 (en) * | 2008-07-23 | 2010-01-28 | International Business Machines Corporation | Semiconductor device and method of manufacturing |
US7808051B2 (en) * | 2008-09-29 | 2010-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell without OD space effect in Y-direction |
CN102024706B (zh) * | 2009-09-22 | 2012-06-20 | 中芯国际集成电路制造(上海)有限公司 | 用于制造半导体器件的方法 |
US8258031B2 (en) * | 2010-06-15 | 2012-09-04 | International Business Machines Corporation | Fabrication of a vertical heterojunction tunnel-FET |
US9406798B2 (en) * | 2010-08-27 | 2016-08-02 | Acorn Technologies, Inc. | Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer |
JP6005364B2 (ja) * | 2012-02-06 | 2016-10-12 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法及び半導体装置 |
US9515181B2 (en) | 2014-08-06 | 2016-12-06 | Qualcomm Incorporated | Semiconductor device with self-aligned back side features |
JP6559745B2 (ja) | 2017-08-23 | 2019-08-14 | 株式会社東芝 | 半導体デバイス検査装置、半導体デバイス検査方法、そのプログラム、半導体装置およびその製造方法 |
JP2018032877A (ja) * | 2017-11-29 | 2018-03-01 | ラピスセミコンダクタ株式会社 | 半導体装置 |
JP2019125747A (ja) | 2018-01-18 | 2019-07-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
KR102396978B1 (ko) * | 2018-11-16 | 2022-05-11 | 삼성전자주식회사 | 반도체 장치 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2327146A (en) * | 1997-07-10 | 1999-01-13 | Ericsson Telefon Ab L M | Thermal insulation of integrated circuit components |
JP2002124564A (ja) * | 2000-09-12 | 2002-04-26 | Zarlink Semiconductor Ltd | 半導体デバイス |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4604162A (en) * | 1983-06-13 | 1986-08-05 | Ncr Corporation | Formation and planarization of silicon-on-insulator structures |
US5270265A (en) * | 1992-09-01 | 1993-12-14 | Harris Corporation | Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure |
US5561302A (en) | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US5811283A (en) * | 1996-08-13 | 1998-09-22 | United Microelectronics Corporation | Silicon on insulator (SOI) dram cell structure and process |
US6211039B1 (en) | 1996-11-12 | 2001-04-03 | Micron Technology, Inc. | Silicon-on-insulator islands and method for their formation |
US6045625A (en) * | 1996-12-06 | 2000-04-04 | Texas Instruments Incorporated | Buried oxide with a thermal expansion matching layer for SOI |
JP3676910B2 (ja) * | 1997-07-30 | 2005-07-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体装置及び半導体アイランドの形成方法 |
US6054343A (en) * | 1998-01-26 | 2000-04-25 | Texas Instruments Incorporated | Nitride trench fill process for increasing shallow trench isolation (STI) robustness |
JP2000294623A (ja) * | 1999-04-02 | 2000-10-20 | Fuji Electric Co Ltd | 誘電体分離基板の製造方法 |
JP2000332099A (ja) * | 1999-05-21 | 2000-11-30 | Matsushita Electronics Industry Corp | 半導体装置およびその製造方法 |
US6245600B1 (en) * | 1999-07-01 | 2001-06-12 | International Business Machines Corporation | Method and structure for SOI wafers to avoid electrostatic discharge |
US6573565B2 (en) * | 1999-07-28 | 2003-06-03 | International Business Machines Corporation | Method and structure for providing improved thermal conduction for silicon semiconductor devices |
US6426252B1 (en) * | 1999-10-25 | 2002-07-30 | International Business Machines Corporation | Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap |
US20020046985A1 (en) * | 2000-03-24 | 2002-04-25 | Daneman Michael J. | Process for creating an electrically isolated electrode on a sidewall of a cavity in a base |
US6403482B1 (en) * | 2000-06-28 | 2002-06-11 | International Business Machines Corporation | Self-aligned junction isolation |
TW501227B (en) * | 2000-08-11 | 2002-09-01 | Samsung Electronics Co Ltd | SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same |
DE10040464A1 (de) * | 2000-08-18 | 2002-02-28 | Infineon Technologies Ag | Grabenkondensator und Verfahren zu seiner Herstellung |
JP2002076336A (ja) * | 2000-09-01 | 2002-03-15 | Mitsubishi Electric Corp | 半導体装置およびsoi基板 |
DE10054109C2 (de) * | 2000-10-31 | 2003-07-10 | Advanced Micro Devices Inc | Verfahren zum Bilden eines Substratkontakts in einem Feldeffekttransistor, der über einer vergrabenen Isolierschicht gebildet ist |
US6506620B1 (en) * | 2000-11-27 | 2003-01-14 | Microscan Systems Incorporated | Process for manufacturing micromechanical and microoptomechanical structures with backside metalization |
US6524929B1 (en) * | 2001-02-26 | 2003-02-25 | Advanced Micro Devices, Inc. | Method for shallow trench isolation using passivation material for trench bottom liner |
-
2002
- 2002-06-25 US US10/178,542 patent/US6680240B1/en not_active Expired - Lifetime
-
2003
- 2003-06-04 EP EP03734436A patent/EP1516362A2/en not_active Withdrawn
- 2003-06-04 WO PCT/US2003/017824 patent/WO2004001798A2/en active Application Filing
- 2003-06-04 AU AU2003238916A patent/AU2003238916A1/en not_active Abandoned
- 2003-06-04 KR KR1020047021192A patent/KR100996725B1/ko not_active IP Right Cessation
- 2003-06-04 JP JP2004515743A patent/JP4452883B2/ja not_active Expired - Fee Related
- 2003-06-04 CN CNB03813263XA patent/CN1333454C/zh not_active Expired - Lifetime
- 2003-06-18 TW TW092116498A patent/TWI289895B/zh not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2327146A (en) * | 1997-07-10 | 1999-01-13 | Ericsson Telefon Ab L M | Thermal insulation of integrated circuit components |
JP2002124564A (ja) * | 2000-09-12 | 2002-04-26 | Zarlink Semiconductor Ltd | 半導体デバイス |
Also Published As
Publication number | Publication date |
---|---|
JP4452883B2 (ja) | 2010-04-21 |
WO2004001798A3 (en) | 2004-07-29 |
US20040018668A1 (en) | 2004-01-29 |
AU2003238916A8 (en) | 2004-01-06 |
EP1516362A2 (en) | 2005-03-23 |
JP2005531144A (ja) | 2005-10-13 |
WO2004001798A2 (en) | 2003-12-31 |
US6680240B1 (en) | 2004-01-20 |
KR20050013248A (ko) | 2005-02-03 |
AU2003238916A1 (en) | 2004-01-06 |
TWI289895B (en) | 2007-11-11 |
TW200400564A (en) | 2004-01-01 |
KR100996725B1 (ko) | 2010-11-25 |
CN1659696A (zh) | 2005-08-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1333454C (zh) | 具有应变膜的绝缘体上硅装置及用于形成应变膜的方法 | |
US7612405B2 (en) | Fabrication of FinFETs with multiple fin heights | |
US7355262B2 (en) | Diffusion topography engineering for high performance CMOS fabrication | |
US6787423B1 (en) | Strained-silicon semiconductor device | |
WO2004068586A1 (en) | Mosfet device with tensile strained substrate and method of making the same | |
CN102169896B (zh) | 一种沟槽型功率mos晶体管的制造方法 | |
CN104009070A (zh) | 用于鳍状场效应晶体管的金属栅极和栅极接触件结构 | |
JP2008041901A (ja) | 半導体装置及びその製造方法 | |
US20190378910A1 (en) | Semiconductor structure and manufacturing method for same | |
US8946819B2 (en) | Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same | |
CN101034709B (zh) | 高耐压半导体集成电路装置、电介质分离型半导体装置 | |
US6642536B1 (en) | Hybrid silicon on insulator/bulk strained silicon technology | |
CN104576501B (zh) | 一种半导体器件及其制造方法 | |
KR20000003493A (ko) | 이중막 실리콘웨이퍼를 이용한 금속-산화막-반도체 전계효과트랜지스터 제조방법 | |
CN103367227B (zh) | 半导体器件制造方法 | |
CN113013228A (zh) | 一种提升ldmos性能的方法 | |
CN103367226A (zh) | 半导体器件制造方法 | |
CN106558489A (zh) | 一种纳米线结构、围栅纳米线器件及其制造方法 | |
CN102751292B (zh) | 一种基于三多晶SiGe HBT的混合晶面应变BiCMOS集成器件及制备方法 | |
CN104282754A (zh) | 高性能高集成度l形栅控肖特基势垒隧穿晶体管 | |
CN102723342B (zh) | 一种混合晶面垂直沟道应变BiCMOS集成器件及制备方法 | |
CN101834158B (zh) | 绝缘体上硅深硅槽隔离结构的制备工艺 | |
CN103137537A (zh) | 一种图形化全耗尽绝缘体上Si/CoSi2衬底材料及其制备方法 | |
JP2000269322A (ja) | 半導体装置及びその製造方法 | |
CN115602729A (zh) | 横向双扩散金属氧化物半导体器件及制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: GLOBALFOUNDRIES SEMICONDUCTORS CO., LTD Free format text: FORMER OWNER: ADVANCED MICRO DEVICES CORPORATION Effective date: 20100721 |
|
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA STATE, THE USA TO: GRAND CAYMAN ISLAND, BRITISH CAYMAN ISLANDS |
|
TR01 | Transfer of patent right |
Effective date of registration: 20100721 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES Inc. Address before: California, USA Patentee before: ADVANCED MICRO DEVICES, Inc. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20210310 Address after: California, USA Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd. Address before: Greater Cayman Islands, British Cayman Islands Patentee before: GLOBALFOUNDRIES Inc. |
|
CX01 | Expiry of patent term |
Granted publication date: 20070822 |
|
CX01 | Expiry of patent term |