CN1388574A - Manufacture of planar display - Google Patents
Manufacture of planar display Download PDFInfo
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- CN1388574A CN1388574A CN 01120811 CN01120811A CN1388574A CN 1388574 A CN1388574 A CN 1388574A CN 01120811 CN01120811 CN 01120811 CN 01120811 A CN01120811 A CN 01120811A CN 1388574 A CN1388574 A CN 1388574A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 165
- 229920002120 photoresistant polymer Polymers 0.000 claims description 78
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- 239000004065 semiconductor Substances 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 31
- 239000011241 protective layer Substances 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 230000004888 barrier function Effects 0.000 claims description 23
- 239000010408 film Substances 0.000 claims description 21
- 239000010409 thin film Substances 0.000 claims description 9
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 8
- 230000003287 optical effect Effects 0.000 description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 239000000463 material Substances 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000012295 chemical reaction liquid Substances 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
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Abstract
The manufacture process of film transistor planar display includes four photoetching steps and one back exposure step to form the film transistor for planar display. The steps include the first photoetching step to form the grid, the second photoetching step to form the source and the drain electrodes, the back exposure and etching step to form a island-like structure, the third photoetching step to form one protecting layer and the final fourth photoetching step to form one pixel electrode.
Description
The present invention relates to a kind of film transistor plane indicator and manufacture method thereof, particularly relate to by back-exposure and reduce the LCD that subsequent process steps formed.
Generally speaking, existing active-matrix LCD (AMLCD) comprises a plurality of pixel electrodes (pixel electrode) and relevant switch module (switching device), for example thin-film transistor of arranging with array (TFT).Define a plurality of pixel regions by interconnected gate line (gate line) and data line (data line).Each pixel region comprises a pixel electrode, and is electrically connected with switch module.In addition, more comprise a storage capacitors (storage capacitor) in each pixel region.
The technology of thin-film transistor comprises the following steps in the existing LCD.At first, shown in Figure 1A, on one transparent (transparent) substrate 40, form one first metallic film; Then, use one first optical mask pattern, on above-mentioned metallic film, form the grid metal lines 42 of set pattern by a photoetching technology.Then, shown in Figure 1B, on substrate 40, form an insulating barrier 44a.Then, go up formation semi-conductor layer (amorphous silicon) 44b in insulating barrier 44a.Then, go up formation one n type doped silicon layer 44c in semiconductor layer 44b.Then, go up formation one conductive layer 46 in n type doped silicon layer 44c.On conductive layer 46, more form a photoresist (photoresist) layer 48.Then, shown in Fig. 1 C, by one second optical mask pattern (not shown) and the photoetching technology is exposed and etching comes define pattern.When rayed during in second optical mask pattern, with reference to figure 1C, this step utilizes part photoresist layer 48a above grid metal lines 42, with semiconductor layer 44b, doped silicon layer 44c, form the island structure 52 of a set pattern with conductive layer 46.Then, shown in Fig. 1 D, utilize exposure of one the 3rd optical mask pattern and etching by the photoetching technology, remove the conductive layer 46 and the doped silicon layer 44c that are positioned at grid metal lines 42 tops, forming a channel (channel) 53, and in channel 53 both sides definition forms a drain electrode 54 and one source pole electrode 56.Then, form a protective film and one second photoresist layer.Shown in Fig. 1 E, utilize one the 4th photomask to expose and etching by the photoetching technology, form a protective layer 58.Protective layer 58 covers source electrode 56, drain electrode 54, semiconductor layer 44b and insulating barrier 44a, has more a plurality of opening 58a, 58b on the protective layer 58, and wherein a drain electrode opening 58a is positioned on the drain electrode 54, and one source pole opening 58b is positioned on the source electrode 56.At last, shown in Fig. 1 F, utilize one the 5th photomask to expose and etching by the photoetching technology, forming a pixel electrode, and pixel electrode comprises a drain electrode pixel electrode 62 and an one source pole pixel electrode 64.Drain electrode pixel electrode 62 contacts with drain electrode 54 by drain electrode opening 58a, and source electrode pixel electrode 64 contacts with source electrode 56 by source electrode opening 58b.
Though existing technology can be produced high-quality AMLCD; Yet, in the transistorized step of process film, need be through five times photoetching step.Use photomask and etching reaction liquid if can reduce, can simplify processing step and form high-quality AMLCD simultaneously, this becomes one of emphasis that improves technology.
In view of this, a purpose of the present invention is to provide a kind of manufacture method of film transistor plane indicator, and its making step is described below.At first, with one first photomask, on a substrate, form one and have the grid metal lines of set pattern; Then, on substrate and grid metal lines, deposit an insulating barrier, semi-conductor layer, a doped silicon layer and a signal metal layer successively.Then,, form a drain electrode and one source pole electrode, and be defined as a channel between drain electrode and the source electrode with one second photomask.On said structure, form a photoresist layer, the photoresist layer is exposed, remove the photoresist layer that is subjected to rayed again by the bottom of substrate.Then, be shielding with the photoresist layer that retains, remove the semiconductor layer that the photoresist layer that do not retained covers, so that form an island structure that comprises semiconductor layer, doped silicon layer, drain electrode and source electrode.Then; remove the photoresist layer that retains; and on insulating barrier, drain electrode, source electrode and semiconductor layer, form a protective layer; utilize one the 3rd photomask on protective layer, to form at least one first opening and one second opening; and first opening is positioned at the drain electrode top, and second opening is positioned at the source electrode top.At last; on protective layer, more form a pixel electrode with one the 4th optical mask pattern; it comprises a drain electrode pixel electrode and an one source pole pixel electrode, and the drain electrode pixel electrode utilizes first opening to contact with drain electrode, and the source electrode pixel electrode utilizes second opening to contact with source electrode.
Another object of the present invention is to provide a kind of manufacture method of film transistor plane indicator, this display is formed on the substrate, and substrate comprises a transistor area and a viewing area at least, and its processing step is summarized as follows.At first, utilize one first optical mask pattern, formation has the grid metal lines of a set pattern in the transistor area of substrate, then, forms an insulating barrier, semi-conductor layer, a doped silicon layer and a signal metal layer successively on grid metal lines.With one second optical mask pattern, definition forms a drain electrode and one source pole electrode, and is defined as a channel between drain electrode and the source electrode.Then, on said structure, form a photoresist layer, and expose to the photoresist layer in the bottom from substrate, remove and be subjected to light-struck photoresist layer, be shielding with the photoresist layer that retains again, remove the semiconductor layer of the photoresist layer covering that is not retained, comprise one of semiconductor layer, doped silicon layer, drain electrode and source electrode island structure so that form one.Then, remove residual photoresist layer after, form the pixel electrode that comprises drain electrode pixel electrode and source electrode pixel electrode with one the 3rd optical mask pattern definition, the drain electrode pixel electrode covers drain electrode, and source electrode pixel electrode covering source electrode.At last, form a protective layer, and protective layer covers the insulating barrier in drain electrode pixel electrode, source electrode pixel electrode and the channel with the definition of one the 4th optical mask pattern.
The invention is characterized in and use four photoetching steps and a back-exposure step to form the thin-film transistor that is applied in the flat-panel screens; wherein utilize a photoetching step to form grid metal lines; utilize a photoetching step to form source electrode and drain electrode; after the substrate back exposure removes the part semiconductor layer; utilize a photoetching step to form protective layer, and utilize a photoetching step to form pixel electrode again.
Engage accompanying drawing below and describe the preferred embodiments of the present invention.In the accompanying drawing:
Figure 1A to Fig. 1 F shows the shop drawings of existing thin-film transistor;
Fig. 2 A to Fig. 2 L shows the shop drawings of the first embodiment of the present invention;
Fig. 3 A to Fig. 3 L shows the shop drawings of the second embodiment of the present invention.
Symbol description:
10～substrate; 11～the first photoresist layers;
12～metallic film; 13～grid metal lines;
14～insulating barrier; 16～semiconductor layer;
18～doped silicon layer; 20～signal metal layer;
21～the second photoresist layers; 22～drain electrode;
23,23a～the 3rd photoresist layer; 24～source electrode;
25～the 4th photoresist layers; 26～protective layer;
28a～drain electrode opening; 28b～source electrode opening;
30～indium tin oxide films; 31～the 5th photoresist layers;
32～drain electrode pixel electrode; 34～source electrode pixel electrode;
36～channel; 40～substrate;
42～grid metal lines; 44a～insulating barrier;
44b～semiconductor layer; 44c～n type doped silicon layer;
46～conductive layer; 48,48a～photoresist layer;
52～island structure; 53～channel;
54～drain electrode; 56～source electrode;
58～protective layer; 58a～drain electrode opening;
58b～source electrode opening; 62～drain electrode pixel electrode;
64～source electrode pixel electrode
First embodiment
Fig. 2 A to Fig. 2 L shows the flow chart of the first embodiment of the present invention.
At first, shown in Fig. 2 A, on a transparency carrier 10, form a metallic film 12 and one first photoresist layer 11.Then, by the photoetching technology, utilize one first optical mask pattern to 11 exposure of the first photoresist layer.Then, with reference to figure 2B, remove the grid metal lines 13 that the first photoresist layer 11 and part metals film 12 form set pattern.
On substrate 10 and grid metal lines 13, more form an insulating barrier 14, for example an amorphous silicon nitride layer.Then, with reference to figure 2C, form semi-conductor layer 16, a doped silicon layer 18 and a signal metal layer 20 on amorphous silicon nitride layer 14 successively, wherein semiconductor layer 16 can amorphous silicon be that made and doped silicon layer 18 can n type amorphous silicon be made.
Shown in Fig. 2 D, on signal metal layer 20, form one second photoresist layer 21.Then, by the photoetching technology, utilize one second optical mask pattern to 21 exposure of the second photoresist layer.Then,, remove the signal metal layer 20 and doped silicon layer 18 of part, to form a drain electrode 22 and one source pole electrode 24 with reference to figure 2E.In addition, be defined as a channel 36 between above-mentioned drain electrode 22 and the source electrode 24.
Shown in Fig. 2 F, on semiconductor layer 16, drain electrode 22 and source electrode 24, form the 3rd photoresist layer 23.Then, the base plate bottom of self-induced transparency is to 23 exposure of the 3rd photoresist layer, because grid metal lines 13, drain electrode 22 become the light shielding with source electrode 24 for being difficult for light-transmitting materials, make the 3rd photoresist layer 23 that is positioned at grid metal lines 13, drain electrode 22 and source electrode 24 tops can not be subjected to irradiate light.Afterwards, remove and be subjected to light-struck photoresist layer, be shielding with the photoresist layer 23a that retains again, remove the semiconductor layer 16 of the photoresist layer covering that is not retained, just can form an island structure that comprises semiconductor layer 16, doped silicon layer 18, drain electrode 22 and source electrode 24, shown in Fig. 2 G.Then, shown in Fig. 2 H, remove the 3rd photoresist layer 23a that retains.
With reference to figure 2I, form a protective layer 26 on the semiconductor layer 16 in insulating barrier 14, drain electrode 22, source electrode 24 and channel 36.On protective layer 26, more form one the 4th photoresist layer 25.Then,, utilize one the 3rd optical mask pattern that the 4th photoresist layer is exposed, after the development etching, in protective layer 26, form a plurality of openings, shown in Fig. 2 J by the photoetching technology.Wherein, a drain electrode opening 28a is positioned at drain electrode 22 tops, and one source pole opening 28b is positioned at source electrode 24 tops.
On protective layer 26, form an indium tin oxide films 30.Then, with reference to figure 2K, on indium tin oxide films 30, form one the 5th photoresist layer 31.Then,, utilize one the 4th optical mask pattern that the 5th photoresist layer is exposed, indium tin oxide films 30 definition are formed a drain electrode pixel electrode 32 and one source pole pixel electrode 34 by the photoetching technology.Channel 36 is source electrode pixel electrodes 34 and drain electrode pixel electrode 32 at interval, and drain electrode pixel electrode 32 contacts with drain electrode 22 by drain electrode opening 28a, and source electrode pixel electrode 34 contacts with source electrode 24 by source electrode opening 28b, shown in Fig. 2 L.
Second embodiment
Fig. 3 A to Fig. 3 L shows the shop drawings of the second embodiment of the present invention.
On substrate 10 and grid metal lines 13, form an insulating barrier 14.Then, with reference to figure 3C, form semi-conductor layer 16, a doped silicon layer 18 and a signal metal layer 20 successively on insulating barrier 14, wherein the material of semiconductor layer 16 can be an amorphous silicon, and doped silicon layer 18 can n type amorphous silicon be a made.
Shown in Fig. 3 D, on signal metal layer 20, form one second photoresist layer 21.Then, by the photoetching technology, utilize one second optical mask pattern to 21 exposure of the second photoresist layer.Then, with reference to figure 3E, remove the signal metal layer 20 and doped silicon layer 18 of part, forming a drain electrode 22 and one source pole electrode 24, and drain electrode 22 defines a channel 36 with 24 of source electrodes.
On semiconductor layer 16, drain electrode 22 and source electrode 24, form one the 3rd photoresist layer 23.Shown in Fig. 3 F, expose in substrate 10 bottoms of self-induced transparency.Is made up of light tight material and becomes shielding owing to grid metal lines 13, drain electrode 22 and source electrode 24, feasible the 3rd photoresist layer 23a that is positioned at grid metal lines 13, drain electrode 22 and source electrode 24 tops can not be subjected to rayed.Then, shown in Fig. 3 G, remove by light-struck the 3rd photoresist layer, and retain part the 3rd photoresist layer 23a.Then, be shielding with the 3rd photoresist layer 23a that retains, remove the part semiconductor layer 16 that is not covered, to form an island structure by the 3rd photoresist layer 23a.Then, shown in Fig. 3 H, remove the 3rd photoresist layer 23a that retains.
On insulating barrier 14, and comprise and form an indium tin oxide films 30 on the island structure of drain electrode 22, source electrode 24, doped silicon layer and semiconductor layer 16.Then, with reference to figure 3I, on indium tin oxide films layer 30, form one the 4th photoresist layer 25.Then, by the photoetching technology, utilize one the 3rd optical mask pattern to 25 exposure of the 4th photoresist layer, after photoetching technology, form a drain electrode pixel electrode 32 and one source pole pixel electrode 34, drain electrode pixel electrode 32 contacts with drain electrode 22 and insulating barrier 14, and source electrode pixel electrode 34 contacts with source electrode 24 and insulating barrier 14, shown in Fig. 3 J.In addition, indium tin oxide films layer 30 more forms a viewing area pixel electrode (not icon) in the viewing area of substrate 10.
On drain electrode pixel electrode 32, source electrode pixel electrode 34, drain electrode 22, source electrode 24 and channel 36 inner semiconductor layers 16, more form a protective layer 26.Then; with reference to figure 3K; on protective layer 26, form one the 5th photoresist layer 31; by the photoetching technology; utilize one the 4th optical mask pattern to 31 exposure of the 5th photoresist layer; and with the pattern of etch process definition back protective layer 26; make drain electrode pixel electrode 32, source electrode pixel electrode 34, drain electrode 22, source electrode 24, the semiconductor layer 16 and insulating barrier 14 in protective layer 26 covering transistor districts; shown in Fig. 3 L, and protective layer does not cover the viewing area pixel electrode (not icon) of viewing area.
Though the present invention discloses as above in conjunction with an embodiment; yet be not in order to limit the present invention; those skilled in the art can make various changes and retouching not breaking away from the spirit and scope of the present invention, so protection scope of the present invention should be by the accompanying Claim person of defining.
Claims (11)
1. the manufacture method of a film transistor plane indicator, aforementioned thin-film transistor is formed on the substrate, and this method comprises the following steps:
(a) on aforesaid substrate, form a grid metal lines;
(b) on aforesaid substrate and above-mentioned grid metal lines, form an insulating barrier, semi-conductor layer, a doped silicon layer and a signal metal layer successively;
(c) pattern of definition above-mentioned doped silicon layer and above-mentioned signal metal layer forming a drain electrode and one source pole electrode, and is defined as a channel between above-mentioned drain electrode and the source electrode;
(d) on above-mentioned semiconductor layer, drain electrode, source electrode, with channel in form a photoresist layer;
(e) from the aforesaid substrate bottom above-mentioned photoresist layer is exposed, remove and be subjected to light-struck photoresist layer, be shielding with the photoresist layer that retains again, remove not the semiconductor layer that is covered by the above-mentioned photoresist layer that retains, with form one comprise above-mentioned semiconductor layer, doped silicon layer, drain electrode, with an island structure of source electrode;
(f) remove above-mentioned photoresist layer, and on above-mentioned insulating barrier, drain electrode, source electrode and semiconductor layer, form a protective layer, above-mentioned protective layer has at least one first opening and one second opening, the wherein above-mentioned first opening position is above above-mentioned drain electrode, and the second opening position is above above-mentioned source electrode; And
(g) more form a drain electrode pixel electrode and an one source pole pixel electrode on above-mentioned protective layer, above-mentioned drain electrode pixel electrode contacts with above-mentioned drain electrode by above-mentioned first opening, and above-mentioned source electrode pixel electrode contacts with above-mentioned source electrode by above-mentioned second opening.
2. manufacture of planar display as claimed in claim 1 wherein in step (a), on aforesaid substrate, forms a metal level and one first photoresist layer earlier, then forms above-mentioned grid metal lines by one first photoetching step.
3. manufacture of planar display as claimed in claim 1 wherein in step (c), after forming one second photoresist layer on the above-mentioned doped silicon layer, forms above-mentioned drain electrode and source electrode by one second photoetching step.
4. manufacture of planar display as claimed in claim 1; wherein the above-mentioned photoresist layer in step (d) is one the 3rd photoresist layer; and in step (f); form a protective layer and one the 4th photoresist layer on the semiconductor layer in above-mentioned insulating barrier, drain electrode, source electrode and above-mentioned channel successively, form above-mentioned protective layer by one the 3rd photoetching step afterwards with above-mentioned first and second opening.
5. as method for fabricating thin film transistor that claim 1 reached; wherein in step (g); on above-mentioned protective layer, form an indium tin oxide layer and one the 5th photoresist layer successively, form above-mentioned drain electrode pixel electrode and above-mentioned source electrode pixel electrode by one the 4th photoetching step.
6. method for fabricating thin film transistor as claimed in claim 1; comprising utilizing the photoetching step four times; comprising one for the first time the photoetching step in order to form above-mentioned grid metal lines; one for the second time the photoetching step in order to form above-mentioned drain electrode and above-mentioned source electrode; one for the third time the gold-tinted step have the above-mentioned protective layer of above-mentioned opening in order to formation, with one the 4th photoetching step in order to form above-mentioned drain electrode pixel electrode and above-mentioned source electrode pixel electrode.
7. the manufacture method of a film transistor plane indicator, aforementioned thin-film transistor is formed on the substrate, and aforesaid substrate comprises a transistor area and a viewing area at least, and said method comprises the following steps:
(a) in the transistor area of aforesaid substrate, form a grid metal lines;
(b) on above-mentioned grid metal lines, form an insulating barrier, semi-conductor layer, a doped silicon layer and a signal metal layer successively;
(c) pattern of definition above-mentioned doped silicon layer and above-mentioned signal metal layer forming a drain electrode and one source pole electrode, and is defined as a channel between above-mentioned drain electrode and the source electrode;
(d) on above-mentioned semiconductor layer, drain electrode, source electrode, with channel in form a photoresist layer;
(e) from the aforesaid substrate bottom above-mentioned photoresist layer is exposed, remove and be subjected to light-struck photoresist layer, be shielding with the photoresist layer that retains again, remove not the semiconductor layer that is covered by the above-mentioned photoresist layer that retains, with form one comprise above-mentioned semiconductor layer, doped silicon layer, drain electrode, with an island structure of source electrode;
(f) remove above-mentioned photoresist layer, and on above-mentioned insulating barrier, drain electrode and source electrode, form a drain electrode pixel electrode and an one source pole pixel electrode, above-mentioned drain electrode pixel electrode covers above-mentioned drain electrode, and above-mentioned source electrode pixel electrode covers above-mentioned source electrode; And
(g) form a protective layer, cover the above-mentioned insulating barrier in above-mentioned drain electrode pixel electrode, source electrode pixel electrode and the above-mentioned channel.
8. method for fabricating thin film transistor as claimed in claim 7, wherein in step (a) on aforesaid substrate, earlier form a metal level and one first photoresist layer successively, form above-mentioned grid metal lines by one first photoetching step afterwards.
9. manufacture of planar display as claimed in claim 7, wherein be included in the above-mentioned steps (c) on the above-mentioned doped silicon layer form one second photoresist layer after, form above-mentioned drain electrode and above-mentioned source electrode by one second photoetching step.
10. manufacture of planar display as claimed in claim 7, wherein the above-mentioned photoresist layer of above-mentioned steps (d) is one the 3rd photoresist layer, and in above-mentioned steps (f), be included in and form an indium tin oxide layer and one the 4th photoresist layer on the aforesaid substrate, on above-mentioned drain electrode and source electrode, form above-mentioned drain electrode pixel electrode and source electrode pixel electrode by one the 3rd photoetching step, and in above-mentioned viewing area, form a viewing area pixel electrode.
11. manufacture of planar display as claimed in claim 10; wherein in the above-mentioned steps (g); be included in and form one silica layer and one the 5th photoresist layer on the aforesaid substrate successively; in above-mentioned drain electrode pixel electrode, source electrode pixel electrode and channel, form a protective layer by one the 4th photoetching step, and above-mentioned viewing area pixel electrode is come out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011208112A CN1154174C (en) | 2001-05-30 | 2001-05-30 | Manufacture of planar display |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011208112A CN1154174C (en) | 2001-05-30 | 2001-05-30 | Manufacture of planar display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1388574A true CN1388574A (en) | 2003-01-01 |
| CN1154174C CN1154174C (en) | 2004-06-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011208112A Expired - Lifetime CN1154174C (en) | 2001-05-30 | 2001-05-30 | Manufacture of planar display |
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| US9806110B2 (en) | 2011-05-30 | 2017-10-31 | Boe Technology Group Co., Ltd. | Pixel structure, LCD panel, and manufacturing method thereof |
| CN108646487A (en) * | 2018-05-15 | 2018-10-12 | 深圳市华星光电技术有限公司 | The production method and FFS type array substrates of FFS type array substrates |
| CN108646487B (en) * | 2018-05-15 | 2020-12-25 | Tcl华星光电技术有限公司 | FFS (fringe field switching) type array substrate and manufacturing method thereof |
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