CN1398423A - 一种成型半导体结构的方法 - Google Patents

一种成型半导体结构的方法 Download PDF

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CN1398423A
CN1398423A CN01804762A CN01804762A CN1398423A CN 1398423 A CN1398423 A CN 1398423A CN 01804762 A CN01804762 A CN 01804762A CN 01804762 A CN01804762 A CN 01804762A CN 1398423 A CN1398423 A CN 1398423A
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layer
monocrystalline
epitaxial growth
compound semiconductor
oxide layer
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J·兰达尼
R·德鲁帕德
L·L·希尔特
K·W·爱森贝瑟
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Motorola Solutions Inc
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Motorola Inc
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Abstract

通过在硅晶片(22)上首先生长缓冲适应层(24)可在大的硅晶片上生长高质量的化合物半导体材料外延层。所述缓冲适应层是通过一个硅氧化物非晶态中间层(28)与所述硅晶片间隔开的单晶氧化物层。所述非晶态中间层优选通过使氧经所述氧化物适应层扩散而形成并可生长出高质量的单晶氧化物缓冲适应层。该方法还可包括模板层(28，30)和半导体缓冲层(32)的形成。其特别适用于化合物半导体与Si SMOS设备的集成。

Description

一种成型半导体结构的方法
发明领域
本发明总体上涉及成型半导体结构的方法，更具体地说，涉及成型化合物半导体的方法以及包括单晶化合物材料的半导体结构的用途。
发明背景
由于廉价、高质量单晶硅基片的易得性，大多数半导体分立设备和集成电路至少部分是由硅来制造。其它的半导体材料如所谓的化合物半导体材料，具有包括比硅更宽的带隙和/或更高的迁移率或直接带隙(direct bandgap)的物理属性，使得这些材料对于某些类型的半导体设备有利。不利的是，化合物半导体材料通常比硅贵得多，且不能如硅那样呈大晶片来得到。最易得到的化合物半导体材料砷化镓(GaAs)可得到的晶片的最大直径仅约为150mm。相反，硅晶片可高达约300mm，且可普通地以200mm来得到。150mm的砷化镓比它们的硅对应物贵许多倍。其它化合物半导体材料晶片更不易得到，并比GaAs还要贵。
由于化合物半导体材料的理想的特性，并由于其通常的高成本和大块形态的低易得性，许多年来一直试图在异质基片上产生化合物半导体材料薄膜。但为获得最佳的化合物半导体材料性能，需要高结晶质量的单晶薄膜。例如，已偿试过在锗、硅、和各种绝缘体上产生单晶化合物半导体材料层。这些尝试一般都是不成功的，因为在基质晶体与生长晶体之间的晶格失配使得所得到的薄膜化合物半导体材料的结晶质量低。
如果能够以低的成本得到高质量的大面积薄膜化合物半导体材料，则可有利地以该薄膜来制造各种半导体设备，这样的制造成本低于在化合物半导体材料大晶片(bulk wafer)上制造这种设备或以在化合物半导体材料大晶片上的这种材料的外延膜来制造这种设备的成本。另外，如可实现在如硅晶片上产生高质量的单晶化合物半导体材料薄膜，则可利用硅与化合物半导体材料两者的最佳性能来获得集成设备结构。
对应的，现在需求在另一种单晶材料上提供高质量的单晶化合物半导体膜的制造半导体结构的方法。
附图简要说明
本发明以实例方式进行说明，并且不局限于所附附图，在附图中相同的标号表示相似的元件，其中：
图1、2、4、5简要图示了本发明各种实施方案中设备结构的横断面图；
图3图示了最大可得到的膜厚度同基质晶体与生长晶体覆盖层之间的晶格失配之间的关系；
图6图示了通信装置的一部分的简图；
图7-11图示了包括化合物半导体部分、双极部分、和MOS部分的一部分集成电路的横断面图；和
图12-18图示了包括半导体层和MOS晶体管的另一种集成电路的一部分的横断面图。
熟练技术人员可理解，为简单和清楚起见在所述图中的元件未按比例来进行图示。例如，在图中的一些元件的尺寸可相对于其它元件进行了放大以有助于增进对本发明实施方案的理解。
附图详细说明
图1简要图示了本发明实施方案的半导体结构20的一部分的横断面图。半导体结构20包括单晶基片22，包含单晶材料的缓冲适应层24、和单晶化合物半导体材料层26。在本文中，术语“单晶”具有在半导体工业中通用的意义。该术语是指单晶或基本为单晶的材料，包括具有较少量缺陷的那些材料，所述缺陷如在硅或锗或硅与锗的混合物的基片中和在半导体工业中常见的这种材料的外延层中常见的位错等。
按照本发明的一种实施方案，所述结构20还包括位于基片22和缓冲适应层24之间的非晶态中间层28。结构20还可包括在缓冲适应层与化合物半导体层26之间的模板层30。如以下将更完全解释的，所述模板层有助于引发在缓冲适应层上化合物半导体层的生长。所述非晶态中间层有助于消除在缓冲适应层中的应变，并此有助于高结晶质量的缓冲适应层的生长。
按照本发明的一种实施方案，基片22是单晶半导体晶片，优选是大直径的。所述晶片可是元素周期表IV族的材料，优选IVA族的材料。IV族材料的实例包括硅、锗、硅与锗的混合物、硅与碳的混合物、硅、锗与碳的混合物等。优选基片22是含有硅或锗的晶片，最优选是在半导体工业中使用的高质量单晶硅晶片。缓冲适应层24优选是在底层基片上外延生长的单晶氧化物或氮化物材料。按照本发明的一种实施方案，在层24的生长过程中，通过基片22的氧化在基片22与生长的缓冲适应层之间的界面处在基片22上生长非晶态中间层28。所述非晶态中间层用来消除由于基片与缓冲层晶格常数的差别在单晶缓冲适应层中可能出现的应变。在这里所使用的晶格常数是指在表面平面上测量的晶胞的原子之间的距离。如果这种应变不通过非晶态中间层来消除，则所述应变可在缓冲适应层的晶体结构中引起缺陷。在缓冲适应层晶体结构中的缺陷又会使得难以在单晶化合物半导体层26中获得高质量的结晶结构。
缓冲适应层24优选是单晶氧化物或氮化物材料，所述材料的选择使得其与底层的基片并与覆盖层化合物半导体材料具有结晶相容性。例如，所述材料可为一种氧化物或氮化物，所述氧化物或氮化物具有与基片并与随后施加的半导体材料相匹配的晶格结构。适用作为缓冲适应层的材料包括金属氧化物如碱土金属钛酸盐、碱土金属锆酸盐、碱土金属铪酸盐、碱土金属钽酸盐、碱土金属钌酸盐、碱土金属铌酸盐、碱土金属钒酸盐、碱土金属锡基钙钛矿、铝酸镧、镧钪氧化物和氧化钆。另外，各种氮化物如氮化镓、氮化铝、和氮化硼也可用作缓冲适应层。大多数这些材料是绝缘体，尽管例如钌酸锶是导体。通常，这些材料是金属氧化物或金属氮化物，更特别是，这些金属氧化物或金属氮化物通常包括至少两种不同的金属元素。在某些具体应用中，所述金属氧化物或金属氮化物可包括三种或更多种不同金属元素。
非晶态中间层28优选是由基片22表面进行氧化所形成的氧化物，更优选是由氧化硅组成。层28的厚度足以消除基片22与缓冲适应层24的晶格常数不匹配所致的应变。通常，层28的厚度范围为约0.5-5nm。
按具体半导体结构的需求，层26的化合物半导体材料可选自任何IIIA和VA族元素(III-V半导体化合物)、混合III-V化合物、II(A或B)族和VIA族元素(II-VI半导体化合物)、和混合II-VI化合物。实例包括砷化镓(GaAs)、镓铟砷化物(GaInAs)、镓铝砷化物(GaAlAs)、磷化铟(InP)、硫化镉(CdS)、镉汞碲化物(CdHgTe)、硒化锌(ZnSe)、锌硫硒化物(ZnSSe)、等。适用的模板材料在选择的部位上与缓冲适应层24表面化学连接并提供随后化合物半导体层26外延生长的成核部位。适用于作为模板30的材料在以下进行讨论。
图2图示了本发明另一种实施方案的半导体结构40的一部分的横断面图。结构40与前述半导体结构20相似，不同之处在于在缓冲适应层24与单晶化合物半导体材料层26之间有附加的缓冲层32。具体来说，所述附加缓冲层们于模板层30和化合物半导体材料覆盖层之间。由半导体或化合物半导体材料形成的所述附加缓冲层用来当缓冲适应层的晶格常数与覆盖化合物半导体材料层不能适当地匹配时提供一种晶格补偿。
如下非限制定性说明性实施例说明了按照本发明各种供选择的实施方案中结构20和结构40中适用的材料的各种组合。这些实施例只是说明性的，不是要将本发明限定于这些说明性实施例。
实施例1
按照本发明的一种实施方案，单晶基片22是沿(100)晶向取向的硅基片。所述硅基片例如可为在制备直径为约200-300mm的互补金属氧化物半导体(CMOS)集成电路中所通用的硅基片。按照本发明的这种实施方案，缓冲适应层24是SrzBa1-zTiO3单晶层，其中Z范围为0至1，且非晶态中间层是在硅基片与缓冲适应层之间的界面上形成的硅氧化物层(SiOX)。Z的数值选择为获得与随后形成的层26的对应晶格常数紧密匹配的一或多种晶格常数。缓冲适应层可具有约2至约100纳米(nm)的厚度，优选厚度为约10nm。通常，希望缓冲适应层的厚度足以使化合物半导体层与基片相互隔离以得到所需的电和光学性能。大于100nm厚度的层在不必要地增加了成本的同时通常不能提供附加的益处；但如果需要可制造较厚的层。硅氧化物非晶态中间层的厚度可为约0.5-5nm，优选厚度为约1.5-2.5nm。
按照本发明的这种实施方案，化合物半导体材料层26是镓砷化物(GaAs)层或铝镓砷化物(AlGaAs)层，其厚度为约1nm至约100微米(μm)，优选厚度为约0.5μm至10μm。所述厚度通常取决于所制备的层的应用。为促进镓砷化物或铝镓砷化物在单晶氧化物上的外延生长，通过覆盖氧化物层来形成模板层。所述模板层优选为Ti-As，Sr-O-As，Sr-Ga-O，或Sr-Al-O的1-10单层。作为优选实施例，Ti-As或Sr-Ga-O，的1-2单层已表现出可成功地生长GaAs层。
实施例2
按照本发明的另一实施方案，单晶基片22是上述的硅基片。缓冲适应层是呈立方或斜方相的单晶氧化锶或钡的锆酸盐或铪酸盐，在硅基片与缓冲适应层之间形成有硅氧化物非晶态中间层。所述缓冲适应层的厚度可为约2-100nm，优选为至少5nm，以确保适当的结晶和表面质量，且由单晶SrZrO3，BaZrO3，SrHfO3，BaSnO3或BaHfO3构成。例如，BaZrO3单晶氧化物层可在约为700℃的温度下生长。所得到的结晶氧化物的晶格结构相对于基片硅晶格结构表现出有45度的旋转。
由这些锆酸盐或铪酸盐材料构成的缓冲适应层适用于生长磷化铟(InP)体系的化合物半导体材料。所述化合物半导体材料可例如是厚度为约1.0nm至10μm的磷化铟(InP)或铟镓砷化物(InGaAs)。对这一结构适用的模板是1-10单层的锆-砷(Zr-As)、锆-磷(Zr-P)、铪-砷(Hf-As)、铪-磷(Hf-P)、锶-氧-砷(Sr-O-As)、锶-氧-磷(Sr-O-P)、钡-氧-砷(Ba-O-As)、铟-锶-氧(In-Sr-O)、或钡-氧-磷(Ba-O-P)，优选为1-2单层的这些材料中的一种。举例来说，对于锆酸钡缓冲适应层来说，所述表面终端为1-2单层的锆，随后沉积1-2单层的砷以形成Zr-As模板。然后在所述模板层上生长磷化铟体系的化合物半导体材料单晶层。所得到的化合物半导体材料晶格结构相对于缓冲适应层晶格结构表现出有45度的旋转，且与(100)InP不匹配的晶格少于2.5％，优选少于约1.0％。
实施例3
按照本发明的另一实施方案，提供了适用于在硅基片上生长II-VI材料外延膜的结构。所述基片优选是上述的硅晶片。适用的缓冲适应层材料是SrxBa1-xTiO3，其中x的范围为0至1，该层厚度为约2-100nm，优选厚度为约5-15nm。所述II-VI化合物半导体材料可例如为锌硒化物(ZnSe)或锌硫硒化物(ZnSSe)。对于这一材料适用的模板包括1-10单层的锌-氧(Zn-O)，随后为1-2单层的过量锌，接着是对表面上的锌进行硒化(selenidation)。模板例如也可为锶-硫(Sr-S)，接着为ZnSeS。
实施例4
本发明的这一实施方案是图2中所示的结构40的实施例。基片22、单晶氧化物层24、和单晶化合物半导体材料层26可与实施例1中所述相似。另外，附加缓冲层32用来减轻由缓冲适应层晶格与单晶半导体材料晶格不匹配而可能产生的任何应变。缓冲层32可为镓砷磷化物(GaAsxP1-x)或铟镓磷化物(InyGa1-yP)应变补偿的超晶格。在镓砷的磷化物超晶格(superlattice)中，x的数值范围为0至1，在铟镓磷化物超晶格中，y数值的范围为0至1。视情况而定通过如此变化数值x或y，超晶格从底部至顶部的晶格常数发生改变使得产生被覆盖氧化物层与上覆的化合物半导体材料之间晶格常数匹配。所述超晶格的厚度可为约50-500nm，优选为约200-100nm。这种结构的模板可与在实施例1中所述相同。另外，缓冲层可为单晶锗层，其厚度为1-50nm，优选为约2-20nm。在使用锗缓冲层的情况下，可使用厚度为约一个单层的锗-锶(Ge-Sr)或锗-钛(Ge-Ti)模板层。形成的所述氧化物层覆盖单层的锶或单层的钛而起随后单晶锗沉积的成核部位作用。单层锶或钛提供了第一单层锗可与之连接的成核部位。
实施例5
这一实施例也对在图2中所示结构40中可使用的材料进行说明。基片材料22、缓冲适应层24、单晶化合物半导体材料层26可与在实施例2中的上述那些相同。另外，在缓冲适应层与覆盖单晶化合物半导体材料层之间插有缓冲层32。另一单晶半导体材料的缓冲层可例如是铟镓砷化物(InGaAs)递变层，其中铟的组成在0至约47％之间变化。所述缓冲层的厚度优选为约10-30nm。将缓冲层的组成由GaAs变化为InGaAs用来提供被覆盖单晶氧化物材料与上覆的单晶化合物半导体材料之间的晶格匹配。如果缓冲适应层24与单晶化合物半导体材料层26之间存在不匹配时，这种缓冲层是特别有利的。
再参照图1和2，基片22是单晶基片，例如为单晶硅基片。所述单晶基片的晶体结构的特征在于其晶格常数和晶格取向。以相似的方式，缓冲适应层24也是单晶材料，且其单晶材料的晶格的特征在于晶格常数和晶体取向。缓冲适应层和单晶基片的晶格常数必须紧密配合，或者必须使得当一种结晶取向相对于另一种结晶取向进行旋转时，实现晶格常数的基本匹配。在本文中，术语“基本相等”和“基本匹配”意义是晶格常数之间有足够的相似性使得可在被覆盖层上生长出高质量的结晶层。
图3图示了高结晶质量生长晶体层的可实现的厚度与基质晶体和生长晶体之间晶格常数失配之间的关系。曲线42图示了高结晶质量材料的边界。曲线42右侧面积代表趋于为多晶态的层。在不存在晶格失配的情况下，理论上可在基质晶体上生长出无限厚的高质量的外延层。随着晶格常数失配的增加，高结晶质量层可实现的厚度快速下降。作为一个参照点，例如，如果基质晶体与生长层的晶格常数失配超过约2％，则不可能实现超过约20nm的单晶外延层。
按照本发明的一种实施方案，基片22是(100)或(111)取向的单晶硅晶片，缓冲适应层24是锶钡钛酸盐层。通过将钛酸盐材料的晶体取向相对于硅基片晶片的晶体取向旋转45°，可实现这两种材料的晶格常数的基本匹配。在结构中包含非晶态中间层24，在本实施例中其为氧化硅层，可用来减轻基质硅晶片与生长钛酸盐层晶格常数的任何失配所可能导致的在钛酸盐单晶层中的应变。结果，按照本发明的一种实施方案，实现了高质量厚的单晶钛酸盐层。
仍参照图1和2，层26是外延生长的单晶化合物半导体材料，该结晶材料的特征也在于晶体晶格常数晶体取向。为在这一外延生长层中实现高结晶质量，所述缓冲适应层必须是高结晶质量的。另外，为在层26中实现高结晶质量，需要基质晶体(在这种情况下为单晶缓冲层适应层)与生长晶体之间晶体晶格常数的基本匹配。通过恰当选择的材料，由生长晶体的晶体取向相对于基质晶体取向的旋转实现了晶格常数的基本匹配。如果生长晶体是砷化镓、铝镓的砷化物、锌的硒化物、或锌硫硒化物，并且所述缓冲适应层是单晶SrxBa1-xTiO3，实现了所述两种材料的晶体晶格常数的基本匹配，其中生长层晶体取向相对于基质单晶氧化物的取向旋转45°。相似的，如果基质材料是锶或钡的锆酸盐或锶或钡的铪酸盐或钡锡氧化物且化合物半导体层是铟磷化物或镓铟砷化物或铝铟砷化物，通过生长晶体层的取向相对于基质氧化物晶体旋转45°可实现晶体晶格常数的基本匹配。在某些情况下，可使用基质氧化物与生长化合物半导体层之间的晶态半导体缓冲层来减轻晶格常数的小的差别可能导致的在生长单晶化合物半导体化合物层中的应变。从而可实现在生长单晶化合物半导体层中更佳的结晶质量。
如下实施例说明了按照本发明的一种实施方案的制造如图1和2中所示结构的半导体结构的方法。所述方法的起始步骤是提供包括硅或锗的单晶半导体基片。按照本发明的优选实施方案，所述半导体基片是具有(100)取向的硅晶片。所述基片优选在轴上取向或至多偏离轴约0.5°。至少一部分所述半导体基片具有裸露表面，但如下所述，基片的其它部分可包覆有其它结构。在本文中术语“裸露”的意义是，在该部分基片中的表面已进行过清洗来除去任何氧化物、污染物或其它外来材料。如众所周知，裸露的硅是高反应活性的，易于形成天然氧化物。术语“裸露”意欲包括这类天然氧化物。薄氧化硅也可是在半导体基片上有意生长的，但这种生长的氧化物不是本发明方法必要的。为覆盖单晶基片来外延生长单晶氧化物层，必须首先除去天然氧化物层来暴露出被覆盖基片的晶体结构。优选进行如下的分子束外延(MBE)方法。可在MBE装置中首先热沉积薄层锶来除去天然氧化物。然后加热所述基片至约750℃来使所述锶与硅天然氧化物层进行反应。所述锶用来减少硅氧化物来得到无硅氧化物的表面。表现出规则的2×1结构的所得到的表面，包括锶、氧、和硅。所述规则的2×1结构构成规则生长单晶氧化物覆盖层的模板。所述模板提供了对覆盖层晶体生长起成核作用所必需的化学和物理性能。
按照本发明的另一实施方案，所述天然硅氧化物可进行转化，且所述基片表面可为生长单晶氧化物层而按下述来进行制备，即，通过MBE在低温下在所述基片上沉积氧化锶，随后将所述结构加热至约750℃的温度。在这一温度下，所述氧化锶与天然硅氧化物之间发生固态反应，使得天然硅氧化物被还原，得到基片表面保留有锶、氧、和硅的规则2×1结构。这又形成了随后生长规则单晶氧化物层的模板。
在从基片表面除去硅氧化物之后，按照本发明的一种实施方案，将所述基片冷却到约400-600℃的温度范围，通过分子束外延来在所述模板层上生长钛酸锶层。所述MBE方法的起始步骤是在MBE装置中的遮挡板，使锶、钛和氧源相互接触。锶与钛的比值为约1∶1。氧的分压初始设置在最小值以在约0.3-0.5nm每分钟的生长速率下来生长化学计量的(stochiometric)的钛酸锶。在初始生长钛酸锶后，氧的分压增加到高于初始最小值。氧的过压使得在被覆盖基片与生长的钛酸锶层之间生长了非晶态硅氧化物层。所述硅氧化物层的生长是由如下过程所致，氧穿过生长的钛酸锶层扩散到所述界面，在界面处氧与被覆盖基片表面上的硅进行反应。所述钛酸锶生长为规则单晶，其结晶取向相对于被覆盖基片的规则2×1结晶结构旋转45°。由于硅基片与生长晶体之间晶格常数的微小不匹配可能在钛酸锶层存在的应变在非晶态硅氧化物中间层被减轻。
在钛酸锶层生长至所需厚度后，在所述单晶钛酸锶之上覆盖一模板层，其有助于随后生长外延层所需化合物半导体材料。为随后生长砷化镓层，可在MBE生长的单晶钛酸锶单晶层上覆盖以终止其生长的1-2单层的钛、1-2单层的钛-氧或1-2单层的锶-氧。在形成这种覆盖层之后，沉积砷来形成Ti-As键、Ti-O-As键或Sr-O-As键。任意这些均可形成用于沉积和形成砷化镓单晶层的适宜的模板。在形成所述模板后，引入镓以与砷进行反应从而形成砷化镓。另外，也可在覆盖层上沉积镓来形成Sr-O-Ga键，并引入砷与镓来形成GaAs。
图2中所示结构可通过以上讨论的方法并添加以附加的缓冲层沉积步骤来形成。在沉积单晶化合物半导体层之前形成覆盖模板的缓冲层。如果所述缓冲层是化合物半导体超晶格，这种超晶格可通过例如MBE来沉积在上述模板上。如果所述缓冲层代之以锗，则以上方法变化为用最终的锶或钛层覆盖钛酸锶单晶层，然后沉积锗以与锶或钛进行反应。然后可在这种模板上直接沉积锗缓冲层。
上述方法说明了通过分子束外延法来形成半导体结构的方法，所述结构包括硅基片、单晶钛酸锶缓冲适应层、和单晶砷化镓化合物半导体层。所述方法还可通过化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、增强迁移外延法(MEE)、原子层外延法(ALE)、或类似方法来进行。再有，通过相似的方法，还可生长其它单晶缓冲层适应层如碱土金属钛酸盐、锆酸盐、铪酸盐、钽酸盐、钒酸盐、钌酸盐、和铌酸盐、碱土金属锡基钙钛矿、铝酸镧、镧钪氧化物、和钆氧化物。另外，通过相似的如MBE的方法，还可沉积覆盖单晶氧化物缓冲适应层的其它III-V和II-VI单晶态化合物半导体层。
各种变化的化合物半导体材料和单晶氧化物缓冲适应层均使用适宜的模板来引发化合物半导体层生长。例如，如所述缓冲适应层是碱土金属锆酸盐，则所述氧化物可覆盖以薄层锆。在沉积锆之后，可接着沉积砷或磷以与作为前体的锆进行反应来分别沉积铟镓砷化物、铟铝砷化物、或铟磷化物。相似的，如果所述单晶氧化物缓冲适应层是碱土金属铪酸盐，则所述氧化物层可覆盖以薄层铪。在沉积铪之后，接着中砷或磷来与作为前体的铪进行反应从而分别生长铟镓砷化物、铟铝砷化物、或铟磷化物层。以相似的方式，可在钛酸锶上覆盖一层锶或锶和氧，在钛酸钡上可覆盖一层钡或钡与氧。各种这些沉积之后均可随后进行砷或磷的沉积来与所覆盖的金属进行反应从而形成沉积化合物半导体材料层的模板，所述化合物半导体材料层包括铟镓砷化物、铟铝砷化物、或铟磷化物。
图4图示了本发明另一实施方案的设备结构的横断面图。设备结构50包括单晶半导体基片52，优选单晶硅晶片。单晶半导体基片52包括两个区域，53和54。在区域53形成由虚线56所总体标明的半导体电子元件。电子元件56可以是电阻器、电容器、有源半导体元件如二极管或晶体管或集成电路如CMOS集成电路。例如，半导体电子元件56可为CMOS集成电路，其配置为来执行适宜于硅集成电路的数字信号处理或其它功能。在区域53中的半导体电子元件可由半导体工业中公知并广泛实施的通用的半导体加工来形成。可有一层绝缘材料58如一层二氧化硅或类似物来覆盖半导体电子元件56。
从区域54的表面除去在区域53中加工半导体元件56的过程中已形成或沉积的绝缘材料58和任何其它层来在该区域提供裸露的硅表面。如所公知的，裸露的硅表面是高反应活性的，在所述裸露的表面上可快速形成天然硅氧化物层。在区域54表面的天然氧化物层上沉积一层钡或钡和氧，并与氧化表面进行反应来形成第一模板层(未示出)。按照本发明的一种实施方案，通过分子束外延法来形成覆盖模板层的单晶氧化物层60。在模板层上沉积包括钡、钛和氧的反应物来形成单晶氧化物层。在沉积过程的初期，氧的分压保持为接近与钡和钛完全反应来形成单晶钛酸钡层60所需的最小值。然后增加氧的分压来提供氧的超压，并使氧经过生长的单晶氧化物层进行扩散。经过钛酸钡扩散的氧与区域54表面的硅进行反应，从而形成在第二区域上和在硅基片与单晶氧化物之间的界面上的非晶态硅氧化物层62。
按照本发明的一种实施方案，沉积单晶氧化物层60的步骤通过沉积第二模板层64来终止，所述第二模板层可为1-10单层的钛、钡、钡和氧、或钛和氧。然后通过分子束外延法沉积一层单晶化合物半导体材料层66来覆盖第二模板层。通过在模板上沉积一层砷来起始层66的沉积。这种起始步骤之后接着进行镓和砷的沉积来形成单晶砷化镓。另外，在以上实施例中的钡可由锶替代。
按照本发明的另一实施方案，在化合物半导体层66中形成由虚线68总体标明的半导体元件。可通过制造砷化镓或其它III-V化合物半导体材料设备所通用的加工步骤来形成半导体元件68。半导体元件68可为任何有源或无源元件，优选为半导体激光、发光二极管、光电探测器、异质结双极晶体管(HBT)、高频MESFET、或利用了化合物半导体材料的物理性能的其它元件。可形成由线70所示意标明的金属导体来使设备68与设备56电连接，从而实现包括至少一种在硅基片上形成的元件和在单晶化合物半导体材料层中形成的一种设备的集成设备。虽然例举性结构50叙述为在硅基片52上形成的结构，并具有钛酸钡(或锶)层60和砷化镓层66，但可使用在本公开内容中其它处叙述的其它的基片、单晶氧化物层和其它化合物半导体层来制造相似的设备。
图5图示了按照本发明的另一实施方案的半导体结构72。结构72包括单晶半导体基片74如包括区域75和区域76的单晶硅晶片。使用在半导体工业中通用的常规硅设备加工技术来在区域75中形成由虚线78所示的电子元件。使用与上述相似的加工步骤，形成覆盖模板74的区域76的单晶氧化物层80和中间非晶态硅氧化物层82。在单晶氧化物层80之上形成模板层84和随后的单晶半导体层86。按照本发明的另一实施方案，通过与形成层80所使用的相似的加工步骤来形成覆盖层86的附加单晶氧化物层88，并通过与形成层86所使用的相似的加工步骤形成覆盖单晶氧化物层88的附加单晶半导体层90。按照本发明的一种实施方案，由化合物半导体材料形成层86和90中的至少一种。
由虚线92总体标明的半导体元件至少部分是在单晶半导体层86中形成。按照本发明的一种实施方案，半导体元件92可包括具有部分通过单晶氧化物88形成的栅极电介质的场效应晶体管。另外，单晶半导体层92可用来实现该场效应晶体管的门电极的功能。按照本发明的一种实施方案，由III-V族化合物来形成单晶半导体层86，且半导体元件92是利用了III-V族组成材料的高迁移率特性的射频放大器。按照本发明的另一种实施方案，由线94所示的连接线路将元件78和元件92电连接。因而结构72使利用了两种单晶半导体材料的独特性能的元件结合为整体。
作为更具体的实例，在图6-18中图示了其它集成电路和系统。图6包括一个简化的框图，其图示了通信设备100的一部分，所述设备100具有信号收发装置101、集成电路102、输出单元103、和输入单元104。信号收发装置的实例包括天线、调制解调器、或信息或数据可由其输出至外部单元或由外部单元输入的任何其它装置。在这里，收发用来指所述信号收发装置能够仅接收、仅传递、或同时接收和传递来自通信设备的信号或传递信号至通信装置。输出单元103可包括显示器、监测器、扬声器、或类似物。输入单元可包括话筒、键盘、或类似物。注意在可选择的实施方案中，输出单元103和输入单元104可由单一单元如存储器等来替换。所述存储器可包括随机存取存储器或非易失性存储器，如硬盘、闪存卡或组件、或类似物。
集成电路通常是在连续基片上或其内不可分离地连接的至少两种电路元件(如晶体管、二极管、电阻器、电容器等)的组合。集成电路102包括化合物半导体部分1022、双极部分1024、和MOS部分1026。化合物半导体部分1022包括至少部分在化合物半导体材料内形成的电子元件。在化合物半导体部分1022内的晶体管和其它电子元件能够处理至少约为0.8GHz的射频信号。在其它实施方案中，所述信号可为更低或更高的频率。例如，某些材料如铟砷化物能够加工约为27GHz的射频信号。
化合物半导体部分1022还包括双工器10222、射频至基带转换器10224(解调装置或解调电路)、基带至射频转换器10226(调制装置或调制电路)、功率放大器10228、和隔离器(isolator)10229。双极部分1024和MOS部分1026通常由IV族半导体材料来制备。所述双极部分1024包括接收放大器10242、模拟-数字转换器10244、数字-模拟转换器10246、和输出放大器10248。MOS部分1026包括数字信号处理装置10262。这类装置的一种实例包括在市场上可得到的任何通常可得到拓DSP芯片(cores)，如Motorola DSP 566xx(得自Motorola，Incorporated ofSchaumburg，Illinois)和Texas Instruments TMS 320C54x(得自TexasInstruments of Dallas，Texas)族的数字信号处理器。这种数字信号处理装置10262通常包括辅助MOS(CMOS)晶体管和模-数和数-模转换器。显然，在集成电路102中存在其它电子元件。
在一种操作方式中，通信装置100接收来自天线的信号，所述天线是信号收发装置101的部件。所述信号经由双工器10227传送至射频-至-基带转换器10224。通过接收放大器10224所述模似数据或其它信息被放大并传送至数字信号处理装置10262。在所述数字信号处理装置10262对信息或其它数据进行处理之后，处理过的信息或其它数据传送至输出单元103。如果通信装置是寻呼机，则输出单元可是显示器。如通信装置是蜂窝式电话，则输出单元103可包括扬声器、显示器、或两者均包括。
数据或其它信息可以按相反方向经由通信装置100传送。所述数据或其它信息经由输入单元104输入。在蜂窝式电话中，这可包括话筒或小键盘。所述信息或其它数据然后使用数字信号处理装置10262进行处理。在处理后，所述信号然后使用数-模转换器10246进行转换。转换过的信号通过输出放大器10248进行放大。放大过的信号通过基带-至-射频转换器10226进行调制并通过功率放大器10228进一步放大。放大后的RF信号经过隔离器10229和双工器10222传送至天线。
现有技术的通信装置100具有至少两个独立的集成电路：一个用于化合物半导体部分1022，一个用于MOS部分1026。双极部分1024可与MOS部分1026同在一个集成电路上，或者可在另一个集成电路上。而对于本发明的实施方案，所有三部分现均可在单一的集成电路内形成。由于所有晶体管可位于单一的集成电路上，所述通信装置可大大地小型化，并使通信装置具有更大的便携性。
现在关注如图7-11所示的集成电路102的实例部分的制备方法。在图7中，提供了p型掺杂、单晶硅基片110，其具有化合物半导体部分1022、双极部分1024、和MOS部分1026。在双极部分内，对单晶硅基片进行掺杂来形成N+埋入区1102(buried region)。然后在所述埋入区1102和基片110之上形成轻微p型掺杂的外延单晶硅层1104。然后进行掺杂步骤来产生在N+埋入区1102之上的轻微n型掺杂的漂移区1117。所述掺杂步骤将双极区1024段内的轻微p型外延层的掺杂剂类型转换为轻微n型单晶硅区。然后在双极部分1024与MOS部分1026之间形成场隔离区1106。在MOS部分1026内的部分外延层1104之上形成栅极电介质层1110，然后在所述栅极电介质层1110之上形成栅电极1112。沿栅电极1112和栅极电介质层1110的垂直边来形成侧壁隔板(sidewallspacers)1115。
向漂移区1117引入p型掺杂剂来形成活性或固有(active orintrinsic)的基极区1114。然后在双极部分1024内形成n型、深集电极区1108以使得与埋入区1102电连接。进行选择性n型掺杂来形成N+掺杂区1116和发射极区1120。在层1104内沿栅电极1112边来形成N+掺杂区1116，且其是MOS晶体管的源区、漏区、或源/漏区。N+掺杂区1116和发射极区1120具有每立方厘米至少1E19原子的掺杂浓度以使得形成电阻性接触。形成p型掺杂区来产生非活性的或非固有的基极区1118，其为P+掺杂区(掺杂浓度为每立方厘米至少1E19原子)。
在所述的实施方案中，已进行了若干个加工步骤，但对其未进行图示或进一步进行叙述，如形成了阱区、阈值调整注入物、防通道穿通注入物、防场穿通注入物、以及各种掩蔽层。在所述方法中至此的设备制备均使用通用步骤来进行。如所图示的，在MOS区1026内已形成了标准N通道MOS晶体管，且在双极部分1024内已形成了垂直NPN双极晶体管。至此，在化合物半导体部分1022内未形成电路。
从化合物半导体部分1022的表面现在除去在集成电路的双极和MOS部分的加工过程中已形成的所有层。从而对这一部分的后续的加工提供裸露的硅表面，例如以上述方式。
然后在基片110上形成图8所示的缓冲适应层124。在部分1022中的适当制备(即，具有适当的模板层)的裸露硅表面上来形成呈单晶层的所述缓冲适应层。但在部分1024和1026上形成的层124部分可为多晶态或非晶态的，因为其是在非单晶材料上形成的，因而不对单晶生长起成核作用。所述缓冲适应层124通常是单晶金属氧化物或氮化物层，通常厚度范围约为2-100纳米。在一种具体实施方案中，所述缓冲适应层为约5-15nm厚。在所述缓冲适应层的形成过程中，沿集成电路102的最顶部硅表面形成非晶态中间层122。这种非晶态中间层122通常包括硅的氧化物，其厚度范围约为1-5nm。在一种具体实施方案中，所述厚度为约2nm。在形成缓冲适应层124和非晶态中间层122之后，然后形成模板层126，其厚度范围为约1至10单层材料。在一种具体实施方案中，所述材料包括钛-砷、锶-氧-砷、或与参照图1-5前面所述相似的材料。
然后如图9所示在缓冲适应层124的单晶部分之上来外延生长单晶化合物半导体层132。在为非单晶态的层124部分上生长的层132部分可是多晶态或非晶态的。可通过许多方法来形成所述单晶化合物半导体层，其通常包括如砷化镓、铝镓砷化物、铟磷化物、或前述的其它化合物半导体材料。该层厚度范围约为1-5000nm，更优选100-500nm。在这种具体实施方案中，在所述缓冲适应层124、单晶化合物半导体材料132、或两者中也存在模板层的各种元素(elements)。因而，在加工过程中，所述模板层126与其两紧邻层之间的界限消失。因而，当摄制透射电子显微(TEM)照片时，可见缓冲适应层124与单晶化合物半导体层132之间的界面。
在这一点上，如图10所示从覆盖双极部分1024和MOS部分1026的部分中除去化合物半导体层132和缓冲适应层124区段。在除去所述区段后，然后在基片110上形成隔离层142。所述隔离层142可包括许多材料如氧化物、氮化物、氧氮化物、低k电介质、或类似物。在这里使用时，低k是具有不高于约3.5的介电常数的材料。在已沉积了隔离层142后，然后对其进行抛光，除去覆盖单晶化合物半导体层132的隔离层142的部分。
然后在单晶化合物半导体部分1022内形成晶体管144。然后在单晶化合物半导体层132上形成栅电极148。然后在单晶化合物半导体层132内形成掺杂区146。在这一实施方案中，所述晶体管是金属半导体场效应晶体管(MESFET)。如果所述MESFET是n型MESFET，则所述掺杂区146和单晶化合物半导体层132也是n型掺杂的。如果要形成p型MESFET，则所述掺杂区146和单晶化合物半导体层132将为相反的掺杂类型。较重的掺杂(N+)区146使得可与单晶化合物半导体层132进行电阻性接触。在这一点上，已形成了集成电路内的有源设备。这一具体实施方案包括n型MESFET、垂直NPN双极晶体管、和平板n通道MOS晶体管。可使用许多其它类型的晶体管，包括p通道MOS晶体管、p型垂直双极晶体管、p型MESFET、及垂直与平板晶体管的结合。另外，在一或多种的部分1022、1024、和1026中可形成其它电子元件，如电阻器、电容器、二极管、及类似物。
加工持续至形成如图11所示的基本完成的集成电路102。在基片110上形成隔离层152。所述隔离层152可包括在图11中未示出的刻蚀终止区或抛光终止区。然后在第一隔离层152之上形成第二隔离层154。除去部分层154、152、142、124、和122以界定要对所述设备进行互相连接的接触开口。在隔离层154内形成互连槽以提供接触点之间的横向连接。如图11所示，互连1562使部分1022内的n型MESFET的源或漏区与双极部分1024内的NPN晶体管的深集电极区1108相连接。NPN晶体管的发射极区1120与MOS部分1026内的n通道MOS晶体管的一个掺杂区1116相连接。其它掺杂区1116与集成电路未示出的其它部分相电连接。
在互连物1562、1564、和1566和隔离层154之上形成钝化层156。对所示的晶体管以及在所述图中未示出的集成电路102内的其它电子或电器元件进行电连接。再有，如必要可形成附加隔离层和互连来形成集成电路102内各种元件的适当互连。
如从前述实施方案中可见，化合物半导体和IV族半导体材料两者的有源设备可组合在单一的集成电路中。由于在同一集成电路内包含双极晶体管和MOS晶体管有一些困难，可将双极部分中的一些元件移入到化合物半导体部分1022或MOS部分1024中。更具体地说，对于参照图6所述的实施方案，可将放大器10248和10242移入到化合物半导体部分1022中，转换器10244和10246可移入到MOS部分1026中。因而，可消除只用于制备双极晶体管所需要的特殊制造步骤。因而，集成电路只有化合物半导体部分和MOS部分。
在另一实施方案中，可制备一种集成电路，其包括在化合物半导体部分中的激光器和与同一集成电路的IV族半导体区的MOS晶体管的光学互连(光波导管)。图12-18包括对一种实施方案的图示说明。
图12图示了一种包括单晶硅晶片161的集成电路160的一部分的横断面图。在晶片161上形成了与前述相似的非晶态中间层162和缓冲适应层164。在这种具体实施方案中，首先形成需要构成激光器的层，随后形成MOS晶体管所需的层。在图12中，下部镜面层(mirror layer)166包括化合物半导体材料的交替层。例如，在激光器内的第一、第三、和第五层膜可包括如砷化镓的材料，下部镜面层166内的第二、第四、和第六层膜可包括铝镓砷化物或次序相反。层168包括用于产生光子的有源区。上部像层170以与下部镜面层166相似的方式形成，且其包括化合物半导体材料的交替膜。在一种具体实施方案中，上部镜面层170可为p型掺杂化合物半导体材料，下部镜面层166可为n型掺杂化合物半导体材料。
与缓冲适应层164相似，在上部镜面层170之上形成另一缓冲适应层172。在另一种实施方案中，所述缓冲适应层164和172可包括不同的材料。但它们的功能基本相同，各用于产生由化合物半导体层至单晶IV族半导体层的转变。在缓冲适应层172之上形成单晶IV族半导体层174。在一种具体实施方案中，所述单晶IV族半导体层174包括锗、硅锗、硅锗碳化物、或类似物。
在图13中，对MOS部分进行加工来形成在这种上部单晶IV族半导体层174内的电子元件。如图13所示，由层174部分来形成场隔离区171。在层174之上形成栅极电介质层173，并在栅极电介质层173之上形成栅电极175。掺杂区177是晶体管181的源、漏区、或源/漏区，如图所示。邻近栅电极175的垂直侧形成侧壁隔板(sidewall spacer)179。可在至少部分层174内来形成其它元件。这些其它元件包括其它晶体管(n通道或p通道)、电容器、晶体管、二极管、及类似物。
在一种掺杂区177之上来外延生长单晶IV族半导体层。上部部分184是P+掺杂的，下部部分182基本上仍为固有的(未掺杂的)，如图13所示。可使用选择性外延方法来形成所述层。在一种实施方案中，在晶体管181和场隔离区171之上形成隔离层(未示出)。所述隔离层的图案形成为限定一个暴露一种掺杂区177的开口。所述选择性外延层至少最初制备为无掺杂剂。所述的全部选择性外延层可是固有的，或在接近形成选择性外延层结束时添加p型掺杂剂。如果所述选择性外延层是固有的，如所形成的那样，可通过注入(Implantation)或通过炉掺杂来进行掺杂步骤。无论P+上部部分184如何形成，然后除去隔离层来形成图13中所示的所得到的结构。
进行后续系列步骤来限定如图14所示的激光器180。除去集成电路的化合物半导体部分之上的场隔离区171和缓冲适应层172。进行附加的步骤来确定上部镜面层170和激光器180的有源层168。上部镜面层170和有源层168是基本上相连的。
形成接触物186和188使其分别与上部镜面层170和下部镜面层166电连接，如图14所示。接触物186具有环形形状以使光线(光子)穿过上部镜面层170进入随后形成的光波导管。
然后形成隔离层190，其图像形成为限定延伸至接触层186和一种掺杂区177的光学开口，如图15所示。所述隔离材料可为任何种不同的材料，包括氧化物、氮化物、氧氮化物、低k电介质、或它们的任何组合。在限定了开口192后，然后在所述开口内形成更高折射率材料202来对其填充并在隔离层190之上来沉积该层，如图16所示。对于更高折射率材料202，“更高”是相对于隔离层190的材料(即，材料202具有比隔离层190更高的折射率)。任选地还可以在形成更高折射率材料202之前先形成较薄的较低折射率膜(未示出)。然后在高折射率层202之上形成硬掩蔽层204。从覆盖所述开口及接近图16的侧边区域的部分中除去部分硬掩蔽层204、和高折射率层202。
完成形成作为光学互连物的光波导管的其余步骤，如图17所示。进行一种沉积步骤(可为沉积-刻蚀(dep-etch)方法)来有效地产生侧壁段212。在这种实施方案中，所述侧壁段212由与材料202相同的材料来制备。然后除去硬掩蔽层204，在更高折射率材料212和202之上形成低折射率层214(相对于材料202和层212低)并暴露出部分隔离层190。在图17中的虚线所示为高折射率材料202和212之间的边界。这种作法的目的是确定所述两者均由相同的材料制备但在不同时间来形成。
继续进行加工来形成如图18所示的基本完成的集成电路。然后在激光器180和MOSFET晶体管181之上形成纯化层220。虽未示出，但对集成电路内未在图18中图示的元件进行了其它的电或光学连接。这些互连可包括其它光波导管或可包括金属互连。
在其它实施方案中，可形成其它类型的激光器。例如，另一种类型的激光器可水平而不是垂直地发射光(光子)。如果光水平发射，则所述MOSFET晶体管可在基片161中形成，并可变换光波导管的结构，使得所述激光器与所述晶体管适当地连接(光学连接)。在一种具体实施方案中，所述光波导管可包括至少部分缓冲适应层。还可以是其它结构。
显然，这些具有化合物半导体部分和IV族半导体部分的集成电路的实施方案是用来对本发明的实施方案进行说明而不是对本发明进行限制。本发明可有多种其它组合和其它实施方案。例如，所述化合物半导体部分可包括发光二极管、光检测器、二极管、或类似物，所述IV族半导体可包括数字逻辑电路、存储器阵列、和在通用MOS集成电路中可形成的大多数结构。通过使用本发明的实施方案，现在可更简单地使在化合物半导体材料中更好运行的设备与在IV族半导体材料中更好运行的其它元件组合。这使得装置缩小，制造成本降低，增加产率和可靠性。
虽然未进行图示，但可使用单晶IV族晶片来在所述晶片上只形成化合物半导体电子元件。以这种方式，所述晶片实际为在覆盖所述晶片的单晶化合物半导体层内化合物半导体电子元件的制造过程中所使用的“操作”晶片。因而，可在直径至少为约200毫米并可至少为约300毫米的晶片上的III-V或II-VI半导体材料内来形成电子元件。
通过使用这种类型的基片，通过将其置于相对更耐久并易于制造的基体材料上，较廉价的“操作”晶片克服了化合物半导体晶片的脆性。因而，可形成集成电路使得所有电子元件、特别是所有有源电子设备可在化合物半导体材料内形成，尽管所述基片本身可包括IV族半导体材料。由于与较小和更易碎的通用化合物半导体晶片相对比，较大基片可更经济更容易地进行加工，所以化合物半导体设备的制造成本应降低。
在前述的说明中，参照具体实施方案对本发明进行了叙述。但本领域普通技术人员可理解，在不偏离以下权利要求书所限定的本发明的范围的条件下，还可进行各种改进和变化。对应的，所述说明和附图应认为是说明性的而不是限制性的，所有这些改进都包括在本发明的范围内。
以上针对具体实施方案叙述了益处、其它优点、和对问题的解决方案。但所述益处、其它优点、对问题的解决方案、和可使任何益处、优点、或解决方案看起来或变得更明显的任何要素都不应认为是任何或全部权利要求的关键、需要、或必需的特征或要素。在这里使用时，术语“包括”、“包含”或其任何其它变化形式是指覆盖了非排除性的包括，因而包括一系列要素的过程、方法、器具、装置不是仅包括那些要素，而是可包括其它未列举或这些过程、方法、器具、或装置所固有的要素。

Claims (48)

1.一种制造半导体结构的方法，包括如下步骤：
提供包括硅的单晶半导体基片；
外延生长覆盖该单晶基片的单晶氧化物层；
在所述外延生长步骤的过程中对单晶半导体基片进行氧化以形成在所述单晶半导体基片与单晶氧化物层之间的硅氧化物层；
外延生长覆盖该单晶氧化物层的单晶化合物半导体层。
2.根据权利要求1的方法，还包括在该单晶半导体基片上形成第一模板层的步骤。
3.根据权利要求2的方法，其中所述提供单晶半导体基片的步骤包括提供在其表面上具有硅氧化物层的基片，且形成所述第一模板层的步骤包括如下步骤：
在所述硅氧化物层上沉积选自钡和锶的材料，和
加热所述基片以使所述材料与硅氧化物进行反应。
4.根据权利要求2的方法，其中所述提供单晶半导体基片的步骤包括提供在其表面上具有硅氧化物层的基片，且形成所述第一模板层的步骤包括如下步骤：
在所述硅氧化物层上沉积锶和氧，和
加热所述基片以使锶和氧与硅氧化物进行反应。
5.根据权利要求1的方法，其中外延生长单晶氧化物层的步骤包括如下步骤：
将所述基片加热至约400℃至约600℃之间的温度；和
引入包括锶、钛、和氧的反应物。
6.根据权利要求5的方法，其中所述引入步骤包括控制锶与钛的比例和控制氧的分压。
7.根据权利要求6的方法，其中所述对单晶半导体基片进行氧化的步骤包括将氧的分压增加至高于外延生长单晶氧化物层所必需的数值。
8.根据权利要求1的方法，还包括形成覆盖所述单晶氧化物层的第二模板层的步骤。
9.根据权利要求8的方法，其中形成第二模板层的步骤包括用包含选自钛、钛和氧、锶、和锶和氧材料的单层的层来覆盖单晶氧化物层的步骤。
10.根据权利要求9的方法，其中外延生长单晶化合物半导体层的步骤包括：
在第二模板层上沉积砷；和
使砷与第二模板层上的材料进行反应。
11.根据权利要求10的方法，其中外延生长单晶化合物半导体层的步骤还包括在反应步骤之后来沉积镓和砷的步骤。
12.根据权利要求8的方法，还包括形成覆盖第二模板层的缓冲层的步骤。
13.根据权利要求1的方法，还包括形成覆盖单晶氧化物层的缓冲层的步骤。
14.根据权利要求13的方法，其中所述形成缓冲层的过程包括外延沉积覆盖单晶氧化物层的锗层的步骤。
15.根据权利要求13的方法，其中所述形成缓冲层的过程包括沉积包括III-V族化合物半导体材料的超晶格的步骤。
16.根据权利要求1的方法，其中所述外延生长单晶氧化物层的步骤包括外延生长碱土金属钛酸盐的步骤。
17.根据权利要求16的方法，其中所述外延生长单晶化合物半导体层的步骤包括外延生长一层选自GaAs，AlGaAs，ZnSe，和ZnSSe的材料的步骤。
18.根据权利要求1的方法，其中所述外延生长单晶氧化物层的步骤包括外延生长选自碱土金属锆酸盐和碱土金属铪酸盐的氧化物的步骤。
19.根据权利要求18的方法，其中所述外延生长单晶化合物半导体层的步骤包括外延生长选自InP和InGaAs的化合物半导体材料的单晶层。
20.根据权利要求19的方法，还包括通过沉积一层厚度为约1-10单层的材料来形成覆盖单晶氧化物层的第二模板层的步骤，所述材料选自Zr-As、Zr-P、Hf-As、Hf-P、Sr-O-As、Sr-O-P、Sr-As，Sr-P，Ba-O-As、Ba-O-P，Ba-As，Sr-Ga-O，Ba-Ga-O，和Ba-P。
21.根据权利要求1的方法，其中外延生长单晶氧化物层的步骤包括以每分钟约0.3-0.5nm的生长速率来外延生长。
22.一种制造半导体结构的方法，包括如下步骤：
提供单晶半导体基片；
外延生长覆盖该单晶基片的单晶氧化物层；
在所述外延生长步骤的过程中对单晶半导体基片进行氧化以形成在所述单晶半导体基片与单晶氧化物层之间的硅氧化物层；
外延生长覆盖该单晶氧化物层的单晶化合物半导体层。
23.一种制造半导体结构的方法，包括如下步骤：
提供具有表面的单晶氧化物层；
在所述表面上形成模板层；和
外延生长覆盖所述模板的单晶化合物半导体层。
24.根据权利要求23的方法，其中所述提供单晶氧化物层的步骤包括提供包含选自碱土金属钛酸盐、碱土金属锆酸盐、和碱土金属铪酸盐的材料的单晶氧化物层。
25.根据权利要求23的方法，其中所述提供单晶氧化物层的步骤包括外延生长与其下层单晶硅基片相匹配的单晶氧化物层晶格。
26.根据权利要求23的方法，其中所述提供单晶氧化物层的步骤包括提供包含SrzBa1-zTiO3的氧化物层，其中z的范围为0至1。
27.根据权利要求26的方法，其中所述形成模板层的步骤包括用选自Ti，TiO，Sr，和SrO的1-10单层材料来覆盖所述氧化物层。
28.根据权利要求27的方法，其中所述外延生长单晶化合物半导体层的步骤包括外延沉积选自GaAs，AlGaAs，GaAsP，和GaInP的层。
29.根据权利要求27的方法，还包括沉积覆盖所述模板层的缓冲层的步骤。
30.根据权利要求29的方法，其中所述沉积缓冲层的步骤包括外延沉积一种材料的超晶格层，所述材料选自其中x范围为0至1的GaAsxP1-x和其中y范围为0至1的InyGa1-yP。
31.根据权利要求30的方法，其中所述外延生长单晶化合物半导体层的步骤包括外延沉积选自GaAs，AlGaAs，GaAsP，GaInAs，InP和GaInP的层。
32.根据权利要求26的方法，所述形成模板层的步骤包括用选自Ge-Sr和Ge-Ti的1-10单层材料来覆盖单晶氧化物层的步骤。
33.根据权利要求32的方法，还包括外延沉积锗缓冲层的步骤。
34.根据权利要求26的方法，其中所述形成模板层的步骤包括如下步骤：
用1-10单层的ZnO来覆盖单晶氧化物层；和
在单层ZnO之上沉积1-3单层的富锌ZnO。
35.根据权利要求34的方法，其中所述外延生长单晶化合物半导体层的步骤包括外延生长选自ZnSe和ZnSeS的层。
36.根据权利要求26的方法，其中所述形成模板层的步骤包括用1-2单层的SrS覆盖单晶氧化物层的步骤。
37.根据权利要求36的方法，其中所述外延生长单晶化合物半导体层的步骤包括外延生长ZnSeS层。
38.根据权利要求23的方法，其中所述提供单晶氧化物层的步骤包括提供包含一种材料的单晶氧化物层，所述材料选自碱土金属锆酸盐、和碱土金属铪酸盐。
39.根据权利要求38的方法，其中所述形成模板层的步骤包括用1-10单层的一种材料来覆盖单晶氧化物层，所述材料选自Zr-As、Zr-P、Hf-As、Hf-P、Sr-As，Sr-O-As、Sr-P，Sr-O-P、Ba-As，Ba-O-As、Ba-P、Sr-Ga-O，Ba-Ga-O，和Ba-O-P。
40.根据权利要求39的方法，其中所述外延生长单晶化合物半导体层的步骤包括外延生长包含选自InP和InGaAs的材料的层。
41.根据权利要求40的方法，还包括沉积在所述模板层上的包含超晶格的缓冲层，所述超晶格包含InGaAs，其中铟的范围为0至约47％。
42.一种制造半导体结构的方法，包括如下步骤：
提供单晶半导体基片；
形成覆盖该单晶半导体基片的缓冲适应层；
形成在所述单晶半导体基片与所述缓冲适应层之间的非晶态中间层；和
外延生长覆盖该缓冲适应层的单晶化合物半导体层。
43.根据权利要求42的方法，其中所述形成非晶态中间层的步骤包括使氧经所述缓冲适应层扩散来氧化所述单晶半导体基片的步骤。
44.根据权利要求42的方法，其中所述形成缓冲适应层的步骤包括通过选自MBE、MOCVC、MEE、和ALE的方法来生长一种外延层。
45.根据权利要求42的方法，其中所述提供单晶半导体基片的步骤包括提供在其表面具有硅氧化物层的单晶硅基片。
46.根据权利要求45的方法，其中所述形成缓冲适应层的步骤包括如下步骤：
使选自Sr和SrO的材料与硅氧化物层进行反应来在硅基片表面形成模板；和
在所述模板上外延沉积包含SrzBa1-zTiO3的层，其中z的范围为0至1。
47.根据权利要求42的方法，还包括在所述外延生长步骤之前形成覆盖所述缓冲适应层的模板的步骤。
48.一种制造半导体结构的方法，包括如下步骤：
提供包含第一区和第二区的单晶硅基片，所述第二区具有氧化的表面；
在所述第一区中形成CMOS电路；
在具有氧化的表面的第二区上沉积包含锶的材料，并使所述材料与氧化的表面进行反应来形成第一模板层；
通过向所述模板层引入锶、钛、和氧的分压来在所述第一模板层之上沉积包含锶、钛和氧的单晶氧化物层；
增加氧的分压来在所述第二区上生长非晶态硅氧化物层；
通过沉积包括包含钛的单层的第二模板层来终止沉积单晶氧化物层的步骤；
在所述第二模板层之上沉积一层包含镓和砷的单晶化合物半导体材料；
在所述单晶化合物半导体材料层中形成半导体元件；和
沉积金属导体，其设置为使所述CMOS电路与半导体元件电连接。
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US20040232525A1 (en) 2004-11-25
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US6392257B1 (en) 2002-05-21
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