CN1409872A - 在晶片级上形成的集成电路封装 - Google Patents

在晶片级上形成的集成电路封装 Download PDF

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CN1409872A
CN1409872A CN00817202A CN00817202A CN1409872A CN 1409872 A CN1409872 A CN 1409872A CN 00817202 A CN00817202 A CN 00817202A CN 00817202 A CN00817202 A CN 00817202A CN 1409872 A CN1409872 A CN 1409872A
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CN1217410C (zh
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K·M·拉姆
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Atmel Corp
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Abstract

一种在晶片级形成的集成电路。集成电路封装(70)在最终使用的印刷电路板上占据了最小量的空间。由金属电路(34)和介电基底(32)制成的预制插入基片(30)具有多个金属化孔，它们与硅片(21)顶表面上的金属化引线接合点对准。焊料(40)或导电粘合剂通过金属化孔沉积以便在插入层(30)的电路和晶片(21)上的电路之间形成电气连接。随后，在插入基片(30)上的金属点孔上放置焊球(50)，并回流以形成晶片级BGA结构。随后，将晶片级BGA结构切割成单独的BGA芯片封装。

Description

在晶片级上形成的集成电路封装
技术领域
本发明通常涉及集成电路封装，尤其是在晶片级上形成的球栅阵列集成封装。
背景技术
在电路板上的集成电路封装的占地面积是指封装所占用的基板面积。通常需要使占地面积最小化，并将封装紧靠在一起放置。近年来，球栅阵列(BGA)封装已经成为一种越来越流行的封装类型，因为它提供了高密度、占地面积最小以及更短的电子路径的优点，这就意味着它比先前的半导体封装类型具有更好的性能。
如图9所示是一种典型的BGA封装。在BGA封装110中，集成电路芯片122通过粘合剂安置在由基片材料制成的基底112的上表面上。金属焊线或引线接合导线120将在芯片122上表面形成的多个金属芯片焊点126与在基底112上表面形成的引线接合焊点128相连。基底112包括电镀通孔通道118以及金属连线114以便从基底112的上表面到下表面连接电路。多个焊球116放置在基底112的底面上，并且与基底金属连线114电气连接。焊球116可以以均匀完整的矩阵阵列方式配置在整个底表面上，以交错完整阵列方式或围绕底表面的周长以多排形式配置。随后，焊球就用于紧固最终使用产品中印刷电路板上的芯片封装。
尽管，已有技术的BGA封装与早期的封装类型相比在高密度和高I/O容量方面提供了极大的改善，还是希望能够使得IC封装更加小巧以进一步减少印刷电路板上安置封装所需的空间。因为引线接合具有预定长度且在相邻焊点之间需要最小的间距以便为焊头提供足够的空间，因此，基片基底必须比芯片更长，这就不可能制造出更加紧凑的封装。从理想上来说，需要制造一种封装，其基片基底并不需要比芯片的尺寸大。
在已有技术中，如上所述，为每个单独的硅片制造一个封装是很普通的情况。另一些认识到在晶片级形成IC封装具有优势，就是说，在晶片上已经形成单独的芯片之后，但在晶片已经切成单独的芯片之前。这就允许更加容易地进行芯片封装的大规模生产，并且对于以矩阵格式配置在晶片上的几个芯片封装来说可以一次制造出来并测试。这就能减少封装和测试IC芯片处理过程中的时间和成本。
已有技术中在晶片级实施的一些封装方法实例包括：Warfield的美国专利号5,604,160，揭示了使用帽盖晶片在器件晶片上封装半导体器件；Salatino等人的美国专利号5,798,557，描述了一种晶片级密封封装集成电路，该电路具有与半导体器件基片基底焊接的保护盖晶片；以及Wood等人的国专利号5,851,845，揭示了一种形成半导体封装的方法，该方法是通过配置含有多个硅片的晶片，经磨光或蚀刻使晶片后部变薄，将较薄的晶片附着在基片上，并随后将晶片切割成小方块来实现。
本发明的目标是提供一种具有最小尺寸的球栅阵列IC封装，这样，该IC封装所占据的空间不会超过IC芯片的面积。
本发明的另一目标是提供一种晶片级IC封装，以便在大规模生产中获得更好的效率，并且能并行执行IC封装检测。
发明内容
上述目标已经在一种使用单晶片倒装芯片设计在晶片级上形成的集成电路封装中实现。集成电路封装的形成是通过：首先配置硅片制品，它具有多个在其上制造的微电路以及多个暴露的标准铝焊接区。对铝焊接区重新进行金属化以使其可软焊。随后，在晶片表面上沉积粘合层，并保持焊接区暴露。将预先制成具有经金属化孔的插入基片对准晶片，并随后固化组件。随后，通过基片上的孔沉积焊料或导电粘合剂，并且对组件进行回流或固化，以便在基片上的电路和硅片上的焊接区之间形成电气连接。随后，在金属焊点或基片上配置焊球，并随后回流形成BGA结构。随后，将晶片切割成小块，这就形成了单独的BGA封装。对该BGA封装进行翻转，以便安置在电路板上。
由于并不需要使用引线接合导线，本发明的集成电路封装与通常需要额外空间的已有技术的BGA封装相比更小。这个晶片可以一次就完全封装完成，这比单独封装每个硅片更加有效，并且允许并行测试封装块，而仍然保持晶片形式。
附图说明
图1是硅片的透视图，在顶表面上形成有多个芯片。
图2是如图1所示的硅片部分2-2的截面图。
图3-6是图1硅片的截面图，示出在形成本发明IC封装中使用的各种处理步骤。
图7是图1硅片的截面图，示出本发明IC封装的最终晶片组件。
图8是本发明最终IC封装的截面图。
图9是如已有技术所示的球栅阵列封装截面图。
具体实施方式
参照图1，硅片21具有多个构成在其上的微电路。微电路配置成单独芯片或方块24、25矩阵形式。围绕每个芯片周长配置了多个铝焊接区23。在已有技术封装操作中，晶片21通常在这里切成单独的芯片，并随后封装每个单独的芯片。在本发明中，在晶片上形成芯片，但直到完成晶片上的封装操作才进行切割，这样，芯片的封装就可以在晶片级实施。
参照图2，示出晶片21的剖面2-2以及放置在晶片21顶表面上的铝焊接区23。封装处理中的第一步骤是对铝焊接区23重新进行金属化以便使得焊接区可软焊。铝(通常用于IC的引线接合焊点)并不是用于焊接连接的理想金属，因为铝容易氧化，从而产生焊接问题。在本发明的IC封装形成中，铝焊接区需要通过焊料保持潮湿，或通过应用导电粘合剂而具有电阻性接触电阻。因此，需要对焊接区重新进行金属化。一种对焊接区重新金属化的处理(廉价而又方便)是使用无电镍金电镀。参照图3，首先，在铝焊接区23上沉积锌层，随后在锌层上沉积无电镍电镀层，并随后在无电镍电镀层上沉积无电镍金电镀层以形成镍金电镀19，使得焊接区23对焊接导电。或者，可以执行薄膜金属化处理对焊接区重新进行金属化。
接着，参照图4，粘合剂27层沉积在晶片21的顶表面上，这样，就留下焊接区23仍然未被覆盖。粘合剂可以由硅酮弹性体制成。粘合剂层27可以通过丝网印刷处理实施，在该处理中，硅酮弹性体材料通过漏印板或网筛的孔进行按压。筛网安置在丝网印刷机上，并且相对于晶片被精确定位。沿筛网的一边配制一定量的硅酮弹性体材料，并且将气动式括板按压在筛网上，使其在筛网上括过，以恒定压力括出材料。材料需要高于剪切压力的更高流动性，这就允许其通过筛网，并且填充筛网的金属丝网留下的间隙。阻塞在焊接区23上的区域，以便在焊接区的顶部不会覆盖材料。移除筛网，而在晶片顶部上就形成均匀的材料层。或者，预先形成的粘合剂层可以用于将粘合剂层27粘合到晶片21的顶表面或粘合到插入基片层的后部。硅酮弹性体是作为密封剂使用，为晶片提供了外界保护。硅酮弹性体也作为晶片21对外界压力的缓冲区，例如晶片和用于安置IC封装的封装焊球之间的热膨胀失配系数，或晶片和将安置IC封装的最终印刷电路板之间的失配。
参照图5，随后，在弹性体层27顶部上固定插入基片层30以形成晶片组件39。插入基片30是预先形成的由金属电路34和介电基底32组成的基片。金属电路34通常由在整个基片上形成的铜连线组成。插入基片30还可以包括阻焊敷层以帮助限定铜金属电路上的焊接可湿区域。金属电路34可以在插入基片的单层或多层上形成。铜金属电路可以是镍金电镀或通过有机材料敷层。介电基底材料32通常由聚酰胺基底基片制成。或者，RT树脂和其他环氧玻璃基片也可以作为介电基底材料32使用。金属电路34通常作为互连电路，因为连线可以在整个基片上布线以便将互连各个焊接区23的电路互连到输入/输出(I/O)互连，如随后的图7所述，将把输入/输出(I/O)互连加入到晶片组件39。
插入基片30的主要特征在于铜电路上的多个孔36。插入基片30可以具有与晶片21大致相同的尺寸，并且与晶片21对齐，这样，孔36就和焊接区23排在一起。在孔36中必须存在足够量的铜以提供对焊料或导电粘合剂的充分连接。在孔36周围的圆形铜环或跨越孔36的铜带可以用于满足该要求。随后，通过粘合胶将插入基片30与弹性体层27粘合，并且随后使晶片组件39固化。这样，插入结构就与晶片对齐并粘结。
参照图6，焊膏层40通过插入基片30的孔36沉积。这可以通过参照上述弹性体层27沉积所述的相同方式用丝网或漏印板印刷处理来实现。插入基片基底32层经筛选，并且通过气动式括板将焊膏40沉积在孔36中，这样，就一次完成将焊膏40沉积在晶片上。随后，将晶片21焊料回流以便在晶片21上的焊接区23和插入基片层30中的铜金属电路34之间形成多个电气连接。焊膏也可以通过使用自动分配装置经插入基片的孔或通过焊料预制存放来沉积。或者，可以使用导电粘合剂代替焊膏来电气连接焊接区23和金属电路34。粘合剂沉积在孔36中，并随后固化以形成电气连接。还可选择用环氧树脂材料保护焊料连接。环氧树脂材料的施加也可以通过上述丝网或漏印板印刷处理来实现，并随后固化保护敷层。
下一步是在晶片上放置封装焊球。封装焊球作为用于封装的I/O互连，并且将用于把完成的IC封装紧固在最终使用的印刷电路板上。参照图7，焊球50通过预制焊球的机械移动安置在金属化的孔36上。或者，焊球50可以通过丝网或漏印板印刷焊膏来形成。随后，将焊料回流形成封装焊球。焊球50可以应用任何所需的图案类型，例如在整个表面上以均匀完整矩阵形式配制。
这里，因为晶片组件39含有完成的以矩阵形式配制的封装块，所以，可以在晶片组件39上执行电气测试。这就允许进行并行测试，这种测试可以在晶片级执行并能节省测试时间和成本。随后，将晶片组件39切割成块或单独成块以形成单独的小片尺寸BGA封装70、72。一种单独成块的普通技术是使用具有金刚石或树脂锯条的晶片锯。参照图8，随后，完成的BGA封装70可以用与已有BGA封装相同的方式安置在最终使用的印刷电路板上。本发明的BGA封装70具有与单个硅片相同的占用面积，因为不需要额外的空间来安置引线接合导线或更大的基片基底。通过这种方法，本发明的集成电路封装提供了更小封装尺寸和在晶片级封装便利性的优点。

Claims (14)

1、一种在晶片级形成的集成电路封装，其特征在于，包括：
具有面积和具有多个焊接区的硅片，所述焊接区配制在第一表面上，
覆盖硅片第一表面相当大部分的粘合剂层，而仍然保留所述多个焊接区暴露，
插入基片，放置在所述粘合剂层上并包括多个金属电路连线以及多个金属化孔，所述孔与所述硅片的多个焊接区对准，
用于电气连接所述插入基片多个金属化孔以及所述硅片上多个焊接区的装置，以及
在所述插入基片的多个金属化孔上形成的多个I/O互连。
2、如权利要求1所述的集成电路封装，其特征在于，所述多个I/O互连是在所述插入基片上形成的焊球。
3、如权利要求1所述的集成电路封装，其特征在于，所述用于电气连接所述多个金属化孔以及所述多个焊接区的装置是焊料。
4、如权利要求1所述的集成电路封装，其特征在于，所述用于电气连接所述多个金属化孔以及所述多个焊接区的装置是导电粘合剂。
5、如权利要求1所述的集成电路封装，其特征在于，所述插入基片具有与硅片面积相同大小的面积。
6、一种在晶片级上形成集成电路芯片封装的方法，其特征在于，所述方法包括：
配制硅晶片，所述晶片具有安置在其第一表面上的多个焊接区，
对所述多个焊接区重新金属化，
在所述晶片的第一表面上沉积粘合剂材料层，而仍然保持所述多个焊接区暴露，
将由介电材料和多个金属化连线组成的插入基片紧固在粘合剂材料层上以形成晶片组件，所述插入基片包括多个金属化孔，它们与所述多个焊接区对准，
在所述多个金属化孔和多个焊接区之间形成电气连接，
在所述插入基片表面上的多个金属化孔上附着多个I/O互连，以及
将所述晶片组件切割成多个单独的集成电路芯片封装。
7、如权利要求9所述的方法，其特征在于，所述将插入基片紧固在粘合剂材料层上的步骤进一步包括固化所述晶片组件。
8、如权利要求9所述的方法，其特征在于，所述多个I/O互连是多个焊球。
9、如权利要求11所述的方法，其特征在于，所述将多个I/O互连附着在多个金属化孔上的步骤包括：
在所述多个金属化孔上放置所述多个焊球，以及
回流所述多个焊球以形成多个互连。
10、如权利要求9所述的方法，其特征在于，所述使多个焊接区重新金属化的步骤包括：
在每个焊接区上沉积锌层，
在每个焊接区上的锌层顶部沉积无电镍电镀层，以及
在每个焊接区上的无电镍电镀层上沉积无电金电镀层。
11、如权利要求9所述的方法，其特征在于，所述在晶片第一表面上沉积粘合剂材料层的步骤是通过丝网印刷处理实现。
12、如权利要求9所述的方法，其特征在于，所述粘合剂材料层由硅酮弹性体制成。
13、如权利要求9所述的方法，其特征在于，所述在多个金属化孔和多个焊接区之间形成电气连接的步骤包括：
在所述金属化孔上沉积焊料层，以及
回流所述焊料层以形成电气连接。
14、如权利要求9所述的方法，其特征在于，所述在多个金属化孔和多个焊接区之间形成电气连接的步骤包括：
在所述金属化孔上沉积导电粘合剂层，以及
固化所述导电粘合剂层以形成电气连接。
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CN100416785C (zh) * 2004-10-08 2008-09-03 伊丕渥克斯股份有限公司 用于使用重新分配基板制造晶片层芯片尺寸封装的方法
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CN102709202A (zh) * 2011-03-25 2012-10-03 美国博通公司 一种集成电路封装及其组装方法
CN102709202B (zh) * 2011-03-25 2015-07-01 美国博通公司 一种集成电路封装及其组装方法
WO2017066930A1 (en) * 2015-10-21 2017-04-27 GM Global Technology Operations LLC Systems and methods for reinforced adhesive bonding using textured solder elements

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NO20022792D0 (no) 2002-06-12
MY135942A (en) 2008-07-31
KR20020059851A (ko) 2002-07-13
CA2392837A1 (en) 2001-06-21
TW490822B (en) 2002-06-11
JP2004537841A (ja) 2004-12-16
WO2001045167A2 (en) 2001-06-21
NO20022792L (no) 2002-06-12
CN1217410C (zh) 2005-08-31
US6388335B1 (en) 2002-05-14
US6413799B1 (en) 2002-07-02
WO2001045167A3 (en) 2002-05-23

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