CN1416590A - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN1416590A
CN1416590A CN01804746A CN01804746A CN1416590A CN 1416590 A CN1416590 A CN 1416590A CN 01804746 A CN01804746 A CN 01804746A CN 01804746 A CN01804746 A CN 01804746A CN 1416590 A CN1416590 A CN 1416590A
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layer
monocrystalline
semiconductor
semiconductor structure
oxide
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珈玛尔·拉丹尼
拉艾德兰斯·德鲁帕德
林迪·L·西尔特
科特·W·埃森贝瑟
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Motorola Solutions Inc
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Motorola Inc
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Abstract

通过首先在硅晶片(22)上生长出调节缓冲层(24)可以生长出覆盖较大硅晶片的高质量复合半导体材料外延层。调节缓冲层是单晶氧化物层，其中氧化硅非晶质分界层(28)将调节缓冲层与硅晶片分离开。非晶质分界层消除变形并且允许生长出高质量单晶氧化物调节缓冲层。调节缓冲层与底层硅晶片和覆盖的单晶复合半导体层(26)晶格匹配。通过非晶质分界层消除调节缓冲层和底层硅质基底之间的任何晶格失配。

Description

半导体结构
技术领域
本发明涉及半导体结构及其制造方法，更具体地是涉及复合半导体结构和包含单晶复合半导体材料的半导体结构的制造和使用。
背景技术
由于价格低廉的高质量单晶硅基底的实用性，绝大多数半导体分立器件和集成电路均是用硅制造的，起码是部分用硅制造的。其它半导体材料，例如所谓的复合半导体材料，具有某些物理特征，其中包含比硅更宽的带隙和/或更高的迁移率，或使这些材料对某些类型的半导体器件更加有利的直接带隙。不幸的是，复合半导体材料通常比硅更加昂贵并且不能象硅那样用于较大的晶片。对于最具实用性的复合半导体材料砷化镓(GaAs)，其所适用的晶片的直径最多只有大约150毫米(mm)。相反，硅晶片的直径可以高达大约300mm，并且普遍有200mm。150mm GaAs晶片通常比相应的硅晶片更加昂贵。采用其它复合半导体材料的晶片更不实用，并且比GaAs更加昂贵。
由于复合半导体材料具有诱人的特性并且复合半导体材料在成块使用时通常成本较高、实用性较低，多年来人们一直尝试在异质基底上生长出复合半导体材料薄膜。然而为了达到复合半导体材料的最优特性，期望得到具有高晶体质量的单晶膜。例如已经尝试在锗、硅和其它各种绝缘体上生长单晶复合半导体材料层。由于基质晶体和生长晶体之间的晶格失配导致所产生的复合半导体材料薄膜的晶体质量较低，这些尝试通常是不成功的。
发明内容
如果能够以较低成本得到面积较大的高质量单晶复合半导体材料薄膜，那么可以在这种低成本薄膜上、或者用这种材料在复合半导体材料体晶片上形成的外延膜上，制造各种半导体器件以得到有利的效果，其中上述低成本薄膜的成本低于在复合半导体材料体晶片上制造这种半导体器件的成本。另外，如果可以在诸如硅晶片的体晶片上实现高质量单晶复合半导体材料薄膜，则可以实现综合了硅和复合半导体材料的最优性质的集成器件结构。
因此，需要在另一种单晶材料上提供高质量单晶复合半导体膜的半导体结构，以及制造这种结构的方法。
附图说明
参照附图中的例子图解本发明，但这些例子不对本发明进行限定，图中用类似的附图标记表示类似的元件，其中：
图1、2、4和5是示意性图解基于本发明各种实施例的器件结构的剖视图；
图3以图表形式图解了可达到的最大薄膜厚度和基质晶体与生长晶体覆层之间的晶格失配之间的关系；
图6是通信器件的一部分的模块图；
图7-11是集成电路的各个部分的剖视图，所述集成电路包含复合半导体部分，双极部分和MOS部分；而
图12-18是另一种集成电路的各个部分的剖视图，所述集成电路包含半导体激光器和MOS晶体管。
本领域技术人员会理解，对图中元件的图解注重简单和清晰，不必按比例绘出。例如，相对于其它元件，可以夸张图中某些元件的尺寸以利于理解本发明的实施例。
具体实施方式
图1是示意性图解基于本发明一个实施例的半导体结构20的一部分的剖视图。半导体结构20包含单晶基底22，包括单晶材料的调节缓冲层24，和单晶复合半导体材料层26。在本文中，规定术语“单晶”具有半导体行业内通用的含义。该术语所指的是单晶或基本上单晶的材料，并且还包含半导体行业常用的、缺陷数量相对较少的材料，所述缺陷可以是在采用硅、锗或硅与锗的混合物的基底中，以及这种材料形成的外延层中常见的错位之类的缺陷。
根据本发明的一个实施例，结构20还包含位于基底22和调节缓冲层24之间的非晶质中间层28。结构20也可以包含调节缓冲层和复合半导体层26之间的模板层30。如下所述，模板层有助于启动复合半导体层在调节缓冲层上的生长。非晶质中间层有助于消除调节缓冲层的变形并借此帮助高晶体质量调节缓冲层的生长。
根据本发明的一个实施例，基底22是最好具有较大直径的单晶半导体晶片。晶片可以由周期表IV族材料组成，最好是由IVA族材料组成。IV族半导体材料的例子包含硅、锗、硅锗混合物、硅碳混合物、硅锗碳混合物等等。基底22最好是含有硅或锗的晶片，如果是半导体行业使用的高质量单晶硅晶片则会更好。调节缓冲层24最好是在底层基底上外延生长的单晶氧化或氮化材料。根据本发明的一个实施例，在层24生长期间，在基底22上生长出非晶质中间层28，并且非晶质中间层28位于基底22和通过氧化基底22生长的调节缓冲层之间的分界面上。非晶质中间层被用来消除基底和缓冲层之间的晶格常数差异在单晶调节缓冲层中造成的变形。这里，晶格常数表示在表面平面内测量的晶胞原子之间的距离。如果非晶质中间层不消除这种变形，则变形会在调节缓冲层的晶体结构中导致缺陷。调节缓冲层晶体结构中的缺陷会使得难以在单晶复合半导体层26中实现高质量晶体结构。
调节缓冲层24最好是为保证其与底层基底和覆盖的复合半导体材料之间的晶体相容性而选择的单晶氧化或氮化材料。例如，这种材料可以是具有与基底和后来涂敷的半导体材料匹配的晶格结构的氧化物或氮化物。适用于调节缓冲层的材料包含诸如碱土金属的钛酸盐、碱土金属的锆酸盐、碱土金属的铪酸盐、碱土金属的钽酸盐、碱土金属的钌酸盐、碱土金属的铌酸盐、碱土金属的钒酸盐、锡基钙钛矿结构碱土金属、铝酸镧、镧钪氧化物和氧化钆之类的金属氧化物。另外，诸如氮化镓、氮化铝和氮化硼之类的各种氮化物也可以用于调节缓冲层。除了少部分材料，例如钌酸锶是导体之外，大部分这种材料均是绝缘体。这种材料通常是金属氧化物或金属氮化物，更具体地，这种金属氧化物或氮化物通常包含至少两种不同的金属元素。在某些具体应用中，金属氧化物或氮化物可以包含三种或更多种不同的金属元素。
非晶质分界层28最好是通过氧化基底22的表面形成的氧化物，如果由氧化硅组成则会更好。层28的厚度足够消除基底22和调节缓冲层24的晶格常数之间的失配造成的变形。层28的厚度通常在大约0.5-5nm的范围内。
根据具体半导体结构的需要，可以从IIIA族和VA族元素(III-V族元素的半导体复合物)，混合III-V族元素的复合物，II族(A或B)和VIA族元素(II-VI族元素的半导体复合物)和混合II-VI族元素的复合物中选择任何一种作为层26的复合半导体材料。例如砷化镓(GaAs)、镓铟的砷化物(GaInAs)、镓铝的砷化物(GaAlAs)、磷化铟(InP)、硫化镉(CdS)、镉汞的碲化物(CdHgTe)、硒化锌(ZnSe)、锌硫的硒化物(ZnSSe)等等。适当的模板材料在选定的附着点被化学粘结到调节缓冲层24的表面上，并且为后续复合半导体层26外延生长的晶核形成提供附着点。下面讨论模板30的适当材料。
图2是示意性图解基于本发明另一个实施例的半导体结构40的一部分的剖视图。除了在调节缓冲层24和单晶复合半导体材料层26之间增加附加缓冲层32之外，结构40类似于前面描述的半导体结构20。具体地，附加缓冲层位于模板层30和复合半导体材料覆层之间。当调节缓冲层的晶格常数不能与单晶复合半导体材料覆层的晶格常数充分匹配时，由半导体或复合半导体材料组成的附加缓冲层被用来提供晶格校正。
下面的非限制性图解例根据本发明的各种可选实施例说明了可用于结构20和结构40的材料的各种组合。这些例子仅仅是图解性的，并不表明本发明受这些图解性例子的限定。
例子1
根据本发明的一个实施例，单晶基底22是具有(100)取向的硅质基底。硅质基底可以是通常在制造直径大约为200-300mm的互补金属氧化物半导体(CMOS)集成电路时使用的硅质基底。根据本发明的这个实施例，调节缓冲层24是SrzBa1-zTiO3组成的单晶层，其中z的范围为0到1，而非晶质中间层是在硅质基底和调节缓冲层之间的分界面上形成的氧化硅(SiOx)层。选择z的数值以获得一或多个与后来形成的层26的对应晶格常数紧密匹配的晶格常数。调节缓冲层可以具有大约2到100纳米(nm)的厚度，并且最好具有大约10nm的厚度。为了获得期望的电气和光学性质，通常希望调节缓冲层的厚度足够将复合半导体层与基底隔离开。厚度超过100nm通常会带来一些额外的好处，但不必要地提高了成本；然而根据需要也可以制造厚度更高的层。氧化硅构成的非晶质中间层可以具有大约0.5-5nm的厚度，并且最好具有大约1.5-2.5nm的厚度。
根据本发明的这个实施例，复合半导体材料层26由厚度大约为1nm到100微米(μm)，并且最好大约是0.5μm到10μm的砷化镓(GaAs)或铝镓的砷化物(AlGaAs)组成。层的厚度通常取决于正在制备的层的用途。为了利于单晶氧化物上的砷化镓或铝镓的砷化物的外延生长，通过覆盖氧化层来形成模板层。模板层最好是1-10个由Ti-As、Sr-O-As、Sr-Ga-O或Sr-Al-O组成的单层。在优选例中，1-2个由Ti-As或Sr-Ga-O组成的单层成功生长出GaAs层。
例子2
根据本发明的另一个实施例，单晶基底22是如上所述的硅质基底。调节缓冲层是由锶或钡的锆酸盐或铪酸盐组成的单晶氧化物，所述锶或钡的锆酸盐或铪酸盐具有立方晶相或斜方晶相，其中在硅质基底和调节缓冲层之间的分界面上形成氧化硅非晶质中间层。调节缓冲层可以具有大约2-100nm，并且最好是至少5nm的厚度，以保证具有足够的晶体和表面质量，并且调节缓冲层由单晶SrZrO3、BaZrO3、SrHfO3、BaSnO3或BaHfO3组成。例如，BaZrO3的单晶氧化层在大约700摄氏度的温度下可以生长。所产生的晶体氧化物的晶格结构相对基底硅晶格结构旋转45度。
由这些锆酸盐或铪酸盐材料组成的调节缓冲层适于磷化铟(InP)晶系中复合半导体材料的生长。复合半导体材料可以是厚度大约为1.0nm到10μm的磷化铟(InP)或铟镓的砷化物(InGaAs)。这种结构的适当模板是1-10个由锆-砷(Zr-As)、锆-磷(Zr-P)、铪-砷(Hf-As)、铪-磷(Hf-P)、锶-氧-砷(Sr-O-As)、锶-氧-磷(Sr-O-P)、钡-氧-砷(Ba-O-As)、铟-锶-氧(In-Sr-O)或钡-氧-磷(Ba-O-P)组成的单层，并且最好是1-2个由这种材料中的一种组成的单层。例如，对于锆酸钡调节缓冲层，用1-2个由锆组成的单层终结表面，所述单层之上沉积1-2个由砷组成的单层以便形成Zr-As模板。接着在模板层上生长出磷化铟晶系的复合半导体材料单晶层。所产生的复合半导体材料的晶格结构相对于调节缓冲层晶格结构旋转45度，并且相对(100)InP的晶格失配小于2.5％，最好小于大约1.0％。
例子3
根据本发明的另一个实施例，提供适于覆盖硅质基底、由II-VI族元素材料组成的外延膜的生长的结构。该基底最好是如上所述的硅晶片。适当的调节缓冲层材料是SrxBa1-xTiO3，其中x的范围为0到1，该调节缓冲层具有大约2-100nm的厚度，并且最好具有大约5-15nm的厚度。II-VI族复合半导体材料可以是硒化锌(ZnSe)或锌硫的硒化物(ZnSSe)。这种材料系的适当模板包含1-10个由锌-氧(Zn-O)组成的单层，所述单层上覆盖1-2个由过量的锌组成的单层，所述锌层上覆盖锌的表面硒化物。可选地，模板可以是其上覆盖有ZnSeS的锶-硫(Sr-S)。
例子4
本发明的这个实施例是图2图解的结构40的例子。基底22，单晶氧化层24和单晶复合半导体材料层26类似于例子1中描述的对应部分。另外，附加缓冲层32被用来消除调节缓冲层和单晶半导体材料的晶格之间的失配可能导致的任何变形。缓冲层32可以是镓的砷磷化物(GaAsxP1-x)或铟镓的磷化物(InyGa1-yp)组成的变形校正超晶格。在镓的砷磷化物超晶格中，x的数值的范围为0到1，并且在铟镓的磷化物超晶格中，y的数值的范围为0到1。通过根据需要改变x或y的数值，在超晶格中自底向上改变晶格常数以便在底层氧化物和覆盖的复合半导体材料的晶格常数之间建立匹配。超晶格可以具有大约50到500nm厚度，并且最好具有大约20-100nm的厚度。这个结构的模板可以和例子1中描述的模板相同。可选地，缓冲层可以是具有大约1到50nm的厚度，并且最好具有大约2-20nm的厚度的单晶锗层。在使用锗缓冲层的情况下，可以使用由厚度为大约一个单层的锗-锶(Ge-Sr)或锗-钛(Ge-Ti)组成的模板层。形成的氧化层被覆盖上锶单层或钛单层以充当用于单晶锗的后续沉积的晶核形成区。
锶或钛单层提供可以粘结由锗组成的第一个单层的晶核形成区。
例子5
这个例子还图解了在图2的结构40中使用的材料。基底材料22，调节缓冲层24，单晶复合半导体材料层26和模板层30可以和例子2中描述的对应部分相同。另外，缓冲层32被插到调节缓冲层和单晶复合半导体材料覆层之间。缓冲层，即另一种单晶半导体材料，可以是由铟镓的砷化物(InGaAs)组成的递变层，其中铟的成分从0变化到大约47％。缓冲层最好具有大约10-30nm的厚度。缓冲层的这种从GaAs到InGaAs的成分变化被用来在底层单晶氧化物材料和单晶复合半导体材料覆层之间提供晶格匹配。在调节缓冲层24和单晶复合半导体材料层26之间存在晶格失配的情况下这种缓冲层尤其有利。
再次参照图1和2，基底22是诸如单晶硅基底之类的单晶基底。  单晶基底的晶体结构的特征在于晶格常数和晶格取向。类似地，调节缓冲层24也是单晶材料，这种单晶材料的晶格的特征在于晶格常数和晶体取向。调节缓冲层和单晶基底的晶格常数必须非常匹配，或者可选地，必须使得在一个晶体取向相对于另一个晶体取向发生旋转时达到晶格常数的基本匹配。在本文中，术语“基本相等”和“基本匹配”是指晶格常数之间的相似程度足够允许在底层上生长出高质量的晶体层。
图3以图表形式将生长的高晶体质量晶体层的可达到厚度图解成关于基质晶体和生长晶体晶格常数之间的失配的函数。曲线42图解了高晶体质量材料的边界。曲线42右边的区域代表会具有多晶性质的层。在没有晶格失配的情况下，理论上在基质晶体上能够生长出无限厚的高质量外延层。随着晶格常数失配的增加，高质量晶体层的可达到厚度快速降低。例如，在基质晶体和生长层晶格常数之间的失配超过大约2％的情况下，单晶外延层的厚度不能超过大约20nm。
根据本发明的一个实施例，基底22是具有(100)或(111)取向的单晶硅晶片，而调节缓冲层24是由锶钡的钛酸盐组成的层。通过使钛酸盐材料的晶体取向相对于硅质基底晶片的晶体取向旋转45度，达到这两种材料的晶格常数之间的基本匹配。非晶质分界层24的结构中的内含物被用来降低基质硅晶片和生长钛酸盐层的晶格常数之间的任何失配可能在钛酸盐单晶层中导致的变形，在这个例子中所述非晶质分界层24为氧化硅层。结果，根据本发明的一个实施例，可得到高质量、厚度高的单晶钛酸盐层。
仍然参照图1和2，层26由外延生长的单晶复合半导体材料组成，而且晶体材料的特征在于晶体晶格常数和晶体取向。为了在这个外延生长层中达到高晶体质量，调节缓冲层也必须具有高晶体质量。另外，为了在层26中达到高晶体质量，期望在基质晶体和生长晶体的晶体晶格常数之间达到基本匹配，这里所述的基质晶体是单晶调节缓冲层。在正确选择材料的情况下，通过使生长晶体的晶体取向相对于基质晶体的晶体取向发生旋转来达到晶格常数的这种基本匹配。如果生长晶体是砷化镓、铝镓的砷化物、硒化锌或锌硫的硒化物，并且调节缓冲层是单晶SrxBa1-xTiO3，则达到两种材料的晶体晶格常数的基本匹配，其中生长层的晶体取向相对于基质单晶氧化物的取向旋转45度。类似地，如果基质材料是锶或钡的锆酸盐、锶或钡的铪酸盐或钡锡氧化物，并且复合半导体层是磷化铟、镓铟的砷化物或铝铟的砷化物，则通过使生长晶体层的取向相对于基质氧化晶体的取向旋转45度可以达到晶体晶格常数的基本匹配。在某些情况下，基质氧化物和生长的复合半导体层之间的晶体半导体缓冲层可用于降低较小的晶格常数差异可能在生长的单晶复合半导体层中产生的变形。因而可以在生长的单晶复合半导体层中达到较好的晶体质量。
下面的例子图解了基于本发明一个实施例、用于制造如图1和2所示的半导体结构的方法。该方法从提供含有硅或锗的单晶半导体基底开始。根据本发明的优选实施例，半导体基底是具有(100)取向的硅晶片。基底最好具有轴向取向，或者最多偏离轴向0.5度。半导体基底的至少一部分具有裸露表面，尽管基底的其它部分可以包括其它结构。在本文中，术语“裸露”是指已经对基底部分的表面部分进行了清洁处理，从而清除了任何氧化物、杂质或其它异物。众所周知，裸露的硅的化学性质很活跃，并且很容易形成原生氧化物。术语“裸露”被用来涵盖这种原生氧化物。也可以有意在半导体基底上生长薄氧化硅，尽管这种生长的氧化物对于本发明的方法不是必要的。为了外延生长覆盖单晶基底的单晶氧化层，必须首先清除原生氧化层以便暴露底层基底的晶体结构。最好通过分子束外延(MBE)实现下面的方法。通过首先在MBE装置上沉积薄锶层可以清除原生氧化物。接着把基底加热到大约750摄氏度的温度，使锶与原生氧化硅层发生反应。锶被用来除去氧化硅以留下无氧化硅表面。所得到的具有有序2×1结构的表面含有锶，氧和硅。有序2×1结构形成用于单晶氧化物覆层的有序生长的模板。该模板提供必要的化学和物理性质以便对覆层的晶体生长起形成晶核的作用。
根据本发明的可选实施例，通过使用MBE以较低的温度在基底表面上沉积氧化锶，并且后来将结构加热到大约750度的温度，可以转化原生氧化硅，并且可以为单晶氧化层的生长制备基底表面。在这种温度上，在氧化锶和原生氧化硅之间发生固态反应，导致除去原生氧化硅并且留下有序2×1结构，该结构在基底表面上保留了锶，氧和硅。于是，形成了用于有序单晶氧化层的后续生长的模板。
根据本发明的一个实施例，在从基底表面除去氧化硅之后，基底被冷却到范围大约为400-600度的温度，并且通过分子束外延在模板层上生长出钛酸锶层。通过打开MBE装置中的快门暴露锶，钛和氧源来启动MBE过程。锶和钛的比率接近1∶1。氧分压被初始设定为最小数值，以便按照大约0.3-0.5纳米每分钟的生长速率生长出化学计量的钛酸锶。在启动钛酸锶的生长之后，提高氧分压使之超过初始的最小数值。氧的过压导致在底层基底和生长的钛酸锶层之间的分界面上生长出非晶质氧化硅层。氧通过生长的钛酸锶层扩散到分界面导致氧化硅层的生长，其中在分界面内氧与底层基底的表面上的硅发生反应。钛酸锶生长成有序单晶，这种有序单晶具有相对于底层基底的有序2×1晶体结构旋转45度的晶体取向。在非晶质氧化硅中间层中消除了硅质基底和生长晶体的晶格常数之间的微小失配可能在钛酸锶层中产生的变形。
在钛酸锶层生长到期望厚度之后，单晶钛酸锶被模板层覆盖，该模板层利于所需的复合半导体材料外延层的后续生长。对于砷化镓层的后续生长，通过完成1-2个钛单层、1-2个钛-氧单层或1-2个锶-氧单层的生长可以覆盖通过MBE方法生长的钛酸锶单晶层。在形成这种覆盖层之后，沉积砷以形成Ti-As粘结、Ti-O-As粘结或Sr-O-As粘结。所有这些均构成了用于砷化镓单晶层的沉积和形成的适当模板。在形成模板之后，引入镓以便与砷发生反应并形成砷化镓。可选地，可以在覆盖层上沉积镓以形成Sr-O-Ga粘结，并且引入砷、使之与镓反应以形成GaAs。
通过上述方法并且增加附加缓冲层沉积步骤可以形成图2中的结构。在沉积单晶复合半导体层之前形成覆盖模板层的缓冲层。如果缓冲层是复合半导体超晶格，则通过在上述模板上执行MBE方法可以沉积这种超晶格。如果缓冲层是锗层，则把上述方法修改成用最终的锶或钛层覆盖钛酸锶单晶层，并且接着沉积锗以便与锶或钛发生反应。接着可以直接在这个模板上沉积锗缓冲层。
上述方法图解了通过分子束外延形成包含硅质基底，单晶钛酸锶调节缓冲层和单晶砷化镓复合半导体层的半导体结构的方法。也可以通过化学汽相沉积(CVD)、金属有机化学汽相沉积(MOCVD)、迁移增强外延(MEE)、原子层外延(ALE)等方法实现该方法。此外，通过类似方法也可以生长出诸如碱土金属的钛酸盐、锆酸盐、铪酸盐、钽酸盐、钒酸盐、钌酸盐和铌酸盐、锡基钙钛矿结构碱土金属、铝酸镧、镧钪氧化物和氧化钆之类的其它单晶调节缓冲层。此外，通过诸如MEE之类的类似方法，可以沉积其它III-V族和II-VI族单晶复合半导体层以覆盖单晶氧化物调节缓冲层。
复合半导体材料和单晶氧化物调节缓冲层的各种变体均使用适当模板启动复合半导体层的生长。例如，如果调节缓冲层是碱土金属的锆酸盐，则可以用薄锆层覆盖氧化物。锆沉积物上面可以沉积砷或磷以便和锆发生反应，从而以反应产物作为先驱体沉积铟镓的砷化物、铟铝的砷化物或磷化铟。类似地，如果单晶氧化物调节缓冲层是碱土金属的铪酸盐，则可以用薄铪层覆盖氧化层。铪沉积物上面可以沉积砷或磷以便和铪发生反应，从而以反应产物作为先驱体沉积铟镓的砷化物层、铟铝的砷化物层或磷化铟层。类似地，可以用锶层或锶氧层覆盖钛酸锶，并且可以用钡层或钡氧层覆盖钛酸钡。所有这些沉积物上面均可以沉积砷或磷以便和覆盖材料发生反应，从而形成用于复合半导体材料层的沉积的模板，所述复合半导体材料层含有铟镓的砷化物、铟铝的砷化物或磷化铟。
图4是示意性图解基于本发明另一个实施例的器件结构50的剖视图。器件结构50包含单晶半导体基底52，单晶半导体基底52最好是单晶硅晶片。单晶半导体基底52包含两个区域53和54。在区域53中形成通常由虚线56表示的电半导体元件。电元件56可以是电阻器、电容器、诸如二极管或晶体管之类的有源半导体元件、或诸如CMOS集成电路之类的集成电路。例如，电半导体元件56可以是被用来执行数字信号处理或非常适合硅集成电路的其它功能的CMOS集成电路。通过半导体行业内众所周知并且广泛应用的传统半导体工艺可以形成区域53中的电半导体元件。诸如二氧化硅层等等的绝缘材料层58可以覆盖电半导体元件56。
从区域54的表面上清除绝缘材料58，以及当加工区域53内的半导体元件56时可能已经形成或沉积的任何其他层，以便在区域54上提供裸露硅表面。众所周知，裸露硅表面的化学性质非常活跃，并且可以在裸表面上迅速形成原生氧化硅层。钡层或钡氧层被沉积在区域54表面的原生氧化物层上，并且与氧化表面反应以形成第一模板层(未示出)。根据本发明的一个实施例，通过分子束外延方法形成单晶氧化层60以覆盖模板层。含有钡，钛和氧的反应物被沉积在模板层上以形成单晶氧化层。最初在沉积期间，使氧分压保持接近最低水平，所述最低水平是与钡和钛发生完全反应以形成单晶钛酸钡层60所需的最低水平。接着提高氧分压，以便提供氧过压并且允许氧扩散穿过生长的单晶氧化层。  扩散穿过钛酸钡的氧与区域54的表面上的硅发生反应，从而在第二区域和硅质基底与单晶氧化物之间的分界面上形成氧化硅非晶质层62。
根据本发明的一个实施例，通过沉积第二模板层64终止沉积单晶氧化层60的步骤，所述第二模板层64可以是1-10个由钛、钡、钡氧或钛氧组成的单层。接着通过分子束外延方法沉积单晶复合半导体材料层66以覆盖第二模板层。通过在该模板上沉积砷层以启动层66的沉积。在这个启动步骤之后沉积镓和砷以形成单晶砷化镓。可选地，在上述例子中可以用锶代替钡。
根据本发明的另一个实施例，在复合半导体层66中形成通常用虚线68表示的半导体元件。通过在制造砷化镓或其它III-V复合半导体材料器件时通常使用的加工步骤可以形成半导体元件68。半导体元件68可以是任何有源或无源元件，并且最好是半导体激光器、发光二极管、光电检测器、异质结双极晶体管(HBT)、高频MESFET或其它利用复合半导体材料的物理性质的元件。可以形成如连线70所示的金属导体以便电耦合器件68和器件56，于是实现了包含至少一个在硅质基底上形成的元件和一个在单晶复合半导体材料层中形成的器件的集成器件。尽管这里将结构50描述成在硅质基底52上形成并且具有钡(或锶)的钛酸盐层60和砷化镓层66的结构，然而也可以使用本说明书中其它地方提到的其它基底、单晶氧化层和其它复合半导体层制造类似的器件。
图5图解了基于本发明另一个实施例的半导体结构72。结构72包含诸如单晶硅晶片之类、含有区域75和区域76的单晶半导体基底74。使用半导体行业常用的传统硅器件加工技术在区域75中形成如虚线78所示的电元件。使用与上述类似的加工步骤形成单晶氧化层80和中间非晶质氧化硅层82以覆盖基底74的区域76。形成模板层84和后来的单晶半导体层86以覆盖单晶氧化层80。根据本发明的另一个实施例，通过与被用来形成层80的加工步骤类似的加工步骤形成额外的单晶氧化层88以覆盖层86，并且通过与被用来形成层86的加工步骤类似的加工步骤形成额外的单晶氧化层90以覆盖层88。根据本发明的一个实施例，利用复合半导体材料形成层86和90中的至少一个。
至少部分地在单晶半导体层86中形成通常由虚线92表示的半导体元件。根据本发明的一个实施例，半导体元件92可以包含场效应晶体管，该场效应晶体管具有部分通过单晶氧化层88形成的栅极介质。另外，单晶半导体层92可用于实现该场效应晶体管的栅电极。根据本发明的一个实施例，利用III-V族复合物形成单晶半导体层86，并且半导体元件92是利用III-V族元件材料的高迁移率特性的射频放大器。根据本发明的另一个实施例，如连线94所示的电气互连将元件78和元件92互连起来。于是，结构72集成了利用两种单晶半导体材料的独特性质的元件。
在图6-18中通过更加具体的例子图解了其它集成电路和系统。图6是图解通信器件100的一部分的简化模块图，通信器件100具有信号收发装置101，集成电路102，输出单元103和输入单元104。信号收发装置的例子包含天线，调制解调器或任何其他可以被用来针对外部单元接收或发送信息或数据的装置。这里，收发被用来表示能够针对通信器件单纯接收、单纯发送或接收并发送信号的信号收发装置。输出单元103可以包含显示器、监视器、扬声器等。输入单元可以包含话筒、键盘等。注意，在可选实施例中，输出单元103和输入单元104可以被诸如存储器等等的分立单元替代。存储器可以包含随机访问存储器或非易失存储器，例如硬盘、快闪存储器卡或模块等等。
集成电路通常是至少两个电路元件(例如晶体管、二极管、电阻器、电容器等等)的组合，所述电路元件在连续基底中互不可分。集成电路102包含复合半导体部分1022，双极部分1024和MOS部分1026。复合半导体部分1022包含至少部分地在复合半导体材料内部形成的电元件。复合半导体部分1022内部的晶体管和其它电元件能够处理至少接近0.8GHz的无线频率上的信号。在其它实施例中，信号可以具有更低或更高的频率。例如，某些诸如铟镓的砷化物的材料能够处理接近27GHz的频率上的信号。
复合半导体部分1022还包含双工器10222，射频-基带转换器10224(解调装置或解调电路)，基带-射频转换器10226(调制装置或调制电路)，功率放大器10228和隔离器10229。双极部分1024和MOS部分1026通常由IV族半导电材料构成。双极部分1024包含接收放大器10242，模数转换器10244，数模转换器10246和发送放大器10248。MOS部分1026包含数字信号处理装置10262。这种装置的例子包含市场上通常可以购买到的任何DSP芯核，例如摩托罗拉DSP 566xx(伊利诺伊州斯康伯格市(Schaumburg)的摩托罗拉公司制造)和德州仪器TMS 320C54x(德克萨斯州达拉斯市的德州仪器公司制造)。这个数字信号处理装置10262通常包含互补MOS(CMOS)晶体管和模数与数模转换器。显然，在集成电路102中还存在其它电元件。
在一个操作模式中，通信器件100从天线接收信号，该天线是信号收发装置101的一部分。信号穿过双工器10227到达射频-基带转换器10224。模拟数据或其它信息被接收放大器10224放大并且被发送到数字信号处理装置10262。在数字信号处理装置10262处理信息或其它数据之后，经过处理的信息或其它数据被发送到输出单元103。如果通信器件是寻呼机，输出单元可以是显示器。如果通信器件是蜂窝电话，输出单元103可以包含扬声器、显示器或二者均被包含。
在相反方向上可以通过通信器件100发送数据或其它信息。数据或其它信息会通过输入单元104进入。在蜂窝电话中，输入单元可以包含话筒或小键盘。接着使用数字信号处理装置10262处理信息或其它数据。在处理之后，使用数模转换器10246转换信号。转换的信号被发送放大器10248放大。放大的信号被基带-射频转换器10226调制并且被功率放大器10228放大。放大的RF信号穿过隔离器10229和双工器10222到达天线。
通信器件100的现有技术实施例具有至少两个分立的集成电路：一个用于复合半导体部分1022，另一个用于MOS部分1026。双极部分1024可以和MOS部分1026位于相同的集成电路上，也可以位于不同的集成电路上。在本发明的实施例中，现在可以在单独的集成电路内构成所有三个部分。由于所有晶体管均可以集成到单独的集成电路内，通信器件可以很大程度地实现小型化并且允许通信器件具有更高的移动性。
现在描述构成图7-11中示出的集成电路102的示例性部分的方法。在图7中，提供p-型掺杂单晶硅基底110，所述的单晶硅基底110具有复合半导体部分1022，双极部分1024和MOS部分1026。在双极部分内部，对单晶硅基底进行掺杂以形成N+埋层1102。接着在埋层1102和基底110上形成具有少量p-型掺杂的外延单晶硅层1104。接着执行掺杂步骤以便在N+埋层1102上产生具有少量n-型掺杂的漂移区1117。掺杂步骤将双极区1024区段内具有少量p-型掺杂的外延层转换成具有少量n-型掺杂的单晶硅区。接着在双极部分1024和MOS部分1026之间形成场隔离区1106。在MOS部分1026内部的外延层1104的一部分上形成栅极介质层1110，接着在栅极介质层1110上形成栅电极1112。沿着栅电极1112和栅极介质层1110的垂直侧形成侧壁隔层1115。
p-型掺杂剂被引入漂移区1117以形成活性或本征基区1114。接着在双极部分1024内部形成n-型深集极区1108以便允许电连接到埋层1102。进行有选择的n-型掺杂以形成N+掺杂区1116和发射区1120。沿着栅电极1112的相邻侧在层1104内部形成N+掺杂区1116，N+掺杂区1116是MOS晶体管的源极区、漏极区或源/漏极区。N+掺杂区1116和发射区1120具有至少1E19原子每立方厘米的掺杂浓度以便允许形成电阻性接点。形成p-型掺杂区以便产生无活性或非本征基区1118，所述无活性或非本征基区1118是P+掺杂区(掺杂浓度至少为1E19原子每立方厘米)。
在所述实施例中，已经进行了若干加工步骤，但是没有对其进行图解或详细描述，例如阱区、阈值调节植入物、穿过预防植入物的沟道、穿过预防植入物的场以及各种掩模层的形成。在所述的方法中，到此为止均是使用传统步骤进行器件构造。如图所示，在MOS区1026内部已经形成标准N-沟道MOS晶体管，并且在双极部分1024内部已经形成垂直NPN双极晶体管。至此，还没有在复合半导体部分1022内部形成电路。
现在从复合半导体部分1022的表面清除所有在集成电路的双极和MOS部分的加工期间形成的层。于是为这个部分的后续加工提供了裸露硅表面，例如按照前面提出的方式。
接着如图8所示，在基底110上形成调节缓冲层124。调节缓冲层会在部分1022中已经制备(即具有适当的模板层)的裸露硅表面上形成单晶层。然而层124中在部分1024和1026上形成的部分可能是多晶或非晶质层，其原因是所述部分是在非单晶材料上形成的，因此没有为单晶生长形成晶核。调节缓冲层124通常是单晶金属氧化物或氮化物层，并且通常具有范围为接近2-100nm的厚度。在一个具体实施例中，调节缓冲层的厚度范围大约为5-15nm。在形成调节缓冲层期间，在集成电路102最上面的硅表面上形成非晶质中间层122。这个非晶质中间层122通常含有氧化硅，并且厚度范围接近1-5nm。在一个具体实施例中，调节缓冲层的厚度接近2nm。在形成调节缓冲层124和非晶质中间层122之后，接着形成模板层126，模板层126的厚度范围接近1到10个材料单层。在一个具体实施例中，所述材料包含钛-砷、锶-氧-砷或其它与参照图1-5描述的材料相类似的材料。
接着如图9所示，外延生长出单晶复合半导体层132以覆盖调节缓冲层124的单晶部分。层132中在层124的非单晶部分上生长出的部分可以是多晶或非晶质层。可以通过若干种方法形成单晶复合半导体层，单晶复合半导体层通常含有诸如砷化镓、铝镓的砷化物、磷化铟或上述其它复合半导体材料之类的材料。该层的厚度范围接近1-5,000nm，并且最好为100-500nm。在这个具体实施例中，模板层内部的各个元件也出现在调节缓冲层124、单晶复合半导体材料132或调节缓冲层124与单晶复合半导体材料132中。因此，模板层126与其两个直接相邻层之间的轮廓在加工期间消失。因此，当拍摄透射电子显微镜(TEM)照片时，可以看见调节缓冲层124和单晶复合半导体层132之间的分界面。
此时，如图10所示，从覆盖双极部分1024和MOS部分1026的部分中清除复合半导体层132和调节缓冲层124的区段。在清除上述区段之后，在基底110上形成绝缘层142。绝缘层142可以含有若干种诸如氧化物、氮化物、氮氧化物、低介电常数电介质等等的材料。这里，低介电常数电介质是介电常数不高于大约3.5的材料。在沉积绝缘层142之后，接着对绝缘层142进行抛光以清除绝缘层142中覆盖单晶复合半导体层132的部分。
接着在单晶复合半导体部分1022内部形成晶体管144。接着在单晶复合半导体层132上形成栅电极148。接着在单晶复合半导体层132内部形成掺杂区146。在这个实施例中，晶体管144是金属半导体场效果晶体管(MESFET)。如果MESFET是n-型MESFET，也对掺杂区146和单晶复合半导体层132进行n-型掺杂。如果要形成p-型MESFET，则掺杂区146和单晶复合半导体层132会具有相反的掺杂类型。重度掺杂(N+)区146允许和单晶复合半导体层132进行电阻性接点。此时形成了集成电路内部的有源器件。这个具体实施例含有n-型MESFET，垂直NPN双极晶体管和平面N-沟道MOS晶体管。可以使用许多其它类型的晶体管，其中包含P-沟道MOS晶体管、p-型垂直双极晶体管、p-型MESFET以及垂直和平面晶体管的组合。并且在一个或多个部分1022，1024和1026中可以形成其它电元件，例如电阻器、电容器、二极管等等。
如图11所示，继续加工以形成基本上完整的集成电路102。在基底110上形成绝缘层152。绝缘层152可以包含图11中未示出的阻蚀或阻抛光区。接着在第一绝缘层152上形成第二绝缘层154。清除层154，152，142，124和122的部分以形成接点开口(contact opening)，将在接点开口中互连各个器件。在绝缘层154内部形成互连沟道以便在接点之间提供侧面连接。如图11所示，互连1562把部分1022内部的n-型MESFET的源极或漏极区连接到双极部分1024内部的NPN晶体管的深集极区1108。NPN晶体管的发射区1120被连接到MOS部分1026内部的N-沟道MOS晶体管的一个掺杂区1116。另一个掺杂区1116被电连接到图中未示出的集成电路其它部分。
在互连1562，1564和1566以及绝缘层154上形成钝化层156。如图所示，建立针对晶体管的其它电连接，并且建立针对集成电路102中未示出的其它电气或电子元件的电连接。此外，根据需要可以形成额外的绝缘层和互连以便在集成电路102内部的各种元件之间形成适当互连。
根据前面实施例可以发现，复合半导体和IV族半导体材料的有源器件可以被集成到单独的集成电路中。由于把双极晶体管和MOS晶体管集成到相同集成电路内有一定难度，可以把双极部分内的某些元件转移到复合半导体部分1022或MOS部分1024中。更具体地说，回到参照图6描述的实施例，放大器10248和10242可以被转移到复合半导体部分1022中，转换器10244和10246可以转移到MOS部分1026中。因此，可以不再需要完全用于制造双极晶体管的特殊制造步骤。因此，集成电路中只有复合半导体部分和MOS部分。
在另一个实施例中，可以构成集成电路，使得该集成电路在复合半导体部分内包含光学激光器，并且包含光学互连(波导)，所述光学互连连接到相同集成电路的IV族半导体区域内的MOS晶体管。图12-18图解了一个实施例。
图12是图解包含单晶硅晶片161的集成电路160的一部分的剖视图。与前面描述的类似，已经在晶片161上形成非晶质中间层162和调节缓冲层164。在这个具体实施例中，首先形成光学激光器所需的各个层，接着形成MOS晶体管所需的各个层。在图12中，下部镜层(mirrorlayer)166包含交替的复合半导体材料层。例如，光学激光器内部的第一、第三和第五薄膜可以包含诸如砷化镓之类的材料，而下部镜层166内部的第二、第四和第六薄膜可以包含铝镓的砷化物，反之亦然。层168包含用于产生光子的有源区域。以和下部镜层166类似的方式形成上部镜层170，上部镜层170包含交替的复合半导体材料薄膜。在一个具体实施例中，上部镜层170可以由p-型掺杂复合半导体材料组成，下部镜层166可以由n-型掺杂复合半导体材料组成。
在上部镜层170上形成另一个与调节缓冲层164类似的调节缓冲层172。在一个可选实施例中，调节缓冲层164和172可以包含不同的材料。然而在产生复合半导体层和IV族单晶半导体层之间的过渡方面，它们具有基本相同的作用。在调节缓冲层172上形成IV族单晶半导体层174。在一个具体实施例中，IV族单晶半导体层174包含锗、硅锗、硅锗的碳化物等等。
在图13中，加工MOS部分以便在这个上部IV族单晶半导体层174内形成电元件。如图13所示，在层174的一部分中形成场隔离区171。在层174上形成栅极介质层173，在栅极介质层173上形成栅电极175。如图所示，掺杂区177是晶体管181的源极、漏极或源极/漏极区。形成与栅电极175的垂直侧相邻的侧壁隔层179。至少可以在部分的层174内产生其它元件。这些其它元件包含其它晶体管(N-沟道或P-沟道)、电容器、晶体管、二极管等等。
IV族单晶半导体层在一个掺杂区177上外延生长。如图13所示，上面的部分184进行P+掺杂，下面的部分182基本上保持本征(未掺杂)。可以使用选择性外延方法形成该层。在一个实施例中，在晶体管181和场隔离区171上形成绝缘层(未示出)。组装绝缘层以形成开口，所述开口暴露出一个掺杂区177。至少在开始时，选择性外延层的形成过程中没有使用掺杂剂。整个选择性外延层可以是本征的，或者可以在选择性外延层的形成接近结束时加入p-型掺杂剂。如果所形成的选择性外延层是本征的，则通过植入或熔炼掺杂(furnace doping)可以完成掺杂步骤。无论以何种方式形成上面的P+部分184，接着清除绝缘层以形成图13所示的结构。
如图14所示，接着执行一系列步骤以形成光学激光器180。清除集成电路的复合半导体部分上的场隔离区171和调节缓冲层172。执行额外步骤以形成光学激光器180的上部镜层170和有源层168。上部镜层170和有源层168的侧面基本上是相连的。
如图14所示，形成接点186和188以便分别与上部镜层170和下部镜层166电连接。接点186呈环形以便光(光子)能够传出上部镜层170并进入后来形成的光学波导中。
接着如图15所示，形成和组装绝缘层190以形成延伸到接点层186和一个掺杂区177的光学开口。绝缘材料可以是任意数量的不同材料，其中包含氧化物、氮化物、氮氧化物、低介电常数电介质或其任意组合。如图16所示，在形成开口192之后，接着在各开口内部形成并填充高折射系数材料202，并且在绝缘层190上沉积出覆层。对于高折射系数材料202，“高”是针对绝缘层190的材料而言(即材料202的折射系数高于绝缘层190的折射系数)。可选地，在形成高折射系数材料202之前可以形成具有相对较低折射系数的薄膜(未示出)。接着在高折射系数层202上形成硬掩模层204。从覆盖开口并且延伸到接近图16侧面区域的部分中清除硬掩模层204和高折射系数层202的相应部分。
如图17所示，完成对光学波导构造的平衡，所述光学波导是光学互连。  执行沉积过程(或者沉积-蚀刻方法)以便有效地产生侧壁区段212。在这个实施例中，侧壁区段212的组成材料与材料202相同。接着清除硬掩模层204，在高折射系数材料212和202以及绝缘层190的暴露部分上形成低折射系数层214(相对于材料202和层212具有较低的折射系数)。图17中的虚线示出了高折射系数材料202和212之间的边界。这种表示方法表示区段202和212具有相同的材料但在不同的时间形成。
如图18所示，继续加工以形成基本上完整的集成电路。接着在光学激光器180和MOSFET晶体管181上形成钝化层220。可以针对集成电路中的元件建立其它电或光连接，但图18中没有示出。这些互连可以包含其它光学波导，也可以包含金属互连。
在其它实施例中，可以形成其它类型的激光器。例如，另一种激光器可以水平而不是垂直发光(光子)。如果水平发光，可以在基底161内形成MOSFET晶体管并且重新配置光学波导，使得激光器与晶体管正确耦合(光连接)。在一个具体实施例中，光学波导可以包含调节缓冲层的至少一部分。还可以有其它结构。
显然，这些具有复合半导体部分和IV族半导体部分的集成电路实施例仅用于图解本发明的实施例，并不对本发明作出限定。本发明有各种其它组合和其它实施例。例如，复合半导体部分可以包含发光二极管、光电检测器、二极管等等，IV族半导体可以包含数字逻辑、存储器阵列和大多数可以在传统MOS集成电路中形成的结构。通过使用本发明的实施例，很容易得到良好发挥出复合半导体材料优势的集成器件，所述集成器件还具有良好发挥出IV族半导体材料优势的其它元件。这允许缩小器件尺寸，降低制造成本并且提高生产率和可靠性。
尽管没有图解，但IV族单晶晶片可被用来在晶片上形成纯复合半导体电元件。通过这种方式，当在覆盖晶片的单晶复合半导体层内制造复合半导体电元件时，晶片实质上被用作“操作”晶片。因此，在直径至少有大约200毫米并且可能至少接近300毫米的晶片上，可以在III-V或II-VI族半导体材料内部形成电元件。
在使用这类基底的情况下，通过把复合半导体晶片放置在相对更加耐用并且易于制造的基底材料上，相对廉价的“操作”晶片克服了复合半导体晶片的易碎性质带来的问题。因此，可以形成这样的集成电路，使得即使基底自身可能包含IV族半导体材料，也可以在复合半导体材料内部形成所有电元件，尤其是所有有源电子器件。由于和相对较小并且更加易碎的传统复合半导体晶片相比，加工较大的基底更加经济并且更加容易，所以肯定可以降低复合半导体器件的制造成本。
在前面的说明书中参照特定实施例描述了本发明。然而本领域的普通技术人员理解，在不偏离如下面权利要求书提出的本发明的范围的前提下可以进行各种修改和变化。相应地，说明书和图例只被看作图解的而不是限定性的，并且所有这种修改均被包含在本发明的范围内。
前面已经针对具体实施例描述了本发明的益处、其它优点和问题解决方案。然而，上述益处、优点、问题解决方案，以及目的是使任何益处、优点或解决方案付诸实现和易于理解的任何要素，均不得被解释成任何或所有权利要求的关键、必需或必要特征或要素。这里，术语“包括”“含有”或其任何其他类似表达方式均被用来覆盖非排它性的内含，使得包括一系列要素的过程、方法、项目或装置不仅仅包含那些要素，而是可以包含其它没有明确列出或所述过程、方法、项目或装置固有的要素。

Claims (30)

1.一种半导体结构，包括：
单晶氧化物材料；和
所形成的、覆盖单晶氧化物材料的第一类型单晶复合半导体材料。
2.如权利要求1所述的半导体结构，还包括在单晶氧化物材料和第一类型单晶复合半导体材料之间形成的模板层。
3.如权利要求1所述的半导体结构，还包括在单晶氧化物材料和第一类型单晶复合半导体材料之间形成的第二类型单晶半导体材料缓冲层。
4.如权利要求3所述的半导体结构，还包括在单晶氧化物材料和第二类型单晶半导体材料缓冲层之间形成的模板层。
5.如权利要求3所述的半导体结构，其中缓冲层包括从以下材料中选出的单晶半导体材料：
锗，GaAsxP1-x超晶格，InyGa1-yP超晶格和InGaAs超晶格。
6.如权利要求1所述的半导体结构，其中单晶氧化物材料包括从以下材料中选出的氧化物：碱土金属的钛酸盐，碱土金属的锆酸盐，碱土金属的铪酸盐，碱土金属的钽酸盐，碱土金属的钌酸盐，碱土金属的铌酸盐，碱土金属的钒酸盐，锡基钙钛矿结构碱土金属，铝酸镧，镧钪氧化物和氧化钆。
7.如权利要求1所述的半导体结构，其中单晶氧化物材料包括SrzBa1-zTiO3，z的范围为0到1。
8.如权利要求1所述的半导体结构，其中单晶氧化物材料包括钙钛矿结构氧化物。
9.如权利要求1所述的半导体结构，其中单晶复合半导体材料包括从以下材料中选出的材料：III-V族复合物，混合III-V族复合物，II-VI族复合物和混合II-VI族复合物。
10.如权利要求1所述的半导体结构，其中单晶复合半导体材料包括从以下材料中选出的材料：GaAs，AlGaAs，InP，InGaAs，InGaP，ZnSe，AlInAs，CdS，CdHgTe和ZnSeS。
11.一种半导体结构，包括：
具有第一特征的单晶氧化物材料；和
在单晶氧化物材料上生长的、具有第二特征的单晶复合半导体材料；
其中第一和第二特征彼此相关，其相关方式包括：
第一和第二特征是晶格常数，并且第一和第二特征基本匹配；及
第一和第二特征涉及单晶氧化物材料和单晶复合半导体材料的晶体取向，其中晶体取向彼此相对旋转。
12.如权利要求11所述的半导体结构，其中单晶复合半导体材料包括从以下材料中选出的材料：GaAs，AlGaAs，InP，InGaAs，InGaP，ZnSe和ZnSeS。
13.如权利要求11所述的半导体结构，其中单晶氧化物材料包括从以下材料中选出的氧化物：碱土金属的钛酸盐，碱土金属的锆酸盐，碱土金属的铪酸盐，碱土金属的钽酸盐，碱土金属的钌酸盐，碱土金属的铌酸盐，碱土金属的钒酸盐，锡基钙钛矿结构碱土金属，铝酸镧，镧钪氧化物和氧化钆。
14.如权利要求11所述的半导体结构，其中单晶氧化物材料包括SrzBa1-zTiO3，z的范围为0到1。
15.如权利要求11所述的半导体结构，其中晶体取向彼此相对旋转45度。
16.一种半导体结构，包括：
以第一晶格常数为特征的单晶基底；
覆盖单晶基底的单晶氮化物层，所述单晶氮化物层具有不同于第一晶格常数的第二晶格常数；和
覆盖单晶氮化物层的单晶复合半导体层，所述单晶复合半导体层具有不同于第一和第二晶格常数的第三晶格常数。
17.如权利要求16所述的半导体结构，其中单晶氮化物包括从以下材料中选出的材料：氮化镓，氮化铝和氮化硼。
18.一种半导体结构，包括：
包括硅并且具有第一区域和第二区域的第一单晶半导体基底；
包括氧化硅并且覆盖第一区域的中间层；
覆盖中间层的第一单晶氧化层；
覆盖第一单晶氧化层的第二单晶半导体层；
覆盖第二单晶半导体层的第二单晶氧化层；和
覆盖第二单晶氧化层的第三单晶半导体层，其中第二单晶半导体层和第三半导体层中的至少一个包括复合半导体材料。
19.如权利要求18所述的半导体结构，还包括位于第一单晶氧化层和第二单晶半导体层之间的模板层。
20.如权利要求18所述的半导体结构，还包括至少部分位于第二区域中的有源半导体元件。
21.如权利要求20所述的半导体结构，还包括至少部分位于第二单晶半导体层中的第二半导体元件。
22.如权利要求21所述的半导体结构，其中第二单晶氧化层包括第二半导体元件的栅极介质。
23.如权利要求21所述的半导体结构，还包括有源半导体元件和第二半导体元件之间的电互连。
24.如权利要求21所述的半导体结构，其中第二单晶半导体层包括III-V族复合物，而第二半导体元件包括射频放大器中的元件。
25.一种半导体结构，包括：
单晶半导体基底；
包括SrzBa1-zTiO3并且覆盖单晶半导体基底的单晶氧化层，其中z的范围为0到1；和
位于单晶半导体基底和单晶氧化层之间的非晶质层。
26.如权利要求25所述的半导体结构，其中单晶半导体基底包括IV族元素。
27.如权利要求25所述的半导体结构，其中单晶氧化层的厚度大于20nm。
28.如权利要求25所述的半导体结构，其中非晶质层包括氧化硅并且其厚度足够消除单晶氧化层中的变形。
29.如权利要求25所述的半导体结构，其中非晶质层包括氧化硅并且其厚度大于1.0nm。
30.如权利要求25所述的半导体结构，其中非晶质层包括氧化硅并且其厚度为0.5到2.5nm。
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