CN1430792A - 半导体器件及方法 - Google Patents

半导体器件及方法 Download PDF

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CN1430792A
CN1430792A CN01809824A CN01809824A CN1430792A CN 1430792 A CN1430792 A CN 1430792A CN 01809824 A CN01809824 A CN 01809824A CN 01809824 A CN01809824 A CN 01809824A CN 1430792 A CN1430792 A CN 1430792A
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insulating barrier
semiconductor device
substrate
forms
layer
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库尔特·埃森贝瑟
王军
拉文德拉纳施·德鲁帕德
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NXP USA Inc
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

电路(10)具有在半导体衬底(14)上形成的双层栅极绝缘层(29)。栅极绝缘层包括非晶层(40)和单晶层(42)。特别地，单晶层具有比非晶层更高的介电常数。

Description

半导体器件及方法
技术领域
本发明一般涉及半导体器件，尤其涉及到在高密度集成电路中制作的晶体管。
背景技术
目前，需要一种具有高密度和功能增强的集成电路。为了满足这个需求，必须减小集成电路中晶体管的尺寸。例如，期望未来制作的集成电路晶体管具有100nm或更小的有效沟道长度。
如此小的晶体管常常受到边缘场和其它短沟道效应的不利影响，这些效应降低晶体管的性能并削弱对晶体管工作的控制。为了减少短沟道效应，通常使用更薄的栅极绝缘层。然而，薄的栅极绝缘层常常引起额外的栅极泄漏电流，栅极泄漏电流使集成电路功率增加并降低集成电路的性能。
因此，需要一种晶体管，这种晶体管具有小的物理尺寸但不会受到短沟道效应或额外的栅极泄漏电流的不利影响。
发明内容
一种电路，具有在半导体衬底上形成的双层栅极绝缘层。栅极绝缘层包括非晶层和单晶层。特别地，单晶层具有比非晶层更高的介电常数。
附图说明
对于本领域的技术人员，从下面结合附图的相关的详细描述中，本发明的特定目的及其优点将是显而易见的，这些附图中：
图1是部分集成电路的顶视图；
图2表示集成电路在加工步骤中制作晶体管栅极绝缘层时的剖面图；
图3表示在制作稍后阶段的集成电路剖面图。
具体实施方式
在所有图中，相同标号的元件具有相同的功能。
图1是集成电路10的顶视图，表示在半导体衬底14上形成的晶体管12。在图1的具体实施方式中，晶体管12是一个N型沟道的金属氧化物半导体晶体管。晶体管12包含漏区16、源区18和栅极20，它们分别通过互连线22、24和26与集成电路10的其它器件(未示出)耦合在一起。
衬底14代表性地由硅制成。也可选择使用其它半导体材料，比如砷化镓、锗以及类似的材料。
图2是集成电路10在晶体管12的沟道区30上制作双层栅极绝缘层29步骤中的剖面图。衬底14的一部分使用N型掺杂物质(比如磷或砷)进行了掺杂，以形成如图所示的漏区16和源区18。漏区16和源区18之间的距离典型为100nm或更小。
栅极绝缘层29包含非晶层40(典型地由SiO2组成)。栅极绝缘层还包含单晶层42(典型地由SrTiO3组成)。这里应该注意的是，单晶层42通常生长为单晶结构，而非晶层40通常是指没有短程或长程有序的一层。
集成电路10所示为置于分子束外延(MBE)反应器等设备的内腔中。在MBE反应器中，环境温度为400到600摄氏度以及压力在10-9到10-5毫巴时，形成包含气态钛(Ti)原子32、锶(Sr)原子34和氧(O2)分子36的气氛。钛气化室(未示出)局部加热到大约1750摄氏度的温度以使钛气化产生钛原子32。锶气化室(未示出)加热到大约450摄氏度的温度以产生锶原子34。锶原子34和钛原子32按照近似单晶钛酸锶形成的化学计量比产生。氧分子36是通过操作过压大约10-6毫巴的氧源(未示出)以过量化学计量比供给。
钛原子32、锶原子34和氧分子36反应形成钛酸锶分子46。在上述的条件下，钛酸锶分子按晶体方式生长以形成单晶层42。单晶层42的第一分子层在图2中表示为空心圆，空心圆用线连在一起表示晶化钛酸锶分子46及其相互连接的键合力。进一步反应致使其它钛酸锶分子层在第一分子层上晶化。
氧分子36以过量化学计量比供给，所以过量的氧可以扩散穿过单晶层42与衬底14的硅原子反应。反应生成二氧化硅分子44(图2中表示为正方形)覆盖在衬底14的表面。二氧化硅分子44以非晶方式生长从而形成非晶层40。
作为本发明的一个特征，在单晶层42生长时生长非晶层40。因此，仅仅需要一次加热过程形成非晶层40和单晶层42，从而实现集成电路10的低制作成本。而且，在衬底14和单晶层42之间形成非晶层40作为一种过渡材料起到吸收衬底14与单晶层42之间的晶格应力的作用，致使栅极绝缘层29质量高。
图3表示集成电路10在比图2中描述步骤更晚的加工步骤中的剖面图。晶体管12包含在衬底14上形成的漏区16和源区18。栅极绝缘层29包含非晶层40和单晶层42。栅极电极26处于栅极绝缘层29之上以在栅极电极26与衬底14之间形成栅极电容，栅极电容通过施加到栅极电极26上的控制信号VIN充电。
非晶层40典型地由生长到10埃厚的二氧化硅组成。取决于应用情况，非晶层40的厚度典型地在8到30埃范围内。非晶层40典型地具有大约3.9的相对介电常数，也就是介电常数。非晶层40还由其它材料组成，比如氮化硅、锶硅酸盐以及类似的材料。非晶层40最好具有小于10的介电常数。
单晶层42以典型地生长到50埃厚的钛酸锶形成，取决于应用情况，单晶层42的厚度典型地在30到100埃范围内。在图3的具体实施方式中，单晶层42具有大约200(在30到300的范围内)的介电常数。单晶层42的介电常数最好大于非晶层40的介电常数。
注意单晶层42可能由钛酸锶之外的其它材料形成。例如，通过碱土金属(比如镧、钡、锶或镁)与过渡金属(比如钛、铝或锆)化合形成的钙钛矿结构的材料，可以用于形成单晶层42。
在使用中，控制信号VIN施加到栅极26以对晶体管12的栅极电容充电。穿过栅极绝缘层29产生一个电场60，该电场60改变衬底14的导电性并在衬底14中源区18与漏区16之间产生导电沟道52。响应电场60，在单晶层42中产生一个极化场62，在非晶层40中产生极化场64。由于单晶层42的介电常数大于非晶层40的介电常数，极化电场64大于极化电场62。
晶体管12的栅极电容依赖于栅极绝缘层29的厚度和有效介电常数。本发明的结果是栅极绝缘层29可以比具有低介电常数栅极绝缘层的晶体管生长到更大的厚度。增加的厚度实质上消除晶体管12的额外栅极泄漏以提高集成电路10的性能。而且非晶层40低的相对介电常数减小控制信号VIN在晶体管12中产生的边缘场，从而避免短沟道效应并改善超过晶体管12阈值电压的控制。
因此，应该意识到本发明提供了一种晶体管，这种晶体管可以缩减到小于100nm的尺寸并同时保持高性能和低制作成本。在半导体衬底上形成双层栅极绝缘层，第一层由非晶材料形成，第二层由单晶材料形成。非晶材料为衬底与单晶材料之间的晶格错配提供过渡，而且具有低的介电常数以减小边缘场。单晶材料部分由于晶体的本身特性而具有高的介电常数，而且制成适于消除额外栅极泄漏的厚度。
尽管我们展示和描述了本发明的详细的具体实施方式，但对于那些本领域的技术人员可进行进一步的改变和改进。因此，我们希望理解本发明并不限于所示出的实例，而且我们打算在附加的权利要求中包含所有不偏离本发明精神和范围的改变。

Claims (10)

1.一种半导体器件，包括：
半导体衬底；和
在半导体衬底上形成的绝缘层，绝缘层第一部分由非晶材料形成，第二部分由单晶材料形成，绝缘层中的电场控制半导体衬底的导电性。
2.根据权利要求1的半导体器件，还包含覆盖在绝缘层之上的控制电极，控制电极用于在控制电极和半导体衬底之间建立电场。
3.根据权利要求2的半导体器件，还包括：
漏区；和
源区，电场在衬底中产生导电沟道以连接漏区和源区。
4.根据权利要求1的半导体器件，其中绝缘层的第一部分靠近半导体衬底形成，绝缘层的第二部分在第一部分与控制电极间形成。
5.根据权利要求1的半导体器件，其中非晶材料包括二氧化硅。
6.根据权利要求1的半导体器件，其中单晶材料包含从钡、锶、钛、镧、锆、铝和氧中选取的材料。
7.根据权利要求1的半导体器件，其中绝缘层的第一部分具有小于10的相对介电常数，绝缘层的第二部分具有大于30的相对介电常数。
8.根据权利要求7的半导体器件，其中绝缘层厚度大于30埃。
9.一种晶体管，包括：
衬底；
处于衬底之上的栅极电极，栅极电极用于响应控制信号在衬底中产生导电沟道；以及
在导电沟道上形成的绝缘层，绝缘层包括由非晶材料形成的第一层和处于第一层与栅极电极之间由单晶材料形成的第二层。
10.根据权利要求9的晶体管，其中单晶材料具有比非晶材料更高的介电常数。
CN01809824A 2000-05-31 2001-04-26 半导体器件及方法 Pending CN1430792A (zh)

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