CN1434983A - 具有晕圈源极/漏极扩散的芯片上的无晕圈非整流接触 - Google Patents
具有晕圈源极/漏极扩散的芯片上的无晕圈非整流接触 Download PDFInfo
- Publication number
- CN1434983A CN1434983A CN01810810A CN01810810A CN1434983A CN 1434983 A CN1434983 A CN 1434983A CN 01810810 A CN01810810 A CN 01810810A CN 01810810 A CN01810810 A CN 01810810A CN 1434983 A CN1434983 A CN 1434983A
- Authority
- CN
- China
- Prior art keywords
- diffusion
- contact
- fet
- nonrectifying
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 title claims abstract description 120
- 125000001475 halogen functional group Chemical group 0.000 title abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000012797 qualification Methods 0.000 claims description 2
- 241000446313 Lamella Species 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000002347 injection Methods 0.000 description 15
- 239000007924 injection Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000036413 temperature sense Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Abstract
一种半导体芯片包含具有整流接触扩散和非整流接触扩散的半导体基底。晕圈扩散邻近整流接触扩散，而无晕圈扩散邻近非整流接触扩散。为了提高击穿抵抗力，整流接触扩散可以是FET的源极/漏极扩散。非整流接触扩散可以是FET体接触、横向二极管接触或电阻或电容接触。避免非整流接触的晕圈，降低了串联电阻并且改进了器件特征。在具有邻近扩散的晕圈的器件的芯片上的另一个实施例中，无晕圈扩散邻近横向二极管的整流接触扩散，从而显著改进了二极管的理想度并且提高了击穿电压。
Description
技术领域
本发明涉及高性能半导体集成电路芯片上的器件中的扩散。更具体地，本发明涉及这种集成电路芯片的晕圈注入(haloimplant)。
背景技术
对称和非对称晕圈注入被用于通过提高抗击穿能力来改进低功率短沟道场效应晶体管(FET)的性能。对称晕圈注入是具有较高掺杂物浓度的区(pocket)，其导电类型与FET源极和漏极边缘相邻区域中的沟道区相同。在与邻近源极/漏极扩散相对的位置上掺杂这些FET晕圈注入的每一个。非对称晕圈注入延伸到邻近源极或者邻近漏极，或者也可以延伸到源极和漏极的相邻位置，但其邻近程度不同。晕圈注入也可以延伸到邻近源极或漏极边缘的沟道区的内部或下面。人们相信晕圈注入的进一步改进是可以获得的并将提高器件和芯片性能，因此本发明提供了一个解决方案。
发明内容
本发明的实施例的目的是避免在具有晕圈注入的FET器件的芯片上的器件的非整流接触(non-rectifying contact)上的晕圈注入。
另一个目的是避免在具有晕圈注入的FET器件的芯片上的栅极导体限定的电阻器、电容器、横向二极管、横向SOI(绝缘体衬底硅)二极管和FET体接触的非整流接触上的晕圈注入。
本发明的实施例的一个特征在于，不需要用特殊的掩膜来避免在非整流接触上的晕圈注入。
本发明的另一个特征在于，横向SOI门控二极管，例如用于过冲/下冲箝位(overshoot/undershoot clamping)、ESD保护和温度感应的横向SOI门控二极管在一个或两个扩散接触中具有无晕圈扩散。
本发明实施例的一个优点在于，避免在非整流接触上的晕圈注入改进了具有晕圈注入的FET的集成电路上的器件的串联电阻和性能。
另一个优点在于，避免在非整流接触上的晕圈注入提高了具有晕圈注入的FET的集成电路芯片的生产量。
这些和其它目的、特性和优点是通过包括半导体基底的半导体芯片来实现的。整流接触扩散和非整流接触扩散均在基底中。晕圈扩散邻近整流接触扩散，而无晕圈扩散邻近非整流接触扩散。
此结构适于形成针对具有邻近源极或漏极晕圈扩散的FET的芯片上的FET、横向二极管、电阻器和电容器的体接触。此结构尤其适用于SOI芯片，但是也可以用于体式(bulk)硅芯片。
附图说明
通过下面结合附图对本发明进行的详细描述可以理解本发明的上述和其它目的、特性和优点，其中：
图1a是本发明的FET的顶视图，其中FET具有源极/漏极扩散和与栅极相邻的体接触，源极/漏极扩散具有晕圈注入，而体接触则没有；
图1b是类似图1a FET的一个FET的顶视图，但是具有T形栅极；
图1c沿着线条1c-1c′切割图1a的器件得到的弯折剖视图；
图2a是本发明的横向二极管的顶视图，其中二极管具有整流扩散和与栅极导体相邻的非整流扩散，整流扩散具有晕圈注入，而非整流扩散则没有；
图2b是图2a的器件的剖视图；
图2c是本发明的横向二极管的顶视图，其中二极管包含整流扩散和与栅极导体相邻的非整流扩散，整流扩散和非整流扩散均不具有晕圈注入；
图3a是比较具有和不具有邻近非整流扩散的晕圈注入的正向偏置二极管的I-V特征图表；
图3b是电阻对应栅极-源极电压的图表，示出了具有邻近非整流体接触扩散的晕圈注入的SOI FET的电阻的不规则变化；
图4a是本发明的器件的剖视图，其中该器件具有两个没有邻近栅极导体的晕圈注入的非整流结，该器件可以充当电阻器或电容器；以及
图4b是现有技术器件的剖视图，该器件具有两个带晕圈注入的非整流结，其中该器件可以充当电阻器或电容器。
具体实施方式
本发明的发明人发现，如果也在非整流或欧姆接触(ohmiccontact)邻近提供晕圈注入，则被用来避免场效应晶体管(FET)器件上的击穿的晕圈注入会降低器件性能。非整流接触被用作例如对FET的体接触。非整流接触也被用于栅极导体限定的横向二极管欧姆接触。非整流接触也可以被用于电阻器和电容器的栅极导体限定的扩散，所述电阻器和电容器具有与栅极导体下面的半导体主体相同的掺杂。形成与这种扩散的接触以便向栅极导体下面的主体区域提供非整流接触，或者向主体提供到达另一个非整流接触的电阻路径。在这些情况下，晕圈注入会被对置地掺杂到扩散和栅极下面的主体区域中。
发明人发现，对置掺杂的晕圈区域引入了与欧姆接触平行的不希望的整流区域。通过减少欧姆接触面积或阻挡欧姆接触，晕圈也对体接触产生干扰。因此，晕圈注入也提高了非整流或欧姆接触与器件的主体或沟道区之间的串联电阻。对于FET，主体电势的控制因而发生退化，从而使对阈值电压的控制退化。这降低了功能测试效率并且增加了制造集成电路芯片的成本。
本发明的实施例提供邻近整流扩散，例如FET的源极/漏极扩散的晕圈注入，而不提供用于非整流扩散，例如针对FET、横向二极管和栅极限定的电阻器和电容器的体接触的晕圈注入。如图1a、1b的顶视图和图1c的弯折剖视图所示，在体式基底16上的后绝缘体14上的SOI主体12上形成FET 10和FET 10′。FET 10包含邻近栅极介质29上的栅极28或T形栅极28′的源极/漏极扩散24、26。
在这种应用中，后来施加的层可以在其它层的“上面”(on)，即使存在中间层，并且不管基底、晶片或芯片的取向如何。
FET 10还包含邻近源极/漏极扩散24和体接触38的延伸扩散30、32和晕圈扩散34、36。从邻近源极/漏极扩散24对置地掺杂晕圈扩散34、36。
如图1c所示，在邻近体接触38的位置提供与主体12和体接触38对置掺杂的无晕圈扩散，从而充分地降低了因含有晕圈而导致的串联电阻和性能退化。
另外，省略了体接触38的延伸扩散。在处理过程中早于源极漏极扩散的相同掩膜步骤中提供延伸和晕圈注入。延伸是与源极/漏极掺杂相同的掺杂类型，但是更接近表面并且更加向栅极的下面延伸。延伸注入通常配有沿着法线指向晶片表面的离子束。晕圈注入可以被垂直瞄向表面或以一个角度，以便在栅极28的下面提供离子。可选地，可以一部分垂直而一部分以一个角度提供晕圈剂。
在形成CMOS芯片上的FET的扩散时，通常使用四个掩膜。一个掩膜被用于p沟道器件的晕圈和延伸注入。该掩膜阻挡了n沟道器件。第二掩膜被用于n沟道器件的晕圈和延伸扩散。该掩膜阻挡了p沟道器件。接着沿着栅极28的侧壁提供隔离物40。第三个掩膜被用于p沟道器件的源极/漏极深扩散。该掩膜阻挡了n沟道器件。然后第四个掩膜被用于n沟道器件的源极/漏极深扩散。该掩膜阻挡了p沟道器件。本发明重新设计了这两个晕圈和延伸掩膜以便向被两个晕圈和延伸掩膜阻挡的一系列位置加入用于FET体接触、横向二极管以及栅极限定的电阻器和电容器的非整流接触。为了在体接触上提供延伸而不是晕圈需要另一个掩膜。这就是晕圈和延伸注入被阻挡的原因。附加的掩膜可以被用于在保持阻挡晕圈的同时提供延伸。
在此处理过程中，阻挡掩膜在非整流扩散接触的位置上具有阻挡区域。由至少一个其它掩膜上的数据来限定这种非整流扩散接触，并且通常需要用三个掩膜定义非整流扩散接触。根据那些其它掩膜上的数据生成该阻挡掩膜上的阻挡区域。通过逻辑组合来自三个其它掩膜的形状并且调整结果以避免在阻挡掩膜上形成亚光刻特征(sublithographic feature)，根据在三个其它掩膜上的数据生成阻挡掩膜上的阻挡区域。亚光刻特征包含尺寸小于用光刻处理可以分辨的最小尺寸的凹口(notch)和长条(sliver)。对于将晕圈保持在非整流扩散接触之外并且不会大到阻挡所需晕圈注入的程度而言，阻挡区域的设计很关键。
在本发明的另一个实施例中，在后绝缘体14上的绝缘体衬底硅(SOI)主体12上形成横向二极管46。如图2a的顶视图和图2b的剖视图所示，二极管46包含整流扩散54和非整流扩散56，它们均邻近栅极导体58。横向二极管46可被用于例如锁相环电路、静电放电(ESD)保护器件、过电压箝位网络或温度感应器件。形成栅极导体58的材料与FET栅极28相同，但对于横向二极管不起栅极功能。整流扩散54具有延伸注入60和晕圈扩散62。如图3a和3b所示，非整流扩散56具有陡峭的、不含晕圈注入的p+到p-欧姆接触区域64，充分地改进了二极管46的串联电阻。另外，即使是实现本发明的最简单的处理也可以消除非整流扩散56上的延伸注入。如果需要，通过一个附加掩膜可以随着扩散56一起提供延伸注入(未示出)。
在本发明的再另一个实施例中，如图2c所示，晕圈注入被包含在FET源极漏极扩散附近，但是横向二极管46′没有将晕圈注入62放置在邻近整流扩散54′和非整流扩散56的位置上。不使晕圈注入62注入整流扩散54′附近，提高了二极管击穿电压，降低了二极管正向泄漏，提高了二极管理想因子，并且改进了指数IV特征的线性。于是，二极管46′可以更好地在芯片上发挥各种作用，例如温度测量和ESD保护。如上所述，通过阻挡晕圈和延伸掩膜上的注入，消除了将晕圈注入到整流扩散54′附近。
在本发明的再另外的实施例中，如图4a所示，在扩散70a、70b附近没有晕圈注入的情况下形成电阻器和电容器。通过在具有晕圈注入的FET(参见图1a、1b)的芯片上提供邻近栅极导体72的扩散，形成这些电阻器或电容器。通过比较，如现有技术图4b所示，如果在具有邻近栅极导体72的晕圈注入74a、74b的情况下形成电阻器和电容器，则串联电阻更高，并且会增加对该附加串联电阻的本质的电压依赖。最终结果是芯片性能退化。当在到扩散70a和扩散70b的接触之间提供电压时，图4a、4b的器件是电阻器。当向栅极导体72和扩散70a、70b之间的接触提供电压时，该器件是电容器。如果需要，通过一个额外的掩膜，可以随着扩散70a、70b一起提供延伸注入(未示出)。
这里结合附图详细描述和说明了本发明的若干实施例及其修改，显然在不偏离本发明的范围的前提下还可以进行各种修改。例如，也包括与所说明的类型相对的掺杂类型。本发明也适用于体式和采用SOI技术的双栅极FET。上述说明书的内容不是要将本发明限定得比所附权利要求书更窄。所提供的例子仅用于说明，并不是排它性的。
Claims (30)
1.一种半导体芯片，包括：
半导体基底；
所述基底中的整流接触扩散和非整流接触扩散；以及
邻近所述整流接触扩散的晕圈扩散和邻近所述非整流接触扩散的无晕圈扩散。
2.如权利要求1所述的半导体芯片，其特征在于，所述整流接触是FET的源极/漏极扩散。
3.如权利要求1或2所述的半导体芯片，其特征在于，所述非整流接触是FET的体接触、横向二极管的欧姆接触、电阻器的接触或者电容器的接触。
4.如权利要求1、2或3所述的半导体芯片，其特征在于，所述芯片还包括栅极导体，其中所述整流接触由所述栅极导体限定。
5.如权利要求1、2、3或4所述的半导体芯片，其特征在于，所述芯片还包括栅极导体，其中所述非整流接触由所述栅极导体限定。
6.如权利要求1至5中任何一个所述的半导体芯片，其特征在于，所述芯片还包括栅极导体，其中所述整流接触和所述非整流接触均由所述栅极导体限定。
7.如权利要求6所述的半导体芯片，其特征在于，所述整流接触是FET的源极/漏极扩散，并且其中所述非整流接触是所述FET的体接触。
8.如权利要求7所述的半导体芯片，其特征在于，所述FET包括栅极导体，所述源极/漏极扩散和所述体接触均由所述栅极导体限定。
9.如权利要求8所述的半导体芯片，其特征在于，所述FET还包括后绝缘体和所述后绝缘体上的半导体薄层。
10.如权利要求6所述的半导体芯片，其特征在于，所述整流接触是横向二极管的扩散，并且其中所述非整流接触是到所述二极管的欧姆接触。
11.如权利要求1至10中任何一个所述的半导体芯片，其特征在于，所述芯片还包括FET和横向二极管，所述FET包括源极/漏极扩散，而所述横向二极管包括整流接触扩散和非整流接触扩散，其中所述整流接触是所述FET的所述源极/漏极扩散，所述非整流接触是所述横向二极管的所述非整流接触扩散，并且进一步其中在所述横向二极管的所述整流接触扩散邻近有无晕圈扩散。
12.如权利要求1至11中任何一个所述的半导体芯片，其特征在于，所述芯片还包括第一栅极导体和第二栅极导体，其中所述整流接触受所述第一栅极导体的限定，而所述非整流接触由所述第二栅极导体限定。
13.如权利要求12所述的半导体芯片，其特征在于，还包括FET以及横向二极管、电阻器和电容器中的一个，其中所述整流接触是所述FET的源极/漏极扩散，并且所述非整流接触是到所述横向二极管、电阻器或电容器的欧姆接触。
14.如权利要求13所述的半导体芯片，其特征在于，所述横向二极管用于ESD保护、过冲/下冲保护或者过电压箝位。
15.如权利要求13所述的半导体芯片，其特征在于，所述横向二极管还包括整流接触扩散，其中无晕圈扩散邻近所述整流接触扩散。
16.如权利要求1至15中任何一个所述的半导体芯片，其特征在于，还包括第二非整流接触，其中无晕圈扩散邻近所述非整流接触中的任何一个。
17.如权利要求1至15中任何一个所述的半导体芯片，其特征在于，该芯片包括绝缘体衬底硅。
18.如权利要求1至17中任何一个所述的半导体芯片，其特征在于，该延伸扩散邻近所述源极漏极扩散，并且无延伸扩散邻近所述非整流接触。
19.一种制作半导体芯片的方法，包括步骤：
提供半导体基底；
在所述基底上形成整流扩散接触；
在所述基底上形成非整流扩散接触；以及
形成邻近所述整流扩散接触的晕圈扩散，并且形成邻近所述非整流扩散接触的无晕圈扩散。
20.如权利要求19所述的方法，其特征在于，在所述形成步骤(b)中，所述整流扩散是FET的源极/漏极扩散，其中在所述形成步骤(c)中，所述非整流接触是所述FET的体接触。
21.如权利要求19所述的方法，其特征在于，所述非整流扩散接触是横向二极管的一个电极。
22.如权利要求21所述的方法，其特征在于，所述横向二极管用于ESD保护、过冲/下冲保护或者过电压箝位。
23.如权利要求21所述的方法，其特征在于，在所述形成步骤(b)中，所述整流扩散是FET的源极/漏极扩散或所述横向二极管的第二电极。
24.如权利要求19至23中任何一个所述的方法，其特征在于，在所述形成步骤(b)中，所述整流扩散是FET的源极/漏极扩散，其中所述形成步骤(c)包括形成具有一对所述非整流扩散接触的器件，并且所述步骤(d)包括形成邻近所述非整流接触中任意一个的无晕圈扩散。
25.如权利要求24所述的方法，其特征在于，所述器件包括电阻器或电容器。
26.如权利要求19到25中任何一个所述的方法，其特征在于，在所述形成步骤(a)中，所述基底包括SOI。
27.如权利要求19至26中任何一个所述的方法，其特征在于，还包括形成邻近所述整流接触扩散的延伸扩散，以及形成邻近所述非整流接触扩散的无延伸扩散。
28.如权利要求19至27中任何一个所述的方法，其特征在于，所述形成步骤(d)包括提供包含非整流扩散接触的位置的第一掩膜，其中所述第一掩膜在所述位置上具有阻挡区域。
29.如权利要求28所述的方法，其特征在于，所述非整流扩散接触由至少一个其它掩膜上的数据限定，并且其中根据所述数据生成所述第一掩膜上的所述阻挡区域。
30.如权利要求29所述的方法，其特征在于，通过逻辑组合来自多个掩膜的形状并且调整结果以避免出现亚光刻特征，从而根据所述数据生成所述第一掩膜上的所述阻挡区域。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/589,719 US6429482B1 (en) | 2000-06-08 | 2000-06-08 | Halo-free non-rectifying contact on chip with halo source/drain diffusion |
| US09/589,719 | 2000-06-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1434983A true CN1434983A (zh) | 2003-08-06 |
| CN1234175C CN1234175C (zh) | 2005-12-28 |
Family
ID=24359197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB018108105A Expired - Lifetime CN1234175C (zh) | 2000-06-08 | 2001-05-23 | 具有晕圈源极/漏极扩散的芯片上的无晕圈非整流接触 |
Country Status (13)
| Country | Link |
|---|---|
| US (2) | US6429482B1 (zh) |
| EP (1) | EP1290719B1 (zh) |
| JP (1) | JP3962326B2 (zh) |
| KR (1) | KR100500805B1 (zh) |
| CN (1) | CN1234175C (zh) |
| AT (1) | ATE425551T1 (zh) |
| AU (1) | AU2001258594A1 (zh) |
| DE (1) | DE60137927D1 (zh) |
| HK (1) | HK1055508A1 (zh) |
| MX (1) | MXPA02011791A (zh) |
| MY (1) | MY133983A (zh) |
| TW (1) | TW512434B (zh) |
| WO (1) | WO2001095369A2 (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100459076C (zh) * | 2005-08-24 | 2009-02-04 | 国际商业机器公司 | 改善体接触绝缘体上硅(soi)场效应晶体管的方法 |
| CN100459146C (zh) * | 2002-09-30 | 2009-02-04 | 英特尔公司 | 用于mosfet的铟-硼双盐注入 |
| CN103700702A (zh) * | 2013-12-30 | 2014-04-02 | 杭州电子科技大学 | 基于soi工艺的漏/源区介质(pn结)隔离前栅p-mosfet射频开关超低损耗器件 |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6692998B2 (en) * | 2000-11-30 | 2004-02-17 | International Business Machines Corporation | Integrated high quality diode |
| JP4676069B2 (ja) * | 2001-02-07 | 2011-04-27 | パナソニック株式会社 | 半導体装置の製造方法 |
| US6894324B2 (en) * | 2001-02-15 | 2005-05-17 | United Microelectronics Corp. | Silicon-on-insulator diodes and ESD protection circuits |
| US6867103B1 (en) * | 2002-05-24 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company | Method of fabricating an ESD device on SOI |
| JP2004311903A (ja) * | 2003-04-10 | 2004-11-04 | Oki Electric Ind Co Ltd | 半導体装置及び製造方法 |
| US7138318B2 (en) * | 2003-05-28 | 2006-11-21 | Advanced Micro Devices, Inc. | Method of fabricating body-tied SOI transistor having halo implant region underlying hammerhead portion of gate |
| US7375402B2 (en) * | 2004-07-07 | 2008-05-20 | Semi Solutions, Llc | Method and apparatus for increasing stability of MOS memory cells |
| US7224205B2 (en) * | 2004-07-07 | 2007-05-29 | Semi Solutions, Llc | Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors |
| US8247840B2 (en) * | 2004-07-07 | 2012-08-21 | Semi Solutions, Llc | Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode |
| US7683433B2 (en) | 2004-07-07 | 2010-03-23 | Semi Solution, Llc | Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors |
| US7651905B2 (en) * | 2005-01-12 | 2010-01-26 | Semi Solutions, Llc | Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts |
| US7898297B2 (en) * | 2005-01-04 | 2011-03-01 | Semi Solution, Llc | Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits |
| US7227204B2 (en) * | 2005-02-16 | 2007-06-05 | International Business Machines Corporation | Structure for improved diode ideality |
| US7612410B1 (en) * | 2005-08-08 | 2009-11-03 | Altera Corporation | Trigger device for ESD protection circuit |
| US7679029B2 (en) * | 2005-10-28 | 2010-03-16 | Cymer, Inc. | Systems and methods to shape laser light as a line beam for interaction with a substrate having surface variations |
| US7335563B2 (en) | 2005-11-09 | 2008-02-26 | International Business Machines Corporation | Rotated field effect transistors and method of manufacture |
| US7737500B2 (en) * | 2006-04-26 | 2010-06-15 | International Business Machines Corporation | CMOS diodes with dual gate conductors, and methods for forming the same |
| US7863689B2 (en) * | 2006-09-19 | 2011-01-04 | Semi Solutions, Llc. | Apparatus for using a well current source to effect a dynamic threshold voltage of a MOS transistor |
| US20080079051A1 (en) * | 2006-09-29 | 2008-04-03 | Luo Yuan | Varactor with halo implant regions of opposite polarity |
| JP2008117938A (ja) * | 2006-11-06 | 2008-05-22 | Toshiba Corp | 半導体記憶装置 |
| JP4329829B2 (ja) * | 2007-02-27 | 2009-09-09 | 株式会社デンソー | 半導体装置 |
| US7485520B2 (en) * | 2007-07-05 | 2009-02-03 | International Business Machines Corporation | Method of manufacturing a body-contacted finfet |
| US8110465B2 (en) | 2007-07-30 | 2012-02-07 | International Business Machines Corporation | Field effect transistor having an asymmetric gate electrode |
| US7932136B2 (en) * | 2008-04-24 | 2011-04-26 | International Business Machines Corporation | Source/drain junction for high performance MOSFET formed by selective EPI process |
| US8665570B2 (en) * | 2009-03-13 | 2014-03-04 | Qualcomm Incorporated | Diode having a pocket implant blocked and circuits and methods employing same |
| US7829939B1 (en) * | 2009-04-20 | 2010-11-09 | International Business Machines Corporation | MOSFET including epitaxial halo region |
| US7858469B1 (en) * | 2009-09-24 | 2010-12-28 | Altera Corporation | Method for forming a trigger device for ESD protection circuit |
| US9577079B2 (en) | 2009-12-17 | 2017-02-21 | Infineon Technologies Ag | Tunnel field effect transistors |
| US8426917B2 (en) * | 2010-01-07 | 2013-04-23 | International Business Machines Corporation | Body-tied asymmetric P-type field effect transistor |
| US8643107B2 (en) * | 2010-01-07 | 2014-02-04 | International Business Machines Corporation | Body-tied asymmetric N-type field effect transistor |
| US9006054B2 (en) | 2013-06-13 | 2015-04-14 | International Business Machines Corporation | Lateral diode compatible with FinFET and method to fabricate same |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5185280A (en) | 1991-01-29 | 1993-02-09 | Texas Instruments Incorporated | Method of fabricating a soi transistor with pocket implant and body-to-source (bts) contact |
| US5650340A (en) | 1994-08-18 | 1997-07-22 | Sun Microsystems, Inc. | Method of making asymmetric low power MOS devices |
| KR960026960A (ko) * | 1994-12-16 | 1996-07-22 | 리 패치 | 비대칭 저전력 모스(mos) 소자 |
| US5578506A (en) | 1995-02-27 | 1996-11-26 | Alliedsignal Inc. | Method of fabricating improved lateral Silicon-On-Insulator (SOI) power device |
| US5744372A (en) * | 1995-04-12 | 1998-04-28 | National Semiconductor Corporation | Fabrication of complementary field-effect transistors each having multi-part channel |
| US5936278A (en) | 1996-03-13 | 1999-08-10 | Texas Instruments Incorporated | Semiconductor on silicon (SOI) transistor with a halo implant |
| US5811857A (en) | 1996-10-22 | 1998-09-22 | International Business Machines Corporation | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications |
| US5952695A (en) | 1997-03-05 | 1999-09-14 | International Business Machines Corporation | Silicon-on-insulator and CMOS-on-SOI double film structures |
| US5923067A (en) | 1997-04-04 | 1999-07-13 | International Business Machines Corporation | 3-D CMOS-on-SOI ESD structure and method |
| US5985727A (en) * | 1997-06-30 | 1999-11-16 | Sun Microsystems, Inc. | Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface |
| US6051458A (en) * | 1998-05-04 | 2000-04-18 | Taiwan Semiconductor Manufacturing Company | Drain and source engineering for ESD-protection transistors |
| US6015993A (en) * | 1998-08-31 | 2000-01-18 | International Business Machines Corporation | Semiconductor diode with depleted polysilicon gate structure and method |
| US5959335A (en) | 1998-09-23 | 1999-09-28 | International Business Machines Corporation | Device design for enhanced avalanche SOI CMOS |
| US6194278B1 (en) * | 1999-06-21 | 2001-02-27 | Infineon Technologies North America Corp. | Device performance by employing an improved method for forming halo implants |
-
2000
- 2000-06-08 US US09/589,719 patent/US6429482B1/en not_active Expired - Lifetime
-
2001
- 2001-05-23 MX MXPA02011791A patent/MXPA02011791A/es active IP Right Grant
- 2001-05-23 EP EP01931903A patent/EP1290719B1/en not_active Expired - Lifetime
- 2001-05-23 AU AU2001258594A patent/AU2001258594A1/en not_active Abandoned
- 2001-05-23 WO PCT/GB2001/002273 patent/WO2001095369A2/en active IP Right Grant
- 2001-05-23 JP JP2002502812A patent/JP3962326B2/ja not_active Expired - Lifetime
- 2001-05-23 AT AT01931903T patent/ATE425551T1/de not_active IP Right Cessation
- 2001-05-23 KR KR10-2002-7016430A patent/KR100500805B1/ko not_active IP Right Cessation
- 2001-05-23 CN CNB018108105A patent/CN1234175C/zh not_active Expired - Lifetime
- 2001-05-23 DE DE60137927T patent/DE60137927D1/de not_active Expired - Lifetime
- 2001-06-05 TW TW090113613A patent/TW512434B/zh not_active IP Right Cessation
- 2001-06-06 MY MYPI20012657 patent/MY133983A/en unknown
-
2002
- 2002-07-01 US US10/064,305 patent/US6750109B2/en not_active Expired - Lifetime
-
2003
- 2003-10-28 HK HK03107752A patent/HK1055508A1/xx not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100459146C (zh) * | 2002-09-30 | 2009-02-04 | 英特尔公司 | 用于mosfet的铟-硼双盐注入 |
| CN100459076C (zh) * | 2005-08-24 | 2009-02-04 | 国际商业机器公司 | 改善体接触绝缘体上硅(soi)场效应晶体管的方法 |
| CN103700702A (zh) * | 2013-12-30 | 2014-04-02 | 杭州电子科技大学 | 基于soi工艺的漏/源区介质(pn结)隔离前栅p-mosfet射频开关超低损耗器件 |
| CN103700702B (zh) * | 2013-12-30 | 2016-08-24 | 杭州电子科技大学 | 漏/源区介质/pn结隔离前栅p-mosfet射频开关器件 |
Also Published As
| Publication number | Publication date |
|---|---|
| TW512434B (en) | 2002-12-01 |
| US20020149058A1 (en) | 2002-10-17 |
| JP3962326B2 (ja) | 2007-08-22 |
| DE60137927D1 (de) | 2009-04-23 |
| KR100500805B1 (ko) | 2005-07-12 |
| AU2001258594A1 (en) | 2001-12-17 |
| JP2003536251A (ja) | 2003-12-02 |
| EP1290719B1 (en) | 2009-03-11 |
| WO2001095369A2 (en) | 2001-12-13 |
| WO2001095369A3 (en) | 2002-05-16 |
| MY133983A (en) | 2007-11-30 |
| HK1055508A1 (en) | 2004-01-09 |
| CN1234175C (zh) | 2005-12-28 |
| MXPA02011791A (es) | 2003-04-10 |
| US6750109B2 (en) | 2004-06-15 |
| ATE425551T1 (de) | 2009-03-15 |
| EP1290719A2 (en) | 2003-03-12 |
| KR20030028478A (ko) | 2003-04-08 |
| US6429482B1 (en) | 2002-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1234175C (zh) | 具有晕圈源极/漏极扩散的芯片上的无晕圈非整流接触 | |
| US8455315B2 (en) | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch | |
| JP7023866B2 (ja) | 最適化層を有する炭化ケイ素金属－酸化物－半導体（ｍｏｓ）デバイスにおける電界シールディング | |
| JP2781504B2 (ja) | 改良されたブレークダウン電圧特性を有する半導体装置 | |
| KR100856818B1 (ko) | 불균일 전력 반도체 및 그 제조 방법 | |
| US20030137016A1 (en) | Lateral power MOSFET for high switching speeds | |
| US8183631B2 (en) | Semiconductor device | |
| US20050212050A1 (en) | Device for electrostatic discharge protection and method of manufacturing the same | |
| KR100510096B1 (ko) | 트렌치-게이트형 파워 mosfet | |
| US8049278B2 (en) | ESD protection for high voltage applications | |
| US7202527B2 (en) | MOS transistor and ESD protective device each having a settable voltage ratio of the lateral breakdown voltage to the vertical breakdown voltage | |
| US11658214B2 (en) | MOSFET device with undulating channel | |
| US20070246740A1 (en) | Transistor with increased esd robustness and related layout method thereof | |
| US6049112A (en) | Reduced capacitance transistor with electro-static discharge protection structure and method for forming the same | |
| US5847431A (en) | Reduced capacitance transistor with electro-static discharge protection structure | |
| US20230113308A1 (en) | Breakdown voltage improvement in vertical trench-gate devices | |
| EP4310888A1 (en) | A method of manufacturing a vertical oriented semiconductor device as well as a corresponding vertical oriented semiconductor device obtained by such a method | |
| KR101044383B1 (ko) | 정전기 방전 보호 반도체 소자 | |
| KR20070071069A (ko) | 카운트 드리프트 영역을 구비한 고전압 수평형 확산 모스트랜지스터 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20051228 |