CN1449021A - 自对准可编程相变存储器件及其制造方法 - Google Patents
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Abstract
本发明公开一种自对准可编程相变存储器件及其制造方法。该器件是以相变物质为基础的自对准及非易失性存储结构,此相变物质例如是硫族化合物,且存储器件被制作于集成电路上的非常小区域面积内。本发明的制造自对准存储单元的过程中只需要2个相关阵列掩模,以定义位线及字线。存储单元被定义于位线及字线的交叉处,且自对准过程中的位线及字线的宽度将定义存储单元的大小。存储单元包括选择组件、加热/阻挡层及相变存储元件,而存储单元位于位线及字线的交叉处。
Description
技术领域
本发明涉及一种非易失性(non-volatile)及高密度集成电路(integratedcircuit,IC)存储器件(memory devices),且特别涉及一种以例如是硫族化合物(chalcogenides)的相变物质(phase change)为基础的存储器件。
背景技术
硫族化合物已经被使用于集成电路存储器件的存储单元(cells)的形成过程中。此领域上的代表性先前专利包括Reinberg的美国专利No.5789758,Harshfield的美国专利No.6153890,Wolstenholme的美国专利No.6153890,Ovshinsky的美国重新领证专利No.RE37259(美国专利案号No.5687112的重新领证)及其它相关美国专利等等。
应用于集成电路存储器件上的硫族化合物为具有多种固态相(solid-state phase)的物质,且硫族化合物藉由加热的方式而被转换于此些相之间,加热的方式例如是提供电流(electrical current)或光学脉冲(optical pulses)。具有一硫族化合物元素的存储单元被排成阵列,此阵列藉由集成电路存储器件中的传统字线/位线(word lines/bit lines)寻址结构(addressing schemes)而能够被寻址。存储单元的状态由硫族化合物的大量电阻所决定。因为硫族化合物的不同固态相具有不同的电阻值,硫族化合物的大量电阻将指出所选择相状态中的硫族化合物的含量。
导致硫族化合物元素相变的具有足够电流密度的所提供电流的问题将反应在存储单元的设计上。典型地,相关复杂结构被使用以形成电流路径(path)中的小孔(pores),且电流路径与硫族化合物元素耦接。电流被浓缩经过小孔,以诱导硫族化合物中的局域高电流密度。复杂结构被使用以形成此些孔,且基于硫族化合物的存储单元的其它方面已经需求相关大型单元体积以执行。此外,复杂结构能够影响存储器件的可靠度。大型单元体积局限存储器件的密度,且增加存储器件的成本。同样地,制造业的可靠度以存储器件的成功商业应用为关键点。高密度及自对准存储单元已经被制造成储存技术的其它型式,如Johnson的美国专利No.6185122所提及的垂直堆叠(vertically stacked)的非易失性内存。此外,如此高密度技术已经没有被应用于相变存储单元。
因此,如何能够提供较小体积的相变存储单元结构及装置是有需要的。此外,如何能够提供具有效率及可靠结构的存储器件的制造方法亦是有需要。
发明内容
因此,本发明的目的在于提供一种以例如是硫族化合物(chalcogenides)的相变物质(phase change)为基的自对准(self-aligned)及非易失性(non-volatile)存储结构,并且提供一使用此存储结构以制造集成电路组件的方法。此存储结构能够被制作于集成电路上的非常小区域内。优选地,阵列内的每一个存储单元(memory cell)所需求的区域面积约为4F2,而F等于制造过程的最小线宽。因此,当制造过程的最小线宽为0.1(μm)时,存储单元所需求的区域面积约为0.04(μm2)。
此外,此制造过程将产生自对准存储单元,而自对准存储单元只需要2个用以定义位线(bit lines)及字线(word lines)的相关阵列掩模(array-relatedmasks)。存储单元被定义于位线及字线的交叉处,且自对准过程中的字线及位线的宽度将定义存储单元的大小。
本发明的存储结构中相变物质包括硫族化合物,且相变物质的使用将提供一高密度、非易失性及可编程存储器件。
根据本发明的目的,提出一种存储器件的制造方法。首先,形成一多层膜(multi-layer film)于一衬底(substrate)上,多层膜具有一第一导电层(conductor layer)、至少一用以形成一选择组件(selection device)的物质层及至少一用以形成一相变存储元件(phase memory element)的物质层。然后,定义多个具有一第一图案(pattern)的第一线(lines)于多层膜上并进行蚀刻,以形成多个第一缺口(gaps)于此些第一线之间及衬底上,此些第一线以一第一方向延伸于多层膜上。接着,填充一绝缘物质于此些第一线之间的此些第一缺口中。然后,形成一第二导电层于此些第一线上及绝缘物质上,以形成一多层复合物(composite)。接着,定义多个具有一第二图案的第二线于多层复合物上并进行蚀刻,以形成多个第二缺口于此些第二线之间及第一导电层上,此些第二线以垂直第一方向的一第二方向延伸于多层复合物上,使得此些第二线与此些第一线相交。其中,第一导电层所形成的此些第一线及第二导电层所形成的此些第二线之间延伸着多个自对准存储单元(self-aligned memory cells)。各存储单元具有用以形成一选择组件的物质层及用以形成一相变存储元件的物质层,且用以形成一选择组件的物质层及用以形成一相变存储元件的物质层与第一导电层中的此些第一线及第二导电层中的此些第二线电连接。
其中,用以形成一选择组件的物质层包括一具有p型掺杂物的第一多晶硅(polysilicon)层及一具有n型掺杂物的第二多晶硅层,并用以形成一二极管(diode),且用以形成一相变存储元件的物质层为一硫族化合物层。此外,本发明可以形成一中间层(intermediate layer)于用以形成一选择组件的物质层及用以形成一相变存储元件的物质层之间。另外,中间层可以当作位于选择组件及相变物质之间的电致迁移(electromigration)及扩散(diffusion)的阻挡层(barrier)。
用以形成一相变存储元件的物质层具有一与中间层进行热对流的相变物质,相变物质包括一具有一较低电阻的第一状态(state)及一具有一较高电阻的第二状态,其中,中间层具有一大于位于第二状态的相变物质的较高电阻的第一电阻。因此,中间层将作为一电阻加热板,用以帮助邻接于中间层的相变物质产生相变。
根据本发明的目的,提出一种新的存储器件,包括一衬底、多个第一导电线、多个第二导电线及多个存储单元。
此些第一导电线以一第一方向延伸于衬底上,此些第二导电线以垂直第一方向的一第二方向延伸于此些第一导电线,且此些第二导电线与此些第一导电线相交。此些存储单元位于此些第一导电线与此些第二导电线的相交处,而此些存储单元与此些第一导电线及此些第二导电线电连接。且各存储单元具有一自对准结构,此自对准结构包括一选择组件及一相变存储元件。
选择组件包括一二极管,而相变存储元件包括一硫族化合物,且硫族化合物具有一均匀厚度于此些第一导电线与此些第二导电线的相交处。
其中,自对准结构包括可形成选择组件的第一多晶硅层及第二多晶硅层、一中间加热/阻挡层及一相变物质层。中间加热/阻挡层包括一电致迁移及扩散的阻挡,而中间加热/阻挡层具有一第一电阻,且相变物质层包括一具有一较低电阻的第一状态及一具有一较高电阻的第二状态。第一电阻大于位于第二状态的相变物质层的较高电阻,使得中间加热/阻挡层将作为一加热板,以帮助邻接于中间加热/阻挡层的相变物质层产生相变。
在不同的实施例中,相变存储元件藉由设定响应于编程电流(programming current)或其它编程刺激的超过2个的体积(bulk)电阻状态,而可以储存一位以上。
本发明的存储阵列形成于衬底上,在某些实施例中,而集成电路组件的衬底上具有一绝缘层,存储阵列被制造于绝缘层上,且存储阵列与衬底内的集成电路系统(integrated circuitry)接触。优选地,衬底内的集成电路系统包括存储阵列的支撑电路系统,而本发明藉由使用标准互补型金属氧化物半导体(complementary metal-oxide semiconductor,CMOS)方式以形成地址译码器(address decoder)、检测放大器(sense amplifier)、电压源(voltage source)及其它组件于支撑电路系统中。
本发明可以提供一存储单元,用以结合多晶硅结(junction)及硫族化合物存储元件,且本发明可以提供制造具有存储单元的存储器件的方法。本发明可以施加合适电压及电流于存储器件上,使得存储器件可以被编程及消除,用以改变硫族化合物存储元件的电阻。本发明只需要2个相关阵列掩模以制造存储单元,而所产生的存储单元自对准地布满阵列的位线及字线。此外,阵列内的每一个存储单元(memory cell)所需求的区域面积约为4F2,而F等于制造过程的最小线宽。
为让本发明的上述目的、特征、和优点能更明显易懂,下文特举一优选实施例,并配合所附图式,作详细说明如下。
附图说明
图1显示的是依照本发明的优选实施例的集成电路存储器件的框图;
图2显示的是依照本发明的优选实施例的自对准相变单元存储阵列的电路线路分布的示意图;
图3~10显示的是依照本发明的优选实施例的自对准相变单元存储阵列的制造方法的流程图;
图11显示的是图10的存储阵列的线路分布的示意图;以及
图12A~12C显示的是本发明的自对准存储单元的操作流程图。
附图中的附图标记说明如下:
5:自对准相变单元存储阵列
10、11:y-译码器及输入驱动器电路系统
12、13:x-译码器及输出检测放大器电路系统
14:编程及消除电压产生器电路
20、21、140、141、142、143、144:位线
22、23、145、146、147、148、149:字线
24、25、26、27、130:存储单元
28:选择组件 29:加热/阻挡层
30:相变层 99:多层膜
100:衬底 101:绝缘层
102:位线物质层 103:第一多晶硅层
104:第二多晶硅层 105:中间加热/阻挡层
106:硫族化合物层 120、121、122:第一线
123:第一缺口 125:氧化物层
126:位线导电层 127、128:第二线
129:第二缺口 131:绝缘物层
135、136、137:第一导电线 138、139:第二导电线
150、151、152、153、154、155、156、157、158、159:接触结构
200:选择组件 201:加热/阻挡层
202:相变元件 203:相变区域
205、206、207、208:区域
具体实施方式
请参照图1,其显示的是依照本发明的优选实施例的集成电路(integrated circuit,IC)存储器件(memory device)的框图。在图1中,本发明的集成电路存储器件包括一自对准相变单元存储阵列(self-alignedphase change cell memory array)5及一衬底(substrate),此衬底上所配置的电路系统(circuitry)将维持自对准相变单元存储阵列5。在发明中,电路系统包括地址译码器(address decoders)、输入驱动器(input drivers)及输出驱动器(output drivers)。因此,y-译码器及输入驱动器电路系统10及11配置于自对准相变单元存储阵列5的左右两边附近,x-译码器及输出检测放大器(amplifier)电路系统12及13配置于自对准相变单元存储阵列5的上下两边附近。其中,本发明的集成电路上又包括编程及消除电压产生器电路(program and erase yoltage generator circuit)14,而编程及消除电压产生器电路或许具有电荷泵浦(charge pumps)、其它高电压或负电压产生器,用以编程及消除相变单元。
在本发明中,集成电路系统可以采用标准互补型金属氧化物半导体(complementary metal-oxide semiconductor,CMOS)技术。其它包括先进(advanced)物质及程序的制造技术或许可以被使用于衬底中的集成电路系统。另外,电路系统的线路分布(layout)或许具有可产生自对准相变单元存储阵列5的逻辑控制电路(logic control circuit)。
请参照图2,其显示的是依照本发明的优选实施例的自对准相变单元存储阵列的电路线路分布的示意图。请参考图1,在图2中,自对准相变单元存储阵列5包括位线(bit lines)20及21、字线(word lines)22及23,位线20及21、字线22及23被排列并互相交叉于存储单元(memory cells)24、25、26及27。在此些存储单元中,以存储单元27为例说明,存储单元27具有选择组件(selection device)28、加热/阻挡层(heating/barrier layer)29及相变层(phase change layer)30。其中,选择组件28具有隔离二极管(isolation diode),而相变层30具有硫族化合物(chalogenide)存储元件。当本发明施加偏压于所选择存储单元附近所交叉的位线及字线时,选择组件的隔离二极管将具有导电性(conductive);当与其它存储单元耦接的位线及字线被反向施加偏压时,选择组件的隔离二极管将不具有导电性。在图2中,位线20及21与输出检测放大器电路系统耦接,而字线22及23与输入驱动器耦接。
请参照图3~10,其显示的是依照本发明的优选实施例的自对准相变单元存储阵列的制造方法的流程图。首先,在图3中,形成一多层膜(multilayerfilm)99于一衬底100上,而衬底100包括一具有上述的集成电路系统的半导体,且衬底100上配置一绝缘层(insulator)101。其中,绝缘层101含有二氧化硅(silicon dioxide,SiO2),而绝缘层101的物质及厚度可被自由选定,以致于自对准相变单元存储阵列可以与位于下面的集成电路系统隔离。此外,多层膜99具有位线物质层102、第一多晶硅层(polysilicon)103、第二多晶硅层104、中间(intermediate)加热/阻挡层105及硫族化合物层106。
位线物质层102可以包括钨(tungsten,W),而位线物质层102的厚度约为150~600纳米(nanometers,nm),且本发明可以使用化学气相沉积(chemical vapor deposition,CVD)的方式形成位线物质层102。当然,其它不同类型的物质亦可以被使用以构成位线物质层102,例如重度掺杂多晶硅(heavily doped polysilicon)、其它高融点(melting point)金属或化合物,如钽(Ta)、铂(Pt)、氮化钛(TiN)、氮化钽(TaN)、硅化钨(WSi)及合金(alloy)等等。
第一多晶硅层103具有n-掺杂多晶硅,而第一多晶硅层103的厚度约为100~600(nm)。本发明可以使用CVD方式、等离子体强化(plasma-enhanced)CVD方式或溅镀(sputtering)方式形成第一多晶硅层103,而本发明亦可使用n-型施主(donor)进行多晶硅的掺杂以形成第一多晶硅层103,且n-型施主可以是砷(arsenic)及磷(phosphorus)。同样地,第二多晶硅层104具有p+掺杂多晶硅,而第二多晶硅层104的厚度约为100~400(nm)。本发明可以使用CVD方式、等离子体强化CVD方式或溅镀方式形成第二多晶硅层104。而本发明亦可使用p+型施主进行多晶硅的掺杂以形成第二多晶硅层104,且p+型施主可以是硼(B)、镓(Ga)或铟(indium)。其中,第一多晶硅层103及第二多晶硅层104以二极管的方式形成选择组件,用以被选出以执行选择组件的两多晶硅层能够形成不同型式的结(junctions)。除了p+/n-结之外,其它如n+/p-结,p+/本征(intrinsic)/n-结,n+/本征/p-结,p+/n+结,p+/本征/n+结及Schottky(肖特基)结也是可以被形成于两多晶硅层之间。甚至,其它选择组件结构或许可以被应用于本发明中。
中间加热/阻挡层105具有一薄膜物质,而中间加热/阻挡层105的厚度约为20~200(nm),本发明可以使用CVD或溅镀方式形成中间加热/阻挡层105。在本发明中,中间加热/阻挡层105是一可加热相变物质的加热元件及一位于选择组件及相变物质之间的电致迁移(electromigration)及扩散(diffusion)的阻挡。另外,中间加热/阻挡层105不能够与相变物质及选择组件发生反应。在高电阻(resistance)的情况下,中间加热/阻挡层105的电阻大于相变物质的电阻。同理,中间加热/阻挡层105可以当作一加热板(plate),以改变邻近于中间加热/阻挡层105的相变物质的相。合适的金属包括有钨化钛(TiW)、氮化铝钛(TiAlN)、钽(Ta)、钼(Mo)等等。
与相变物质的高电阻率(resistivity)相比较时,其它许多物质的特征在于相当高电阻,并且良好阻挡亦可以被使用。中间加热/阻挡层105可以选自于一化合物,而此化合物具有钛(Ti)、钒(V)、铬(Cr)、锆(Zr)、铌(Nb)、M、铪(Hf)、钽(Ta)及钨(W)的中任何一种元素与硼(B)、碳(C)、氮(N)、铝(Al)、硅(Si)、磷(P)及硫(S)的中任2种或多种元素。在美国重新领证专利No.RE37259中,第13段的第31行至第14段的第4行之间公开出可以当作阻挡的物质。所以,中间加热/阻挡层105包括一具有阻挡特性的物质及一可当作加热板的物质。优选地,中间加热/阻挡层105只具有一可以同时实现加热及阻挡的物质。
图3的多层膜99的最上层由相变物质所构成,而在本发明中,多层膜99的最上层以硫族化合物层106为例作说明。当物质的薄膜被当作上电极或下电极时,硫族化合物层106亦可被包括在内。虽然本发明的相变物质由硫族化合物所构成,但本发明亦可以使用其它类型的相变物质。本发明的硫族化合物层106的厚度约为5~200(nm),而优选的厚度为20~40(nm),且本发明使用溅镀方式形成硫族化合物层106。其中,包括有硫族化合物的代表性相变物质被公开于美国重新领证专利No.RE37259中。
接着,使用光致抗蚀剂(photoresist)以定义具有第一掩模图案(maskpattern)的第一线120、121及122,使得第一线120、121及122形成于多层膜99上,如图4所示。第一线120、121及122彼此有间隔地互相平行并沿一第一方向延伸于多层膜99上,第一线120、121及122用以定义存储阵列的位线。
然后,使用反应离子蚀刻(reactive ion etching)方式进行蚀刻,以去除未被第一线120、121及122所覆盖的多层膜99的部分结构,并且形成多个第一缺口(gaps)123于绝缘层101上,如图5所示。
接着,填充氧化物层125或其它绝缘物质于第一缺口123中,如图6所示。其中,本发明可以使用高密度等离子体CVD方式或其它可填充狭窄缺口的沉积方式以填充氧化物125或其它绝缘物质于第一缺口123中。
接着,形成字线导电层126于多层膜99及氧化物层125上,以形成一多层复合物(composite),如图7所示。字线导电层126具有一导电物质,如W,Ta,Pt,TiN,TaN,Wsi或重度掺杂多晶硅,且本发明使用溅镀或CVD的方式形成字线导电层126。
然后,定义具有第二掩模图案的第二线127及128,使得第二线127及128形成于字线导电层126上,如图8所示。第二线127及128彼此有间隔地互相平行并沿与第一方向垂直的一第二方向延伸于字线导电层126上。
接着,使用反应离子蚀刻方式进行蚀刻,以去除未被第二线127及128所覆盖的字线导电层126、氧化物层125、第一多晶硅层103、第二多晶硅层104、中间加热/阻挡层105及硫族化合物层106的部分结构。形成多个第二缺口129于位线物质层102上,如图9所示。在图9中,存储单元130形成于位线及字线的交叉处,位线及字线分别位于相互平行的两平面中,但互相交叉于存储阵列的平面上。其中,因为本发明使用相同掩模步骤定义存储单元130的侧边及字线与位线,故本发明将以自对准制造方式形成存储单元130、位线及字线。
然后,填充绝缘物层131或其它氧化物于第二缺口129中,如图10所示。其中,本发明可以使用任何高密度等离子体CVD方式或其它可填充狭窄缺口的沉积方式以填充绝缘物层131或其它氧化物于第二缺口129中。
图10显示存储阵列的基本结构。存储阵列包括第一导电线135、136及137及第二导电线138及139。第二导电线138及139分别与第一导电线135、136及137交叉于第一导电线135、136及137上。以存储单元130为例作说明,存储单元130位于第一导电线及第二导电线的交叉处,而存储单元130与第一导电线及第二导电线电连接。所以,存储单元具有自对准结构,而此自对准结构包括第一多晶硅层及第二多晶硅层所形成的选择组件、一中间加热/阻挡层及一硫族化合物层,且选择组件、中间加热/阻挡层及硫族化合物层直立地排列于第一导电线及第二导电线的交叉处。
请参照图11,其显示的是图10的存储阵列的线路分布的示意图。在图11中,位线140、141、142、143及144纵向地排列于存储阵列中,字线145、146、147、148及149横向地排列于存储阵列中。位线140、141、142、143及144分别延伸出接触结构(contact structures)150、151、152、153及154,字线145、146、147、148及149分别延伸出接触结构155、156、157、158及159。接触结构具有钨插塞(plugs),且钨插塞由绝缘层101延伸到衬底的集成电路系统。
请参照图12A~12C,其显示的是本发明的自对准存储单元的操作流程图。首先,在图12A中,本发明的基本存储单元包括选择组件200、加热/阻挡层201及相变元件202。接着,在图12B中,当存储单元接受一外来的电流时,加热/阻挡层201将加热以达到相变元件202的相变温度。相变元件202包括一具有较低电阻的第一固态相及一具有较高电阻的第二固态相。邻近于加热/阻挡层201的相变区域203中的相变元件202的物质改变相状态。相变元件202的体积电阻指出具有第一固态相及第二固态相的相变元素202的相对物质含量。藉由控制相变,数据可以储存于相变元件202中。
然后,在图12C中,存储单元包括选择元素200、加热/阻挡层201及相变元件202,本发明可以控制相变以获得2种以上的存储状态。举例而言,在状态1时,区域205的物质处于高电阻状态。在状态2时,区域205及206的物质处于高电阻状态。在状态3时,区域205、206及207的物质处于高电阻状态。在状态4时,区域205、206、207及208的物质处于高电阻状态。因此,本发明具有可储存于一存储单元内的4种不同电阻状态,且此4种不同状态可以表示成一存储单元内的2个位。
本发明可以由图10明了存储器件的基本操作流程。上层金属线可以当作字线,而下层金属线可以当作位线,且p+/n-多晶硅结可以当作二极管,用以隔离/选择每一存储单元。当本发明编程或消除一存储单元时,字线及位线之间将形成一合适电压,用以提供足够的电流。此电流将穿透通过硫族化合物及加热/阻挡层,以产生热量。藉由控制加热速度,本发明可以控制硫族化合物的固态相,用以建立硫族化合物的体积电阻所指示的存储状态。当读取存储单元时,电流将由字线出发而经过硫族化合物、加热/阻挡层及p+/n-结,且最后到达位线。藉由区别特殊存储单元的电压或电流级数,数据将可以被善加利用。
本发明的存储阵列可以使用于单次(one-time)编程非易失性内存、于制造时编程的非易失性内存及适合进行多次编程与消除循环的电可消除及可编程随机存取内存(random access memory)。
需要注意的是,存储阵列内的每一个存储单元所需求的区域面积约为4F2,而F等于制造过程的最小线宽。因此,当制造过程的最小线宽为0.1(μm)时,存储单元所需求的区域面积约为0.04(μm2)。
本发明上述实施例所公开的自对准可编程相变存储器件可以提供较小体积的相变存储单元结构及装置,不再局限存储器件的密度,且减少存储器件的生产成本。
综上所述,虽然本发明已以一优选实施例公开如上,但是其并非用以限定本发明,本领域技术人员在不脱离本发明的精神和范围的情况下,可作各种更动与润饰,因此本发明的保护范围当以所附的权利要求所确定的为准。
Claims (34)
1.一种存储器件的制造方法,包括:
形成一多层膜于一衬底上,该多层膜具有一第一导电层、至少一用以形成一选择组件的物质层及至少一用以形成一相变存储元件的物质层;
定义多个具有一第一图案的第一线于该多层膜上并进行蚀刻,以形成多个第一缺口于该些第一线之间及该衬底上,该些第一线以一第一方向延伸于该多层膜上;
填充一绝缘物质于该些第一线之间的该些第一缺口中;
形成一第二导电层于该些第一线上及该绝缘物质上,以形成一多层复合物;以及
定义多个具有一第二图案的第二线于该多层复合物上并进行蚀刻,以形成多个第二缺口于该些第二线之间及该第一导电层上,该些第二线以垂直该第一方向的一第二方向延伸于该多层复合物上,使得该些第二线与该些第一线相交,其中,该第一导电层所形成的该些第一线及该第二导电层所形成的该些第二线之间延伸着多个自对准存储单元,各该存储单元具有该用以形成一选择组件的物质层及该用以形成一相变存储元件的物质层。
2.如权利要求1所述的制造方法,其中该衬底上配置一绝缘层。
3.如权利要求1所述的制造方法,其中该衬底上配置一具有一绝缘层的集成电路组件。
4.如权利要求1所述的制造方法,其中该用以形成一选择组件的物质层包括一具有p型掺杂物的第一多晶硅层及一具有n型掺杂物的第二多晶硅层,并用以形成一二极管。
5.如权利要求1所述的制造方法,其中该用以形成一相变存储元件的物质层是一硫族化合物层。
6.如权利要求5所述的制造方法,其中该硫族化合物层覆盖该用以形成一选择组件的物质层。
7.如权利要求6所述的制造方法,其中该硫族化合物层及该用以形成一选择组件的物质层之间具有一加热/阻挡元件。
8.如权利要求1所述的制造方法,其中该自对准存储单元又包括一具有一第一电阻的中间加热/阻挡层,该用以形成一相变存储元件的物质层具有一与该中间加热/阻挡层进行热对流的相变物质,该相变物质包括一具有一较低电阻的第一状态及一具有一较高电阻的第二状态,其中,该第一电阻是大于位于该第二状态的该相变物质的该较高电阻。
9.如权利要求8所述的制造方法,其中该中间加热/阻挡层具有一扩散及电致迁移的阻挡层。
10.一种存储器件,包括:
一衬底;
多个第一导电线,其以一第一方向延伸于该衬底上;
多个第二导电线,其以垂直该第一方向的一第二方向延伸于该些第一导电线,且该些第二导电线与该些第一导电线相交;以及
多个存储单元,其位于该些第一导电线与该些第二导电线的相交处,而该些存储单元与该些第一导电线及该些第二导电线电连接,且各该存储单元具有一自对准结构,该自对准结构包括一选择组件及一相变存储元件。
11.如权利要求10所述的存储器件,其中该存储单元包括至少一用以作为该选择组件的物质层、至少一用以形成一加热/阻挡元件的物质层及至少一用以作为该相变存储元件的物质层。
12.如权利要求10所述的存储器件,其中该相变存储元件包括一硫族化合物。
13.如权利要求12所述的存储器件,其中该硫族化合物具有一均匀厚度于该些第一导电线与该些第二导电线的相交处。
14.如权利要求10所述的存储器件,其中该存储单元包括一用以作为该选择组件的物质层、一具有一第一电阻的中间物质层及一邻接于该中间物质层的相变物质层,该相变物质层包括一具有一较低电阻的第一状态及一具有一较高电阻的第二状态,其中,该第一电阻是大于位于该第二状态的该相变物质层的该较高电阻。
15.如权利要求14所述的存储器件,其中该中间层具有一用以产生扩散及电致迁移的阻挡层。
16.如权利要求14所述的存储器件,其中该用以作为一选择组件的物质层包括一具有p型掺杂物的第一多晶硅层及一具有n型掺杂物的第二多晶硅层,并用以形成一二极管。
17.如权利要求10所述的存储器件,其中该存储单元包括至少一用以作为该选择组件的物质层、至少一用以形成一中间加热/阻挡元件的物质层及至少一用以作为该相变存储元件的物质层,其中,该用以作为该相变存储元件的物质层包括一硫族化合物层。
18.如权利要求17所述的存储器件,其中该硫族化合物层覆盖该用以作为该选择组件的物质层。
19.如权利要求17所述的存储器件,其中该用以作为该选择组件的物质层包括一具有p型掺杂物的第一多晶硅层及一具有n型掺杂物的第二多晶硅层,并用以形成一二极管。
20.如权利要求10所述的存储器件,其中该衬底上配置一绝缘层。
21.如权利要求10所述的存储器件,其中该衬底上配置一具有一绝缘层的集成电路组件。
22.如权利要求10所述的存储器件,其中该相变存储元件藉由设定响应于编程电流的超过2个的体积电阻状态,而可以储存一个位以上。
23.一种存储器件的制造方法,包括:
形成一多层膜于一衬底上,该多层膜包括一第一导电层、一具有一第一电阻的中间加热/阻挡层、一硫族化合物层及至少一用以形成一选择组件的物质层,该硫族化合物层包括一具有一较低电阻的第一状态及一具有一较高电阻的第二状态,该第一电阻是大于位于该第二状态的该硫族化合物层的该较高电阻;
定义多个具有一第一图案的第一线于该多层膜上并进行蚀刻,以形成多个第一缺口于该些第一线之间及该衬底上,该些第一线以一第一方向延伸于该多层膜上;
填充一绝缘物质于该些第一线之间的该些第一缺口中;
形成一第二导电层于该些第一线上及该绝缘物质上,以形成一多层复合物;以及
定义多个具有一第二图案的第二线于该多层复合物上并进行蚀刻,以形成多个第二缺口于该些第二线之间及该第一导电层上,该些第二线以垂直该第一方向的一第二方向延伸于该多层复合物上,使得该些第二线与该些第一线相交,其中,该第一导电层所形成的该些第一线及该第二导电层所形成的该些第二线之间延伸着多个自对准存储单元,各该存储单元具有该用以形成一选择组件的物质层及该用以形成一相变存储元件的物质层。
24.如权利要求23所述的制造方法,其中该衬底上配置一绝缘层。
25.如权利要求23所述的制造方法,其中该衬底上配置一具有一绝缘层的集成电路组件。
26.如权利要求23所述的制造方法,其中该用以形成一选择组件的物质层包括一具有p型掺杂物的第一多晶硅层及一具有n型掺杂物的第二多晶硅层,并用以形成一二极管。
27.如权利要求23所述的制造方法,其中该中间加热/阻挡层具有一扩散及电致迁移的阻挡层。
28.一种存储器件,包括:
一衬底,该衬底上配置一集成电路系统及一绝缘层;
多个第一导电线,其以一第一方向延伸于该衬底上;
多个第二导电线,其以垂直该第一方向的一第二方向延伸于该些第一导电线,而该些第二导电线与该些第一导电线相交,且集成电路系统接触该些第一导电线及该些第二导电线的交叉处;以及
多个存储单元,其位于该些第一导电线与该些第二导电线的相交处,而该些存储单元与该些第一导电线及该些第二导电线电连接,各该存储单元具有一自对准结构,且该自对准结构包括一选择组件、一中间层及一硫族化合物存储元件。
29.如权利要求28所述的存储器件,其中该硫族化合物存储元件具有一均匀厚度于该些第一导电线与该些第二导电线的相交处。
30.如权利要求28所述的存储器件,其中该中间层具有一第一电阻,该硫族化合物存储元件包括一硫族化合物物质,该硫族化合物物质包括一具有一较低电阻的第一状态及一具有一较高电阻的第二状态,其中,该第一电阻是大于位于该第二状态的该硫族化合物物质的该较高电阻。
31.如权利要求28所述的存储器件,其中该中间层具有一加热元件。
32.如权利要求28所述的存储器件,其中该中间层具有一扩散及电致迁移的阻挡层。
33.如权利要求28所述的存储器件,其中该选择组件包括具有p型掺杂物的第一多晶硅层及具有n型掺杂物的第二多晶硅层,并用以形成二极管。
34.如权利要求28所述的存储器件,其中该硫族化合物存储元件藉由设定响应于编程电流的超过2个的体积电阻状态,而可以储存一个位以上。
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Also Published As
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CN1218384C (zh) | 2005-09-07 |
US20030186481A1 (en) | 2003-10-02 |
TW200304689A (en) | 2003-10-01 |
US6750101B2 (en) | 2004-06-15 |
US6579760B1 (en) | 2003-06-17 |
JP2003303941A (ja) | 2003-10-24 |
TW586186B (en) | 2004-05-01 |
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