CN1466218A - RAM made of carbon nano tube and preparation method thereof - Google Patents
RAM made of carbon nano tube and preparation method thereof Download PDFInfo
- Publication number
- CN1466218A CN1466218A CNA021238642A CN02123864A CN1466218A CN 1466218 A CN1466218 A CN 1466218A CN A021238642 A CNA021238642 A CN A021238642A CN 02123864 A CN02123864 A CN 02123864A CN 1466218 A CN1466218 A CN 1466218A
- Authority
- CN
- China
- Prior art keywords
- grid
- electrode
- tube
- carbon nano
- insulating barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
This invention relates to a carbon nano transistor random memory including Si as the substrate with SiO2 insulation layer, carbon nm tube, grid and electrode on it, the grid is placed in a groove in SiO2 insulation layer, Al deposited on it becomes Al2O3 insulation layer after surface oxidation, the grid is connected to a resistor linking to a constant voltage source. The electrode is parallel to the grid above or below the carbon nm tube at both sides of the grid, the first one connects to the earth, the second links to switch and the grid is connected with the secone electrode in short, a carbon nm tube is vertical to the grid and two independent electrodes, plainly, placed on the surface of SiO2 layer contacting with surfaces of Al2O2 and electrodes.
Description
Technical field
The invention belongs to memory area, particularly a kind of random asccess memory and preparation method based on carbon nano-tube.
Background technology
Human society has developed into " information age ", and various information mediums such as TV, network etc. have become indivisible important component part in people's daily life.And among these medium, we none can not find the shadow of the Digital Logical Circuits of being made up of semiconductor transistor.Not just medium around looking around, almost can find digital circuit in Sheng Huo each corner." digitlization " become human a kind of life style.The mankind are brought into " information age " just based on traditional " metal---oxide---semiconductor field " digital integrated circuit (MOSFET).MOSFET utilizes the principle of the P-N knot of conventional P N-type semiconductor N and N type semiconductor formation to realize its function.Integrated circuit is to utilize the semiconductor processing technologies such as photoetching, iontophoretic injection, doping will be based on the circuit production of MOSFET on chip piece.Present stage, utilize 0.13 micron process technology a forty-two million transistor can be integrated on one 1 square centimeter the chip.In various Digital Logical Circuits, random asccess memory is an important part.Do not have random asccess memory, Digital Logical Circuits just can't realize its function.Effect just because of random asccess memory is so important, so the development of random asccess memory has been subjected to general attention in all semiconductor device.Per 2 years of other semiconductor product beyond the memory is more of new generation, and memory then is per 18 months generation.The speed of its update is higher than other semiconductor product.
Along with people to the speed of device and improving constantly of dimensional requirement, the memory that traditional semiconductor technology is made has exposed all deficiencies.As: conventional semiconductor processing is used methods such as photoetching, is subjected to working media---and the influence of light wavelength, size of devices are difficult to further dwindle.With the metal oxide semiconductor field effect tube is example: minimum dimension of picture is that the area of 256,000,000 DRAM of 0.25 μ m is approximately 0.72 μ m
2, the area that minimum figure is of a size of the 1 gigabit DRAM of 0.18 μ m is approximately 0.32 μ m
2, the area that minimum figure is of a size of the 4 gigabit DRAM of 0.13 μ m is approximately 0.18 μ m
2, and the area that minimum figure is of a size of the 16 gigabit DRAM of 0.1 μ m is approximately 0.1 μ m
2Under traditional technology, 0.1 μ m has almost reached the limit.If further reduction of device size, it is imperative to seek a kind of new method.And, being subjected to the restriction of Physics of Semiconductor Devices, the speed that memory writes and reads also is difficult to further improve.
All restrictions of traditional semiconductor memory, people turn to another kind of novel material---carbon nano-tube to sight.Carbon nano-tube becomes the preferred material of electronic device of future generation with its distinctive electrology characteristic.
People such as calendar year 2001 Adrian Bachtold (" science " SCIENCE, 2001, Vol 294,1317) produce the memory based on carbon nano-tube.The principle of this carbon nano-tube memory is the conducting state by the grid controlling carbon nanotube, and keeps this state, thereby realizes the function of stored information.But, this carbon nano-tube memory by two independently carbon nano-tube form, this structure to the design and making brought many difficulties.
At first, because the circuit structure more complicated, the making of circuit will increase the difficulty of circuit production through a series of as operations such as photoetching, plated film and oxidations, is unfavorable for the integrated of circuit.Secondly and since circuit by two independently carbon nano-tube forms, how to have only the carbon nano-tube while of several nanometers to be in place accurately two diameters is the biggest problem that face in the circuit production.In the making based on the device of carbon nano-tube and circuit, people are being perplexed in the accurate placement of carbon nano-tube always.Present stage, people generally use atomic force microscope (AFM) or scanning tunnel microscope (STM) control single-root carbon nano-tube to drag it to the position, perhaps use special methods such as " random orientation methods ".Shortcomings such as all efficient end of these methods, difficult acquisition excellent contact.In above this " double-carbon nanotube memory ", the placement meeting of two carbon nano-tube brings very big difficulty for the making of circuit.
Summary of the invention
The objective of the invention is shortcoming for the circuit structure more complicated that reduces existing carbon nano-tube memory; With reduce in making the manufacture difficulty that reaches accurate placement of carbon nano-tube based on the device of carbon nano-tube; In order to obtain the device good Ohmic contact, thereby provide a kind of random asccess memory based on single-root carbon nano-tube.
Carbon nano-tube random asccess memory provided by the invention comprises that with Si as substrate, this substrate is provided with a SiO
2Insulating barrier, carbon nano-tube, grid and electrode; It is characterized in that: described grid is positioned at SiO on the Si substrate
2Among the groove in the insulating barrier, its interior depositing Al and the Al that forms through surface oxidation
2O
3Insulating barrier, grid also is connected with a resistance, and this resistance is connected with constant pressure source; Described electrode comprises two independently electrodes, two electrodes are parallel to the both sides that grid is arranged on grid, be positioned on the carbon nano-tube or under, its second electrode also has a section vertical with grid of direction, this section contacts with grid, first electrode grounding wherein, second electrode is connected with switch, and grid links to each other with the short circuit on substrate of second electrode simultaneously; Carbon nano-tube is perpendicular to grid and two electrode independently, the straight SiO that is placed on
2On the surface of insulating barrier, and and Al
2O
3Surface of insulating layer and electrode surface contact.
It is respectively to cover a layer of precious metal at the carbon nano-tube two ends that described electrode is provided with on the carbon nano-tube, and it highly is 5nm to 200 μ m, and noble metal comprises gold or platinum.
Described electrode is arranged under the carbon nano-tube by forming in the groove of noble metal loading in the insulating barrier of two grid both sides.
Described grid and distance between electrodes are between 5nm to 100 μ m.
Described carbon nano-tube is the P type Single Walled Carbon Nanotube of diameter less than 2nm, the straight placement of this carbon nano-tube.
The degree of depth of described groove is between 10nm to 95 μ m; The thickness of insulating barrier is between 35nm to 100 μ m; The width of grid and electrode is between 10nm to 50 μ m.
The method for preparing the carbon nano-tube random asccess memory provided by the invention may further comprise the steps:
1. the silicon of choosing (001) orientation is as substrate.Utilize the organic vapor phase deposition method
(PECVD), the thick SiO of preparation 35nm-100nm on the Si substrate
2Insulating barrier 7;
2. at first make grid: at SiO
2Adopt the exposure of conventional electrical bundle, photoetching on the insulating barrier
Technology is at SiO
2Form wide 10nm-30nm on the insulating barrier, dark 10nm-95 μ m's
Groove; Utilize the method for electron beam evaporation,, photoresist is shelled at surface deposition one deck Al
From, clean, again through peroxidating, make the Al surface form the thick Al of 2-3nm
2O
3Insulation
Layer has been finished the preparation of grid;
3. prepare first electrode and second electrode: repeat above lithography step, at SiO
2Insulating barrier
7 grid both sides, apart from the distance of grid be 10nm-50 μ m, direction parallel with grid,
Its width is that the groove and second electrode of 10nm-95 μ m also has a direction and grid
Vertically be connected to the groove of grid, utilize the method for electron beam evaporation again, on whole surface
Deposit the gold that a layer thickness is 30nm, both intact after then electric lithography glue being peeled off, cleaned
Become the preparation of first electrode and second electrode;
4. selecting a diameter is that 1nm-5nm, length are 200nm-400nm, and charge carrier is dense
Degree is 9 * 10
6Cm
-1Single Walled Carbon Nanotube, with atomic force microscope with its straight being positioned over
On the entire device, direction is basic vertical with the grid direction with electrode, and wants and electrode
Contact well with grid;
5. after device being encapsulated, connect resistance 2 and constant pressure source 5, the first electrodes 3 ground connection;
Preparation.
Device preparation finishes the back structure as shown in Figure 3: the grid 6 and first electrode 3 and second electrode 4 all should with SiO
2Insulating barrier 7 maintains an equal level.
The present invention compares with people's such as Adrian Bachtold carbon nano-tube memory following advantage: use comparatively general Single Walled Carbon Nanotube, reduced the difficulty of element manufacturing from material.The present invention has greatly reduced the area of grid, and has only used a carbon nano-tube just can realize memory function, makes the design of device more reasonable, makes more simple.From design, the structure that the present invention has creatively used grid to be connected with electrode has been simplified the structure of device, for the extensive integrated condition of having created of following device, is convenient to advantages such as integrated.
Description of drawings
Fig. 1 is the schematic diagram of the carbon nano-tube memory made of people such as Adrian Bachtold.
Fig. 2 is the schematic diagram of carbon nano-tube random asccess memory of the present invention.
Fig. 3 is the structure chart according to the carbon nano-tube random asccess memory of the embodiment of the invention 1.
Fig. 4 is the structure chart according to the carbon nano-tube random asccess memory of the embodiment of the invention 2.
Shown in the figure: 1, carbon nano-tube; 2, resistance; 3, first electrode; 4, second electrode;
5, constant pressure source; 6, grid; 7, SiO
2Insulating barrier; 8, Si substrate; 9, switch.
Embodiment:
Embodiment 1:
With reference to Fig. 2 and 3, be elaborated in conjunction with the structure of manufacture method to the carbon nano-tube random asccess memory of present embodiment:
The silicon of choosing (001) orientation is as substrate 8.Utilize organic vapor phase deposition method (PECVD), the thick SiO of preparation 300nm on Si substrate 8
2Insulating barrier 7.At first make grid 6: at SiO
2Even smearing thickness is the thick electric lithography glue (PMMA) of 80nm on the insulating barrier 7.Photoresist behind the electron beam exposure behind the photoresist of removal exposure, forms the groove of a wide 30nm through development, photographic fixing on photoresist layer.The SiO that uses dry etching method etching not have photoresist to cover
2, at SiO
2Form wide 30nm on the insulating barrier 7, the groove of dark 30nm.Utilize the method for electron beam evaporation, at the thick Al of surface deposition one deck 30nm.With photoresist lift off, cleaning,, make the Al surface form the thick Al of 2-3nm again through peroxidating
2O
3Insulating barrier.So just finished the preparation of grid 6.Prepare first electrode 3 and second electrode 4 then: repeat above lithography step, evenly smear the photoresist that a layer thickness is 80nm on the entire device surface.Behind the resist exposure, forming two on photoresist layer is that 50nm, direction are vertical with grid 6 with a direction with grid 6 grooves parallel, that width is 30nm in grid 6 both sides, apart from the distance of grid 6, the position is between grid 6 and groove, and width is that 30nm, length are the 50nm groove.Use dry etching, do not having the SiO of photoresist
2Etch the groove of wide 30nm, dark 30nm on the insulating barrier 7.Utilizing the method for electron beam evaporation again, is the gold of 30nm at whole surface deposition one layer thickness.Both finished the preparation of first electrode 3 and second electrode 4 after then electric lithography glue being peeled off, cleaned.Selecting a diameter is that 1nm, length are 200nm, and carrier concentration is 9 * 10
6Cm
-1Single Walled Carbon Nanotube 1 is placed on the entire device with atomic force microscope.Requiring carbon nano-tube to place does not have bending, and direction is basic vertical with the grid direction with electrode, and will contact well with grid with electrode.After device encapsulated, connect resistance 2 and constant pressure source 5, the first electrodes 3 ground connection, finish the preparation of entire device.
Device preparation finishes the back structure as shown in Figure 3: the grid 6 and first electrode 3 and second electrode 4 all should with SiO
2Insulating barrier 7 maintains an equal level, and second electrode 4 is connected with switch 9, and is connected with grid 6, and connects resistance 2.Resistance 2 links to each other with a constant pressure source 5.Carbon nano-tube 1 is positioned on two electrodes and the grid 6, should keep straight.
Embodiment 2:
With reference to Fig. 2 and 4, be elaborated in conjunction with the structure of manufacture method to the carbon nano-tube random asccess memory of present embodiment:
The silicon of choosing (001) orientation is as substrate 8.Utilize organic vapor phase deposition method (PECVD), the thick SiO of preparation 300nm on Si substrate 8
2Insulating barrier 7.At first make grid 6: at SiO
2Even smearing thickness is the thick electric lithography glue (PMMA) of 80nm on the insulating barrier 7.Photoresist behind the electron beam exposure behind the photoresist of removal exposure, forms the groove of a wide 30nm through development, photographic fixing on photoresist layer.The SiO that uses dry etching method etching not have photoresist to cover
2, at SiO
2Form wide 30nm on the insulating barrier, the groove of dark 30nm.Utilize the method for electron beam evaporation, at the thick A1 of entire device surface deposition one deck 30nm.With photoresist lift off, cleaning,, make the Al surface form the thick Al of 2-3nm again through peroxidating
2O
3Insulating barrier.So just finished the preparation of grid 6.Choosing a diameter is that 1nm, length are 400nm, and carrier concentration is 9 * 10
6Cm
-1Single Walled Carbon Nanotube 1 is placed on the entire device with atomic force microscope.Require grid to be in the carbon nano-tube position intermediate substantially, the carbon nano-tube straight line is placed, and direction is basic vertical with the grid direction with electrode, and carbon nano-tube 1 will contact well with grid 6.After carbon nano-tube is in place, be 50nm in grid 6 both sides, apart from the distance of grid 6, prepare two width and be 0.1 μ m, highly be first electrode 3 of 50nm and second electrode 4 with focused ion beam (FIB) method.Two electrode direction are parallel with grid.After device package finishes, first electrode 3 is connected with grid 6.Connect resistance 2 and constant pressure source 5, the first electrodes 3 ground connection at last, finish the making of device.
After device preparation finishes, structure as shown in Figure 4: grid 6 and SiO
2Insulating barrier 7 maintains an equal level.On carbon nano-tube 1 placement and the grid 6, keep straight, two ends are fixing by first electrode 3 and second electrode 4.Connect second electrode 4 and grid 6, connect switch 9 and resistance 2 simultaneously, resistance 2 connects constant pressure source 5.
The carbon nano-tube memory of making below in conjunction with people such as Adrian Bachtold as shown in Figure 1 describes device operation principle of the present invention: first electrode 3 is connecting the grid of another carbon nano-tube simultaneously again as the input of a carbon nano-tube; Second electrode 4 is as the same.So the structure of two carbon nano-tube is identical, promptly the grid of the input utmost point of a carbon nano-tube and another carbon nano-tube is to being connected.When first electrode, 3 inputs, one logical value, during as logical value " 1 ", grid just is in conducting state with the carbon nano-tube that first electrode 3 is connected.At this moment, the logical value that obtains on second electrode 4 is " 0 ".Grid just is in cut-off state with the carbon nano-tube that second electrode 4 is connected, and will keep logical value " 1 " on such first electrode 3.Whole system all will keep this state, just can obtain stable and the opposite output valve of first electrode, 3 input values on such second electrode 4.In like manner: when first electrode, 3 input logic values " 0 ", two carbon nano-tube also will keep opposite state, make on second electrode 4 and obtain stable output.Realized the storage of data like this by the state that keeps two carbon nano-tube.
Electrical properties below in conjunction with schematic diagram 2 of the present invention and carbon nano-tube illustrates operation principle of the present invention.
Diameter is the Single Walled Carbon Nanotube of 1nm, and resistance is generally several K Ω at normal temperatures.Its charge carrier is the hole by testing as can be known, and conduction type is the P type.Under the effect of forward grid bias, the concentration in charge carrier---hole will reduce.At thickness of insulating layer is under the situation of 140nm, and grid voltage is about 6V, and the hole in the carbon nano-tube will be exhausted fully, and carbon nano-tube is in cut-off state.Simultaneously, we are as can be known: at this moment, if keep the cut-off state of carbon nano-tube, added bias voltage should be not more than 1.5V at the carbon nano-tube two ends.(" Applied Physics wall bulletin " Appl.Phy.Letters, 2001, Vol73, NO.17,2447.) so we are defined in the circuit of the present invention, and 1.2V is logical value " 1 ", 0V is logical value " 0 ".
In logical circuit, unified logical value is very important, all should observe this regulation in all parts of logical circuit, can guarantee that like this circuit structure is simple, efficient is higher, calculating is reliable.Will observe this regulation except the input and the output at carbon nano-tube two ends, the grid of controlling carbon nanotube also must be observed this regulation.
By above discussion we as can be known: when the gate insulator layer thickness was 140nm, the voltage that exhausts of grid was 6V.We determine by following calculating, during the exhausting voltage and be 1.2V of grid, and the thickness of gate insulator.
Known, there is following relationship in the voltage that blocks between carbon nano-tube and the grid:
Q＝CV
G，T 1
V
G, TFor blocking voltage, Q is electrically charged by charge carrier, and C is the electric capacity between carbon nano-tube and the grid.
Q and carrier concentration satisfy formula:
Q＝peL 2
P is a carrier concentration; E is electrically charged by charge carrier, and charge carrier is the hole in p type carbon nano-tube, so e=+1.6 * 10 here
-19Coulomb; L is the length of carbon nano-tube and grid contact portion.
Know that again the electric capacity between carbon nano-tube and the grid satisfies formula:
C≈2πεε
0L/ln(2h/r) 3
H is the distance between carbon nano-tube and the grid, i.e. the thickness of gate insulator; R is the carbon nano-tube diameter; ε is a dielectric constant, and here we get ε=2.5.
peln(2h/r)＝2πεε
0V
G，T
It is 9 * 10 that the present invention selects carrier concentration
6Cm
-1P type carbon nano-tube (" Applied Physics wall bulletin " Appl.Phy.Letters, 2001, vol 73, NO.17,2447.).The carbon nano-tube diameter is 1nm, and cut-ff voltage is 1.2V.Bringing formula 4 into can get: h ≈ 3nm.That is: in the present invention, work as Al
2O
3Thickness of insulating layer is not more than under the situation of 3nm, and carbon nano-tube is in cut-off state.
The present invention has utilized the conducting state of the grid controlling carbon nanotube of carbon nano-tube to realize the purpose of information stores.Its schematic diagram as shown in Figure 2.Switch 9 closures, memory enters write state.At this moment, if input second electrode 4 input voltages are 1.2V, promptly during logical value " 1 ", carbon nano-tube 1 is in the state of not conducting under the effect of grid 6.Cut-off switch 9, device enters store status.Second electrode 4 has identical electromotive force 1.2V with constant pressure source 5, i.e. logical value " 1 ".Simultaneously, grid 6 is connected with second electrode 4, so grid 6 is sustaining voltage 1.2V, and carbon nano-tube 1 is also with the remain off state.So though switch 9 has disconnected, second electrode 4 will stably keep output voltage 1.2V, i.e. logical value " 1 " always.In like manner, after switch 9 closures, if input second electrode 4 input voltages are 0V, promptly during logical value " 1 ", voltage is 0V on the grid 6, and carbon nano-tube 1 is in conducting state.Cut-off switch 9, device enters store status.Second electrode, 4 voltages are 0V, i.e. logical value " 0 ".Grid 6 is connected with second electrode 4, so grid 6 voltages will keep 0V, carbon nano-tube 1 also will keep conducting state.Though switch 9 has disconnected, second electrode 4 still will obtain stable output voltage 0V, i.e. logical value " 0 ".
The storage numerical value read the part be that an internal resistance can be considered infinitely-great voltmeter, measure the voltage between second electrode 4 and first electrode 3.If recording voltage is 1.2V, then be considered as logical value " 1 "; If recording voltage is 0V, then be considered as logical value " 0 ".Like this, we have just realized that capacity is the information stores of 1bit.
Claims (8)
1. random asccess memory of utilizing carbon nano-tube to make comprises that with Si as substrate, this substrate is provided with a SiO
2Insulating barrier, carbon nano-tube, grid and electrode; It is characterized in that: described grid is positioned at SiO on the Si substrate
2Among the groove in the insulating barrier, its interior depositing Al and the Al that forms through surface oxidation
2O
3Insulating barrier, grid also is connected with a resistance, and this resistance is connected with constant pressure source; Described electrode comprises two independently electrodes, two electrodes are parallel to the both sides that grid is arranged on grid, be positioned on the carbon nano-tube or under, its second electrode also has a section vertical with grid of direction, this section contacts with grid, first electrode grounding wherein, second electrode is connected with switch, and grid links to each other with the short circuit on substrate of second electrode simultaneously; Carbon nano-tube is perpendicular to grid and two electrode independently, the straight SiO that is placed on
2On the surface of insulating barrier, and and Al
2O
3Surface of insulating layer and electrode surface contact.
2. the random asccess memory of utilizing carbon nano-tube to make according to claim 1, it is characterized in that: it is respectively to cover a layer of precious metal at the carbon nano-tube two ends that described electrode is provided with on the carbon nano-tube, and it highly is 5nm to 200 μ m.
3. the random asccess memory of utilizing carbon nano-tube to make according to claim 1, it is characterized in that: it is depositing noble metal in two grooves in the insulating barrier on substrate that described electrode is provided with under the carbon nano-tube, and surface of insulating layer maintains an equal level on this electrode surface and the substrate.
4. the random asccess memory of utilizing carbon nano-tube to make according to claim 1, it is characterized in that: the noble metal of described making electrode comprises gold or platinum.
5. according to claim 1 or the 3 described random asccess memory of utilizing carbon nano-tube to make, it is characterized in that: described grid and two electrodes are arranged in the groove of insulating barrier on the substrate, and the degree of depth of groove is between 10nm to 95 μ m; The thickness of insulating barrier is between 35nm to 100 μ m; The width of grid and electrode is between 10nm to 50 μ m.
6. the random asccess memory of utilizing carbon nano-tube to make according to claim 1 is characterized in that: the Al of grid
2O
3Thickness of insulating layer between 1 nanometer to 5 nanometer, its surface and be positioned on the substrate surface of insulating layer and maintain an equal level.
7. according to claim 1 or the 2 or 3 described random asccess memory of utilizing carbon nano-tube to make, it is characterized in that: the straight placement of carbon nano-tube.
8. one kind prepares the described method of utilizing the random asccess memory of carbon nano-tube making of claim 1, may further comprise the steps:
(1) silicon of choosing (001) orientation is as substrate.Utilize the organic vapor phase deposition method, the thick SiO of preparation 35nm-100nm on the Si substrate
2Insulating barrier 7;
(2) at first make grid: at SiO
2Adopt the exposure of conventional electrical bundle, photoetching process on the insulating barrier, at SiO
2Form wide 10nm-30nm on the insulating barrier, the groove of dark 10nm-95 μ m; Utilize the method for electron beam evaporation,,,, make the Al surface form the thick Al of 2-3nm again through peroxidating with photoresist lift off, cleaning at surface deposition one deck Al
2O
3Insulating barrier has been finished the preparation of grid;
(3) preparation first electrode and second electrode: repeat above lithography step, at SiO
2The grid both sides of insulating barrier 7, be that 10nm-50 μ m, direction are parallel with grid, its width is the groove of 10nm-95 μ m apart from the distance of grid, also have a vertical groove that is connected to grid of direction with second electrode with grid, utilize the method for electron beam evaporation again, at whole surface deposition one layer thickness is the gold of 30nm, has both finished the preparation of first electrode and second electrode after then electric lithography glue being peeled off, cleaned;
(4) selecting a diameter is that 1nm-5nm, length are 200nm-400nm, and carrier concentration is 9 * 10
6Cm
-1Single Walled Carbon Nanotube, with its straight being positioned on the entire device, direction is basic vertical with the grid direction with electrode with atomic force microscope, and contacts with grid with electrode;
(5) device is encapsulated after, connect resistance 2 and constant pressure source 5, the first electrodes 3 ground connection; Second electrode 4 is connected with switch 9, and is connected with grid 6, finishes the preparation of entire device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02123864 CN1252819C (en) | 2002-07-05 | 2002-07-05 | RAM made of carbon nano tube and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02123864 CN1252819C (en) | 2002-07-05 | 2002-07-05 | RAM made of carbon nano tube and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466218A true CN1466218A (en) | 2004-01-07 |
| CN1252819C CN1252819C (en) | 2006-04-19 |
Family
ID=34142532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02123864 Expired - Fee Related CN1252819C (en) | 2002-07-05 | 2002-07-05 | RAM made of carbon nano tube and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1252819C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420033C (en) * | 2004-10-28 | 2008-09-17 | 鸿富锦精密工业（深圳）有限公司 | Field effect transistor |
| US7768016B2 (en) | 2008-02-11 | 2010-08-03 | Qimonda Ag | Carbon diode array for resistivity changing memories |
| US7894253B2 (en) | 2006-10-27 | 2011-02-22 | Qimonda Ag | Carbon filament memory and fabrication method |
| US7915603B2 (en) | 2006-10-27 | 2011-03-29 | Qimonda Ag | Modifiable gate stack memory element |
| CN101484997B (en) * | 2005-05-09 | 2011-05-18 | 南泰若股份有限公司 | Memory arrays using nanotube articles with reprogrammable resistance |
| US8030637B2 (en) | 2006-08-25 | 2011-10-04 | Qimonda Ag | Memory element using reversible switching between SP2 and SP3 hybridized carbon |
| CN102027610B (en) * | 2008-04-11 | 2012-12-05 | 桑迪士克3D有限责任公司 | Memory cell that includes a carbon nano-tube reversible resistance-switching element and methods of forming the same |
| CN107819037A (en) * | 2017-12-07 | 2018-03-20 | 苏州大学 | Using the fin field effect pipe of CNT as conductive trench and preparation method thereof |
-
2002
- 2002-07-05 CN CN 02123864 patent/CN1252819C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420033C (en) * | 2004-10-28 | 2008-09-17 | 鸿富锦精密工业（深圳）有限公司 | Field effect transistor |
| CN101484997B (en) * | 2005-05-09 | 2011-05-18 | 南泰若股份有限公司 | Memory arrays using nanotube articles with reprogrammable resistance |
| US8030637B2 (en) | 2006-08-25 | 2011-10-04 | Qimonda Ag | Memory element using reversible switching between SP2 and SP3 hybridized carbon |
| US7894253B2 (en) | 2006-10-27 | 2011-02-22 | Qimonda Ag | Carbon filament memory and fabrication method |
| US7915603B2 (en) | 2006-10-27 | 2011-03-29 | Qimonda Ag | Modifiable gate stack memory element |
| US7768016B2 (en) | 2008-02-11 | 2010-08-03 | Qimonda Ag | Carbon diode array for resistivity changing memories |
| CN102027610B (en) * | 2008-04-11 | 2012-12-05 | 桑迪士克3D有限责任公司 | Memory cell that includes a carbon nano-tube reversible resistance-switching element and methods of forming the same |
| CN107819037A (en) * | 2017-12-07 | 2018-03-20 | 苏州大学 | Using the fin field effect pipe of CNT as conductive trench and preparation method thereof |
| CN107819037B (en) * | 2017-12-07 | 2023-10-27 | 苏州大学 | Fin type field effect transistor using carbon nano tube as conductive groove and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1252819C (en) | 2006-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20040144972A1 (en) | Carbon nanotube circuits with high-kappa dielectrics | |
| CN1765011A (en) | Manufacturing has the method for the semiconductor probe of resistance tip | |
| CN1811944A (en) | Semiconductor probe with resistive tip and method of fabricating the same | |
| Sun et al. | Graphene electronic devices | |
| CN1252819C (en) | RAM made of carbon nano tube and preparation method thereof | |
| US7332740B2 (en) | Memory device having molecular adsorption layer | |
| CN101894909A (en) | Nanowire resistance change memory and implementation method thereof | |
| CN2566463Y (en) | Random access memory with carbon nano tube structure | |
| CN1236492C (en) | Carbon nano tube type integrated EFI and preparation process thereof | |
| CN1262008C (en) | AND gate logic device with monowall carbon nano tube strucure and mfg. method | |
| CN1251247C (en) | Method for raising electrical property of nano-materials | |
| CN2566462Y (en) | Single wall carbon nano tube 'and ' gate logical device | |
| CN1236496C (en) | Logic NOT gate device made of carbon nano tube | |
| CN1236495C (en) | Carbon nano tube NOR logic device | |
| CN1248313C (en) | Carbon nano tube logic OR gate device and preparation method thereof | |
| CN2556790Y (en) | Carbon nano tubular integrated FET | |
| CN1252817C (en) | Single electron memory having carbon nano tube structure and process for making it | |
| CN2567779Y (en) | Carbon nano-pipe 'OR' gate logical device | |
| CN1228855C (en) | Single-electron storage designed based on coulomb damping principle and its preparing method | |
| US20090059654A1 (en) | High density magnetic memory based on nanotubes | |
| CN113823636B (en) | Ferroelectric domain engineering modulated two-dimensional homojunction memory cell and regulation and control method | |
| CN1240134C (en) | Single electron multi-value memory device | |
| CN1275327C (en) | Single electron trivalue storage based on coulomb baffle principle design and its preparation method | |
| CN1262007C (en) | Single electron memory having carbon nano tube structure and process for making it | |
| CN1156019C (en) | Molecular tunnen diode and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060419 Termination date: 20120705 |