CN1469472A - 光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器 - Google Patents

光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器 Download PDF

Info

Publication number
CN1469472A
CN1469472A CNA031491189A CN03149118A CN1469472A CN 1469472 A CN1469472 A CN 1469472A CN A031491189 A CNA031491189 A CN A031491189A CN 03149118 A CN03149118 A CN 03149118A CN 1469472 A CN1469472 A CN 1469472A
Authority
CN
China
Prior art keywords
integrated circuit
chip
light
optical interconnection
microwatt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA031491189A
Other languages
English (en)
Other versions
CN100438027C (zh
Inventor
�ٹ���
近藤贵幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN1469472A publication Critical patent/CN1469472A/zh
Application granted granted Critical
Publication of CN100438027C publication Critical patent/CN100438027C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/43Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405Shape
    • H01L2224/24051Conformal with the semiconductor or solid-state device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76Apparatus for connecting with build-up interconnects
    • H01L2224/7615Means for depositing
    • H01L2224/76151Means for direct writing
    • H01L2224/76155Jetting means, e.g. ink jet
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821Forming a build-up interconnect
    • H01L2224/82101Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06527Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10329Gallium arsenide [GaAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13064High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/103Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type
    • H01L31/1035Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type the devices comprising active layers formed only by AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/023Mount members, e.g. sub-mount members
    • H01S5/02325Mechanically integrated components on mount members or optical micro-benches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/40Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/4025Array arrangements, e.g. constituted by discrete laser diodes or laser bar
    • H01S5/4087Array arrangements, e.g. constituted by discrete laser diodes or laser bar emitting more than one wavelength
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/40Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/42Arrays of surface emitting lasers
    • H01S5/423Arrays of surface emitting lasers having a vertical cavity

Abstract

本发明提供了一种能够实现集成电路间的信号传输速度高速化的光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器。根据本发明的光互联集成电路其特征在于包括:多个集成电路芯片(1)、(2)、(3);发光元件(VC1)、(VC2)、(VC3)、(VC4),其为微瓦片状元件,被分别粘结在集成电路芯片(1)、(2)、(3)上;以及光检测器(PD1)、(PD1’)、(PD2)、(PD2’)、(PD3)、(PD3’)、(PD4)、(PD4’),其为微瓦片状元件,被分别粘结在集成电路芯片(1)、(2)、(3)上,是用于检测所述发光元件出射光的光接收元件。

Description

光互联集成电路、光互联集成电路的制造方法、 光电装置以及电子仪器
技术领域
本发明涉及一种光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器。
背景技术
现有技术是在硅半导体衬底上,设置砷化镓制作的表面发射激光器(VCSEL)、光电二极管(PD)及高电子迁移率晶体管(HEMT)等,或者是把微硅晶体管粘贴固定到玻璃衬底上,用以取代液晶显示器(LCD)各象素的薄膜晶体管(TFT),这些可以被认为是在材料不同的衬底上形成半导体元件的技术。
作为这种具有不同材质的半导体集成电路,可以举例的有光电集成电路(OEIC)。光电集成电路是具有光输入输出装置的集成电路。虽然采用电信号进行集成电路内的信号处理,但是与集成电路外部的输入输出采用光信号进行。
发明内容
但是,对于计算机来说,由于集成电路内部结构的细化,使CPU内部的运算速度(工作时钟)逐年提高。但是,总线的信号传输速度几乎逐渐达到了极限,成为计算机处理速度的瓶颈问题。如果使用光进行总线的信号传输,则计算机的处理速度的极限可以显著提高。为了实现这个目的,则需要在硅制作的集成电路中内置微型光发射和接收元件。
然而,由于硅是间接跃迁型半导体而不能发光。这样,有必要将硅同其它的半导体发光元件进行组合来构成集成电路。
在这里,有希望成为半导体发光元件的有砷化镓(GaAs)等由化合物半导体形成的表面发射激光器(VCSEL)。但是,由于表面发射激光器与硅晶格不匹配,因此,很难利用晶体取向附生等的半导体制造工艺,直接在硅集成电路上形成。
通常,表面发射激光器可以在砷化镓衬底上形成。因此,可以考虑使用一种融合电信号传输电路和光信号传输电路的方法,将砷化镓衬底上的表面发射激光器制作成芯片,然后把该芯片机械性地安装在硅集成电路衬底上。
此外,为了不浪费形成集成电路的半导体衬底的面积,或者为了便于融合后的处理,最好,集成电路上的表面发射激光器元件的芯片尺寸尽可能小。如果可能,其尺寸最好与单片形成的集成电路大致相同,即尺寸=(厚度数μm×面积数十μm2)。但是,现有的半导体安装技术中,可装卸的芯片尺寸大于等于(厚度数十μm×面积数百μm2)的尺寸。
针对这些问题,第一参考文献(杂志《电子学》,2000年10月号,37~40页)以及第二参考文献(杂志《电子情报通信学会论文志》,2001/9,Vol.J84-C.No9)中有相关技术记载。这些参考文献阐述的技术是,首先,通过研磨清除衬底,只将形成半导体元件的最外层的功能层(数μm)复制到其它支撑衬底上,通过装卸以及光蚀刻技术整形出所希望的大小尺寸,粘结到最终衬底上,这样,在最终衬底的需要的位置上形成最后的半导体元件的厚度为数μm的半导体层(功能层)。通过通常的半导体工艺进行加工、安装电极等后完成这些半导体层。
这些第一和第二参考文献的技术上的问题在于:由于是通过研磨清除半导体衬底,因此需要刚体的支撑衬底。而且,需要全面一次性地进行与最终衬底的接合。即在进行接合前,必须全部清除最终需要保留部分以外的半导体膜,因而浪费极大。另外,由于被接合部分只是功能层,所以,接合后需要进行半导体处理。因此,若所需的半导体元件的配置密度不太大时,会因为逐个进行最终衬底的处理而造成很大的浪费。
鉴于以上的不足,本发明的目的是提供一种能够实现集成电路间的信号传输速度高速化的光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器。
另外,本发明还提供能够简易、小型、低成本制造具有高速的信号传输速度的集成电路的光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器。
为达到上述目的,本发明涉及的光互联集成电路,其特征在于包括:至少两个集成电路芯片;至少一个微瓦片状元件,粘结在每一个所述集成电路芯片上;在至少一个所述微瓦片状元件上设置的发光元件;以及在至少一个所述微瓦片状元件上设置的光接收元件,用于检测所述发光元件发射的光。
根据本发明,安装在某一集成电路芯片上的发光元件发射的光信号,由安装在其它的集成电路上的光接收元件进行检测,发光元件受通信信号驱动,可以收发集成电路芯片之间的光通信信号,可以使集成电路芯片间的信号传输速度高速化。
另外,由于在微瓦片状元件上设置了作为收发装置的发光元件和光接收元件,故收发装置可以小型化,从而可以制造出结构简单、小型、且低成本的在集成电路芯片间高速进行信号收发的光互联集成电路。
本发明的光互联集成电路的该微瓦片状元件优选粘结在该集成电路芯片的指定位置上。
根据本发明,微瓦片状元件的尺寸很小,由于其微瓦片状元件是通过粘结设置在集成电路芯片上的,因此微瓦片状元件不仅限于集成电路芯片的周边部分,也可以设置在集成电路中的任意位置。
另外,本发明的光互联集成电路的该发光元件,用于发射光信号,所述光接收元件用于接收发光元件发射的光信号。
根据本发明,由于从安装在某一集成电路芯片上的发光元件发射的光,由安装在其它的集成电路上的光接收元件进行检测,所以在集成电路芯片之间可以收发光信号,可以使集成电路芯片间的信号传输速度高速化。
另外,本发明的光互联集成电路,优选所述发光元件设置在该集成电路芯片之一的第一集成电路芯片上所粘结的微瓦片状元件上;该光接收元件设置在该集成电路芯片之一的第二集成电路芯片上所粘结的微瓦片状元件上。
根据本发明,由于第二集成电路芯片上所粘结的微瓦片状元件的光接收元件检测第一集成电路芯片上所粘结的微瓦片状元件的发光元件发射的光,故在集成电路芯片之间可以收发光信号,可以使集成电路芯片间的信号传输速度高速化。
本发明的光互联集成电路中,优选该第一集成电路芯片具有至少两个该发光元件或光接收元件;该第二集成电路芯片具有至少该两个发光元件或是光接收元件;该第一集成电路芯片与第二集成电路芯片具有至少两组由该发光元件和光接收元件组成的信号收发装置。
根据本发明,可通过第一集成电路芯片上设置的多个发光元件或光接收元件和第二集成电路芯片上设置的多个发光元件或是光接收元件形成多组信号收发装置,利用该多组信号收发装置,可以形成能够同时(并行)收发信号的光总线。因此,根据本发明,可以使集成电路芯片间的信号传输速度进一步提高。
另外,根据本发明,可以构成更加紧凑、高速的光互联集成电路,因为构成光总线的多个发光元件以及光接收元件是微瓦片状元件,因此,在一个集成电路芯片上设置的多个发光元件以及光接收元件之间的间隔可以非常狭小。
另外,本发明的光互联集成电路,该两组信号收发装置具有该第一集成电路芯片和第二集成电路芯片间作为双向通信装置的功能。
根据本发明,可以构成在集成电路芯片间进行双向通信的高速、紧凑的光互联集成电路。
本发明的光互联集成电路,优选该至少两组的信号收发装置在该第一集成电路芯片和第二集成电路芯片之间作为并行传输多个光信号的光总线。
根据本发明,可以构成在集成电路芯片间包含高速、紧凑的信号传输装置的光总线的光互联集成电路。
本发明的光互联集成电路中,优选将上述发光元件和光接收元件设置在该第一集成电路芯片的发光元件的发光中心轴与该第二集成电路芯片的光接收元件的受光中心轴处于基本同一条直线的位置上。
根据本发明,由于第一集成电路芯片的发光元件发射的光入射到第二集成电路芯片的光接收元件中,所以能够很好地收发集成电路芯片间的光信号,可以实现集成电路芯片间的信号传输速度高速化。
本发明的光互联集成电路的该光总线中的多个光信号最好分别由不同波长的光组成。
根据本发明,由于光总线内多个光信号分别采用了不同的波长,所以即使由发光元件和光接收元件为一组的多组光信号收发装置相互间配置的很近,也能够防止由于散射光造成的信号干扰,可以使光互联集成电路进一步小型化。
本发明的光互联集成电路中,上述发光元件优选为表面发射激光器。
根据本发明,通过表面发射激光器,可以进一步提高通信速度,同时也容易形成能穿透叠压的多层结构的多个集成电路芯片的激光发射装置(信号发送装置)。
本发明的光互联集成电路中,最好该光接收元件具有波长选择性。
根据本发明,由于使用了具有波长选择性的光接收元件(光检测器),可以更好地防止由于散射光造成的信号干扰,使光互联集成电路更加小型化。
本发明的光互联集成电路中的该发光元件优选发射波长大于等于1.1微米的光。
根据本发明,当用硅半导体形成集成电路芯片时,由于发光元件发射的光可以透过此硅半导体,所以,以多层结构重叠多个集成电路芯片,使用穿透集成电路芯片的光信号,则可以在各集成电路芯片间进行良好的信号传输。
还有,本发明的光互联集成电路,优选该发光元件发射的光透过至少一个该集成电路芯片后,入射到该光接收元件。
根据本发明,当多个集成电路芯片重叠形成多层结构时,可通过穿透集成电路芯片的光在各集成电路间进行通信,从而可以简单地构成小型、高速的光互联集成电路。
本发明的光互联集成电路中,至少两个集成电路芯片重叠粘合,使一个集成电路芯片的上述发光元件发射的光能够在另外的至少一个集成电路芯片的至少一个该光接收元件上检测到。
根据本发明,由于能通过光信号进行各集成电路间的通信,所以能够容易地构成小型、高速的光互联集成电路。
本发明的光互联集成电路中,最好至少两个集成电路芯片通过透明粘合剂重叠粘合在一起。
根据本发明,可借助具有透明性质的粘合剂传输各集成电路间通信用的光信号,与通过空气传输的方法相比,更有可能使传输路径的介质的折射率和集成电路芯片的折射率一致,可以很好地进行光信号的传输。
本发明的光互联集成电路中,该发光元件的一个面或是该光接收元件的一个面最好由非透明材料覆盖。
根据本发明,由于光通信中的散射光可以被非透明材料吸收,故可以进行优质的光通信。
另外,根据本发明的光互联集成电路制造方法,其特征在于包括以下步骤:在至少两个集成电路芯片中的每一个的指定位置上,用透明粘合剂粘合至少一个构成发光元件或光接收元件的微瓦片状元件;用透明粘合剂重叠粘合所述至少两个集成电路芯片,使一个所述集成电路芯片所粘结的微瓦片状元件的发光元件发射的光,能够被其它至少一个集成电路芯片所粘结的微瓦片状元件的光接收元件检测到。
根据本发明,不仅是在集成电路芯片的周边部分,在集成电路之中的任意位置都可以设置微瓦片状元件,可以在重叠粘合成多层结构的各集成电路芯片之间进行光通信,因此,可以构成小型的、能够实现集成电路芯片间的信号传输速度高速化的光互联集成电路。
本发明的光互联集成电路制造方法中,在半导体衬底上形成作为该发光元件或光接收元件的半导体元件,在该半导体衬底形成半导体元件的面上粘贴薄膜,并将该半导体衬底中包含半导体元件的功能层从该半导体衬底上切割分离而形成微瓦片状元件。
根据本发明,可以将切割分离成微瓦片状的半导体元件(微瓦片状元件)与任意的材料体接合,形成集成电路。这里,半导体元件可以是化合物半导体或硅半导体,与半导体元件接合的物体可以是硅半导体衬底,也可以是化合物半导体或是其它物质。这里,根据本发明,可以将半导体元件形成于与该半导体元件材质不同的衬底(集成电路芯片)上,就象在硅半导体衬底(集成电路芯片)上,形成砷化镓的表面发射激光器或是光电二极管等一样。另外,在半导体衬底上完成半导体元件后,要将其切割分离成微瓦片状,所以,在加工完成集成电路之前,可以预先对半导体元件进行测试筛选。
此外,根据本发明,可以只把含有半导体元件的功能层作为微瓦片状元件,从半导体衬底上切下来,固定到薄膜上,进行处理,所以,可以一个一个选择半导体元件(微瓦片状元件),粘贴固定到最后的衬底(集成电路芯片)上,同时,还能够使得可处理的微瓦片状元件的尺寸较从前的封装技术的尺寸还小。因此可以达到高精度配置。
本发明的光互联集成电路的制造方法中,在将微瓦片状元件粘结到该集成电路芯片的步骤中,该透明粘合剂优选使用液滴喷出的方法涂敷。
根据本发明,可以减少形成透明粘合剂的材料的用量,可以容易地应对设计变化,降低制造成本。
本发明的光互联集成电路的制造方法中,在粘结该至少两个集成电路芯片的步骤中,该透明粘合剂优选使用液滴喷出的方法涂敷。
根据本发明,可以减少形成透明粘合剂的材料的用量,可以容易地应对设计变化,降低制造成本。
根据本发明的一种光电装置,其特征在于包括上述光互联集成电路。
根据本发明,可以提供一种具有高速信号传输装置、使显示状态高速转换的小型光电装置。
根据本发明的一种电子仪器,其特征在于,包括上述光互联集成电路。
根据本发明,可以提供一种具有高速信号传输装置、可进行高速信号处理的小型光电装置。
附图说明
图1是根据本发明的一个实施方式的光互联集成电路的剖面示意图;
图2是说明光互联集成电路动作的简要剖面示意图;
图3是微瓦片状元件的制造方法的第一步骤的剖面示意图;
图4是微瓦片状元件的制造方法的第二步骤的剖面示意图;
图5是微瓦片状元件的制造方法的第三步骤的剖面示意图;
图6是微瓦片状元件的制造方法的第四步骤的剖面示意图;
图7是微瓦片状元件的制造方法的第五步骤的剖面示意图;
图8是微瓦片状元件的制造方法的第六步骤的剖面示意图;
图9是微瓦片状元件的制造方法的第七步骤的剖面示意图;
图10是微瓦片状元件的制造方法的第八步骤的剖面示意图;
图11是微瓦片状元件的制造方法的第九步骤的剖面示意图;
图12是微瓦片状元件的制造方法的第十一步骤的剖面示意图;
图13示出了包含根据本实施方式的光电装置的电子仪器的一个示例;
图14示出了包含根据本实施方式的光电装置的电子仪器的一个示例;以及
图15示出了包含根据本实施方式的光电装置的电子仪器的一个示例。
具体实施方式
以下就根据本发明的光互联集成电路,参照附图进行说明。
图1是根据本发明的一个实施方式的光互联集成电路的剖面示意图。该光互联集成电路的结构是三个集成电路芯片(硅半导体衬底)1、2、3,通过插入其间的树脂等透明粘合剂(无图示)重叠粘结形成多层结构。集成电路芯片1、2、3是在半导体衬底上形成集成电路(LSI等)的。此外,集成电路芯片1、2、3也可以在玻璃衬底上形成薄膜晶体管(TFT)等。
在集成电路芯片1的特定位置上,粘贴固定有两个表面发射激光器VC1、VC2和两个光检测器PD3、PD4。即不但集成电路芯片1上的周边部分,在集成电路中的任意位置均可配置表面发射激光器VC1、VC2以及光检测器PD3、PD4。
这里,表面发射激光器VC1、VC2以及光检测器PD3、PD4分别是微瓦片状元件。微瓦片状元件是微小的瓦片形状(板形状)的半导体器件,例如,厚度1μm到20μm,长宽尺寸是数十μm到数百μm的板状材料。有关微瓦片状元件的制造方法将在其后详细说明。
表面发射激光器VC1、VC2以及光检测器PD3、PD4的各自的间隔可以很小,例如其间隔可以是数μm。
此外,各个微瓦片状元件,通过具有透明性的粘合材料30粘贴固定在集成电路芯片1上。粘合剂30可以使用例如树脂材料。
在集成电路芯片2的上面,粘结有一个表面发射激光器VC3和3个光检测器PD1、PD2、以及PD4’。这里,表面发射激光器VC3和光检测器PD1、PD2、PD4’分别是微瓦片状元件。这些微瓦片状元件通过具有透明性的粘合材料30粘贴固定在集成电路芯片2上。
在集成电路芯片3的上面,粘结有一个表面发射激光器VC4和3个光检测器PD1’、PD2’、PD3’。这里,表面发射激光器VC4以及光检测器PD1’、PD2’、PD3’分别是微瓦片状元件。这些微瓦片状元件通过具有透明性的粘合材料30粘贴固定在集成电路芯片3上面。
粘合剂30是通过喷嘴(无图示)喷出含有粘合剂30的液滴,涂敷在集成电路芯片1、2、3上。这样做可以减少粘合剂30的用量,容易应对设计上的变化,降低制造成本。
另外,用粘合剂对集成电路芯片1、2、3进行重叠粘贴固定时也可以使用这样的粘合剂液滴喷出的涂敷方法。这样做可以减少粘合剂的用量,容易应对设计上的变化,降低制造成本。
另外,面对表面发射激光器VC1的发光中心轴设置有两个光检测器PD1、PD1’;面向表面发射激光器VC2的发光中心轴设置有两个光检测器PD2、PD2’;面向表面发射激光器VC3的发光中心轴设置有两个光检测器PD3、PD3’;以及面向表面发射激光器VC4的发光中心轴设置有两个光检测器PD4、PD4’。
表面发射激光器VC和光检测器PD、PD’的配置,最好使各个表面发射激光器VC的发光中心轴与面向各个表面发射激光器设置的两个光检测器PD、PD’的光接收中心轴重合。
表面发射激光器VC1发射第一波长的激光束,表面发射激光器VC2发射第二波长的激光束,表面发射激光器VC3发射第三波长的激光束,表面发射激光器VC4发射第四波长的激光束。这里的第一至第四波长,例如在硅半导体衬底上形成集成电路芯片1、2、3的情况下,波长大于等于1.1μm。据此,从表面发射激光器VC1、VC2、VC3、VC4发射的激光束可以穿透集成电路芯片1、2、3。例如第一波长为1.20μm,第二波长为1.22μm,第三波长为1.24μm,第四波长为1.26μm。
即使是波长1.10μm以下的光也能够穿透玻璃衬底。因此,采用玻璃衬底形成集成电路芯片1、2、3时,第一至第四波长也可以设定在1.10μm以下。例如第一波长为0.79μm,第二波长为0.81μm,第三波长为0.83μm,第四波长为0.85μm。
理想的是,各光检测器PD1、PD1’、PD2、PD2’、PD3、PD3’、PD4、PD4’均具有波长选择性。例如,光检测器PD1、PD1’只检测第一波长的光,光检测器PD2、PD2’只检测第二波长的光,光检测器PD3、PD3’只检测第三波长的光,光检测器PD4、PD4’只检测第四波长的光。另外,也可以在各光检测器PD1、PD1’、PD2、PD2’、PD3、PD3’、PD4、PD4’的上面和下面,设置具有波长选择性的薄膜等而形成具有波长选择功能的光接收元件。作为光检测器PD1、PD1’、PD2、PD2’、PD3、PD3’、PD4、PD4’,可以使用例如光电二极管等。
另外,优选在表面发射激光器VC1、VC2以及光检测器PD3、PD4的上面覆盖非透明材料。在光检测器PD1’、PD2’、PD3’以及表面发射激光器VC4的下面,也覆盖有非透明材料。
这样做可以抑制因散射光产生的噪声。
通过上述组合,从表面发射激光器VC1向下方发射的第一波长的激光束穿透表面发射激光器VC1与集成电路芯片1之间的粘合剂30、集成电路芯片1、以及集成电路芯片1与集成电路芯片2之间的粘合剂后,入射到光检测器PD1,接着,穿透光检测器PD1、光检测器PD1与集成电路芯片2之间的粘合剂30、集成电路芯片2、以及集成电路芯片2与集成电路芯片3之间的粘合剂后,入射到光检测器PD1’。
从表面发射激光器VC2向下方发射的第二波长的激光束穿透表面发射激光器VC2与集成电路芯片1之间的粘合剂30、集成电路芯片1、以及集成电路芯片1与集成电路芯片2之间的粘合剂,入射到光检测器PD2,接着,穿透光检测器PD2、光检测器PD2与集成电路芯片2之间的粘合剂30、集成电路芯片2、以及集成电路芯片2与集成电路芯片3之间的粘合剂,入射到光检测器PD2’。
从表面发射激光器VC3向上方发射的第三波长的激光束穿透集成电路芯片2与集成电路芯片1之间的粘合剂、集成电路芯片1、以及集成电路芯片1与光检测器PD3之间的粘合剂30,入射到光检测器PD3。从表面发射激光器VC3向下方发射的第三波长的激光束穿透表面发射激光器VC3与集成电路芯片2之间的粘合剂30、集成电路芯片2、以及集成电路芯片2与集成电路芯片3之间的粘合剂,入射到光检测器PD3’。
另外,从表面发射激光器VC4向上方发射的第四波长的激光束穿透集成电路芯片3与集成电路芯片2之间的粘合剂、集成电路芯片2、以及集成电路芯片2与光检测器PD4’之间的粘合剂30,入射到光检测器PD4’,接着,穿透光检测器PD4’、集成电路芯片2与集成电路芯片1之间的粘合剂,集成电路芯片1、以及集成电路芯片1与光检测器PD4之间的粘合剂30,入射到光检测器PD4。
因此,作为表面发射激光器VC1输出的第一波长激光束的光信号几乎同时被光检测器PD1、PD1’接收。而且,作为表面发射激光器VC2输出的第二波长激光束的光信号几乎同时被光检测器PD2、PD2’接收。从表面发射激光器VC3输出的第三波长激光束的光信号几乎同时被光检测器PD3、PD3’接收。从表面发射激光器VC4输出的作为第四波长激光束的光信号几乎同时被光检测器PD4、PD4’接收。
这样,在集成电路芯片1、集成电路芯片2、以及集成电路芯片3的相互之间,第一波长至第四波长的四个光信号可以同时、并行收发信号,进行双向通信。换言之,该表面发射激光器VC1、VC2、VC3、VC4以及光检测器PD1、PD2、PD3、PD4、PD1’、PD2’、PD3’、PD4’成为光总线的信号收发装置,第一至第四波长的四个光信号为光总线的传输信号。
因此,本实施方式的光互联集成电路由于具有在三个集成电路芯片1、2、3的相互间并列收发多个光信号的光总线,因而可以使集成电路芯片间的信号传输速度高速化,可以解决在使用金属配线收发电气信号时产生的以下问题。
1)配线间信号传输时间的偏差(歪斜失真)
2)传输高频信号时需要的较大功率
3)配线设置时自由度受到限制,设计困难
4)需要阻抗匹配
5)需要解决接地噪声和电磁感应噪声的措施
本实施方式的光互联集成电路,由于使用微瓦片状元件作为发光元件和光接收元件,可以使多个发光元件和光接收元件相互间的配置间隔极小,从而可实现装置的小型化。
本实施方式的光互联集成电路中,由于做为光总线通信信号的多个激光束分别具有不同的波长,因此,即使发光元件和光接收元件组成一组的多组光信号收发装置相互间的配置间隔很小,也可以防止由于散射光等造成的信号干扰,从而可进一步使装置小型化。
另外,本实施方式的光互联集成电路使用表面发射激光器作为发光元件,所以,在使通信速度进一步提高的同时,也容易形成穿透多层结构的多个集成电路芯片的激光束的发射装置(信号发送装置)。
还有,本实施方式的光互联集成电路中,由于使用具有波长选择性的光接收元件(光检测器),可以进一步防止由于散射光等造成的信号干扰,从而使装置更加小型化。
接下来,就光互联集成电路的一般动作参照图2进行说明。图2是相当于图1所示光互联集成电路的一部分的光互联集成电路的剖面示意图。该光互联集成电路具有多层结构,是使用树脂等透明粘合剂(无图示)重叠粘合的两个(多个)集成电路芯片(硅半导体衬底)10、20而形成的。集成电路芯片10包含集成电路区11,在集成电路芯片10的上面,光检测器PD10与表面发射激光器VC10通过透明粘合剂30粘合在一起。另外,集成电路芯片20包含集成电路区21,在集成电路芯片20的上面,表面发射激光器VC20与光检测器PD20通过透明粘合剂30粘接在一起。在集成电路区11、21上,形成构成CPU、存储器或是ASIC的各种集成电路。
在这种结构中,将在集成电路芯片10的集成电路区11内处理的电信号,通过表面发射激光器VC10转换为激光脉冲信号,然后发送至集成电路芯片20的光检测器PD20。光检测器PD20将接收到的激光脉冲信号转换为电信号发送至集成电路区21。接着,在集成电路芯片20的集成电路区21内处理的电信号,通过表面发射激光器VC20转换为激光脉冲信号,然后发送至集成电路芯片10的光检测器PD10。光检测器PD10将接收到的激光脉冲信号转换为电气信号发送至集成电路区11。
这样,集成电路芯片10与集成电路芯片20,可通过激光脉冲进行双向信号传输。(微瓦片状元件的制造方法)
以下就微瓦片状元件的制造方法参照图3至图12进行说明。本制造方法中,将要说明的是把微瓦片状元件的化合物半导体器件(化合物半导体元件)粘接到成为衬底的硅LSI芯片上的情况,但是,本发明也适用于与半导体器件的种类和LSI芯片种类无关的情况。此外,本实施例中的“半导体衬底”虽然是指由半导体物质形成的材料体,但并不限于平板状的衬底,无论形状如何,只要是半导体材料,都包含在“半导体衬底”内。<第一步骤>
图3是微瓦片状元件的制造方法的第一步骤的剖面示意图。图3中的衬底110为半导体衬底,例如,假设采用砷化镓化合物半导体衬底,衬底110上的最底层设置有牺牲层111。牺牲层111由砷化铝(AlAs)构成,厚度为例如数百nm。
例如,在牺牲层111的上层设置有功能层112。功能层112的厚度为例如从1μm到10(20)μm左右。而且,在功能层112上形成半导体器件(半导体元件)113。半导体器件113可以是例如发光二极管(LED)、表面发射激光器(VCSEL)、光电二极管(PD)、高电子迁移率晶体管(HEMT)、异质双极型晶体管(HBT)等。这些半导体器件113都是在衬底110上重叠多层外延层后形成的元件。另外,在各半导体器件113内还形成电极,进行动作测试。<第二步骤>
图4是表示微瓦片状元件的制造方法的第二步骤的剖面示意图。在本步骤中,将各个半导体器件113分割开形成分离槽121。分离槽121至少需到达牺牲层111的深度。例如,分离槽的宽度和深度都在10μm到数百μm。另外,为使后述的选择蚀刻液在该分离槽121内流动,分离槽121成为不设隔档的相连的沟槽。进而,分离槽121形成围棋盘状的格子。
另外,由于分离槽121相互间的间隔在数十μm到数百μm,因此被分离槽121分割形成的各半导体器件113的面积成为边长从数十μm到数百μm的四方块。分离槽121的形成方法可以有光刻和湿式蚀刻方法,以及干式蚀刻方法。另外,只要在衬底上不产生裂缝的范围内,也可以用切割U型槽的方式形成分离槽121。<第三步骤>
图5是微瓦片状元件的制造方法的第三步骤的剖面示意图。在本步骤中,中间复制薄膜131粘贴在衬底110的表面(半导体器件113一侧)。中间复制薄膜131是表面上涂抹了粘合剂的柔性带状薄膜。<第四步骤>
图6是微瓦片状元件的制造方法的第四步骤的剖面示意图。在本步骤中,在分离槽121内注入选择蚀刻液141。本步骤里因为只对牺牲层111实施有选择的蚀刻,因此使用对砷化铝选择性高的低浓度的盐酸作为选择蚀刻液141。<第五步骤>
图7是微瓦片状元件的制造方法的第五步骤的剖面示意图。在第四步骤,向分离槽121内注入选择蚀刻液141后,经过规定的时间,牺牲层111的全部被选择地蚀刻并从衬底110上去除。<第六步骤>
图8是微瓦片状元件的制造方法的第六步骤的剖面示意图。在第五步骤里,如果对牺牲层111进行全面蚀刻,就可以从衬底110中切割分离功能层112。
然后,在该步骤,通过从衬底110剥离中间复制薄膜131,便可以从衬底110上拉开粘在中间复制薄膜131上的功能层112。据此,形成半导体器件113的功能层112,由于分离槽121的形成以及牺牲层111的蚀刻而被分割,变为特定形状的(例如瓦片状)的半导体元件(上述实施例中的“微瓦片状元件”),粘贴保留在中间复制薄膜131上。这里,最好,功能层的厚度例如从1μm到20μm,大小(长宽)例如是从数十μm到数百μm。<第七步骤>
图9是微瓦片状元件的制造方法的第七步骤的剖面示意图。在本步骤中,通过移动中间复制薄膜131(微瓦片状元件161粘贴其上),在最终衬底171(集成电路芯片1、2、3)的特定位置上,定位微瓦片状元件161。这里,最终衬底171使用例如硅半导体,形成LSI区172。另外,在最终衬底171的特定位置,涂敷上粘贴固定微瓦片状元件161的粘合剂173。粘合剂也可以涂抹在微瓦片状元件161上。<第八步骤>
图10是表示本制造方法的第八步骤的剖面示意图。在该步骤,使用压紧器181,将定位在最终衬底171特定位置上的微瓦状元件161,越过中间复制胶片131,压紧接合到最终衬底171上。这里,因为在该特定位置涂敷了粘合剂173,所以,微瓦状元件161,被粘贴固定到该最终衬底171的特定位置上。<第九步骤>
图11是表示本半导体集成电路制造方法第九步骤的剖面示意图。在本步骤中,使中间复制薄膜131失去粘力,从微瓦片状元件161上揭下中间复制薄膜131。
中间复制薄膜131的粘合剂,设定为UV硬化性或者热硬化性的粘合剂。当为UV硬化性的粘合剂时,将压紧器181定为透明材料,从压紧器181的前端开始照射紫外线(UV),使中间复制薄膜131失去其粘力。当采用热硬化性的粘合剂时,加热压紧器181即可。或者,也可以在第六步骤以后,对中间复制薄膜131进行全面紫外线照射等,使粘力全面消失。虽说叫粘力消失,但实际上,还残留有少量的粘性,微瓦片状元件161非常薄,也非常轻,所以,被保持在中间复制薄膜131上。<第十步骤>
本步骤无图示。在本步骤中,施行加热处理等,将微瓦片状元件161大体固定到最终衬底171上。<第十一步骤>
图12是表示本半导体集成电路制造方法的第十一步骤的剖面示意图。在本步骤中,通过配线191,将微瓦片状元件161的电极与最终衬底171上的电路进行电连接,使得完成一个LSI芯片等(用于光互联集成电路的集成电路芯片)。作为最终衬底171,不仅可以用硅半导体,还可以使用玻璃衬底、石英衬底或者塑料薄膜。(应用实例)
以下就本发明涉及的光互联集成电路的应用实例进行说明。
第一应用实例使用的是上述实施例的光电集成电路信号传输装置的光互联集成电路。计算机可作为光电集成电路的例子。形成CPU的集成电路内的信号处理使用了电信号,而在CPU与存储装置等之间进行数据传输的总线上使用的是该实施例的光互联集成电路。
因此,根据本应用实例,可以比现有技术大幅度提高成为计算机处理速度瓶颈的总线信号传输速度。
另外,根据本应用实例,也可以使计算机等更大幅度地实现小型化。
作为第二应用实例,在光电装置的液晶显示器、等离子显示器或是有机EL(电致发光)显示器上使用了该实施例的光互联集成电路。
据此,根据本应用实例,因为可以高速收发显示信号,故可以提供高速转换显示状态的光电装置。(电子仪器)
以下对配备有上述实施方式的光互联集成电路的电子仪器的例子进行说明。
图13是移动电话例子的立体透视图。在图13中,符号1000表示使用了该光互联集成电路的移动电话主体,符号1001表示使用了该光电装置的显示部分。
图14是电子手表例子的立体透视图。在图14中,符号1100表示使用了该光互联集成电路的手表主体,符号1101表示使用了该光电装置的显示部分。
图15是文字处理机、个人计算机等便携型信息处理装置例子的立体透视图。在图15中,符号1200是信息处理装置,符号1202是键盘等输入部分,符号1204是使用了该光互联集成电路的信息处理装置主体,符号1206是使用了该光电装置的显示部分。
图13至图15表示的电子仪器由于设置了该实施方式的光互联集成电路或是光电装置,所以可以实现显示水平优异,特别是包含了高速响应和明亮的画面显示部分的电子仪器。另外,通过使用该实施方式的光互联集成电路,可比现有的电子仪器更加小型,同时,由于使用了该实施方式的光互联集成电路,而使制造成本比现有仪器更加低廉。
本发明的技术范围并不仅限于该实施方式,在不脱离本发明的主题范围之内可以有各种变形,实施方式中所列举的具体的材料或是层的构成只是其中一种例子,可以进行适当的变化。
例如,在上述实施例中使用了表面发射激光器作为发光元件,但也可以使用端面发射激光器或是光电二极管作为发光元件。
在该实施方式中列举了3个集成电路芯片重叠组合的例子,但本发明不限于此,也可以把2个或者4个集成电路芯片重叠组合。
综上所述,可以明确,如果采用本发明,可以在各集成电路芯片上设置了微瓦片状元件的发光元件或是光接收元件,因此,能够实现集成电路芯片间的信号传输速度的高速化。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的权利要求范围之内。
附图标记说明
1、2、3、10、20  集成电路芯片
11、21           集成电路区
30               粘合剂
PD1、PD1’、PD2、PD2’  光检测器
PD3、PD3’、PD4、PD4’  光检测器
PD10、PD20              光检测器
VC1、VC2、VC3、VC4      表面发射激光器
VC10、VC20              表面发射激光器

Claims (22)

1.一种光互联集成电路,其特征在于包括:
至少两个集成电路芯片;
至少一个微瓦片状元件,粘结在每一个所述集成电路芯片上;
在至少一个所述微瓦片状元件上设置的发光元件;以及
在至少一个所述微瓦片状元件上设置的光接收元件,用于检测所述发光元件发射的光。
2.根据权利要求1所述的光互联集成电路,其特征在于:所述微瓦片状元件被粘结在所述集成电路芯片的指定位置上。
3.根据权利要求2所述的光互联集成电路,其特征在于:所述发光元件发射光信号,所述光接收元件接收所述发光元件发射的光信号。
4.根据权利要求3所述的光互联集成电路,其特征在于:所述发光元件被设置在所述集成电路芯片之一的第一集成电路芯片所粘结的微瓦片状元件上;所述光接收元件被设置在所述集成电路芯片之一的第二集成电路芯片所粘结的微瓦片状元件上。
5.根据权利要求4所述的光互联集成电路,其特征在于:所述第一集成电路芯片具有至少两个所述发光元件或光接收元件;所述第二集成电路芯片具有至少两个所述发光元件或光接收元件;所述第一集成电路芯片和第二集成电路芯片具有至少两组由所述发光元件和光接收元件组成的信号收发装置。
6.根据权利要求5所述的光互联集成电路,其特征在于:所述至少两组信号收发装置具有在所述第一集成电路芯片和第二集成电路芯片间作为双向通信装置的功能。
7.根据权利要求6所述的光互联集成电路,其特征在于:所述至少两组信号收发装置在所述第一集成电路芯片和第二集成电路芯片之间,构成并行传输多个光信号的光总线。
8.根据权利要求6所述的光互联集成电路,其特征在于:设置所述发光元件和光接收元件,使所述第一集成电路芯片的发光元件的发光中心轴与所述第二集成电路芯片的光接收元件的光接收中心轴处于基本相同的直线上。
9.根据权利要求7所述的光互联集成电路,其特征在于:所述光总线中的多个光信号分别由不同波长的光组成。
10.根据权利要求1至9中任一所述的光互联集成电路,其特征在于:所述发光元件为表面发射激光器。
11.根据权利要求1所述的光互联集成电路,其特征在于:所述光接收元件具有波长选择性。
12.根据权利要求1所述的光互联集成电路,其特征在于:所述发光元件发射波长大于等于1.1微米的光。
13.根据权利要求1所述的光互联集成电路,其特征在于:所述发光元件发射的光至少透过一个所述集成电路芯片,入射到所述光接收元件上。
14.根据权利要求1所述的光互联集成电路,其特征在于:所述至少两个集成电路芯片重叠粘合,使所述集成电路芯片中的一个的发光元件发射的光能够被其它至少一个集成电路芯片的至少一个所述光接收元件检测到。
15.根据权利要求14所述的光互联集成电路,其特征在于:所述至少两个集成电路芯片通过透明的粘合剂重叠粘合在一起。
16.根据权利要求1所述的光互联集成电路,其特征在于:所述发光元件的一个面或所述光接收元件的一个面由非透明材料覆盖。
17.一种光互联集成电路的制造方法,其特征在于包括以下步骤:
在至少两个集成电路芯片中的每一个的指定位置上,用透明粘合剂粘结至少一个构成发光元件或光接收元件的微瓦片状元件;
用透明粘合剂重叠粘结所述至少两个集成电路芯片,使一个所述集成电路芯片所粘结的微瓦片状元件的发光元件发射的光,能够被其它至少一个所述集成电路芯片所粘结的微瓦片状元件的光接收元件检测到。
18.根据权利要求17所述的光互联集成电路的制造方法,其特征在于:在半导体衬底上形成作为所述发光元件或光接收元件的半导体元件,在所述半导体衬底形成半导体元件的面上粘贴薄膜,并将所述半导体衬底中包含半导体元件的功能层从所述半导体衬底上切割分离而形成微瓦片状元件。
19.根据权利要求17或18所述的光互联集成电路的制造方法,其特征在于:在将微瓦片状元件粘结到所述集成电路芯片的步骤中,所述透明粘合剂是以液滴喷出的方法涂敷的。
20.根据权利要求17至19中任一所述的光互联集成电路的制造方法,其特征在于:在粘结所述至少两个集成电路芯片的步骤中,所述透明粘合剂是以液滴喷出的方法涂敷的。
21.一种光电装置,其特征在于包括权利要求1所述的光互联集成电路。
22.一种电子仪器,其特征在于包括权利要求1所述的光互联集成电路。
CNB031491189A 2002-06-18 2003-06-16 光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器 Expired - Fee Related CN100438027C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002177489 2002-06-18
JP2002177489A JP2004022901A (ja) 2002-06-18 2002-06-18 光インターコネクション集積回路、光インターコネクション集積回路の製造方法、電気光学装置および電子機器

Publications (2)

Publication Number Publication Date
CN1469472A true CN1469472A (zh) 2004-01-21
CN100438027C CN100438027C (zh) 2008-11-26

Family

ID=29996493

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031491189A Expired - Fee Related CN100438027C (zh) 2002-06-18 2003-06-16 光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器

Country Status (3)

Country Link
US (1) US6858872B2 (zh)
JP (1) JP2004022901A (zh)
CN (1) CN100438027C (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102522455A (zh) * 2011-12-16 2012-06-27 哈尔滨工业大学(威海) 一种芯片垂直互联方法
CN104781932A (zh) * 2012-11-14 2015-07-15 高通股份有限公司 穿硅光学互连
CN104813598A (zh) * 2012-11-08 2015-07-29 株式会社V技术 光互连装置
CN104919731A (zh) * 2013-01-11 2015-09-16 株式会社V技术 光互联装置
CN106783744A (zh) * 2016-12-27 2017-05-31 成都海威华芯科技有限公司 一种InP PIN光电探测器集成器件的制作方法
CN107733524A (zh) * 2017-09-30 2018-02-23 天津大学 一种具有柔性薄膜pin光电二极管阵列的检测器
CN108364909A (zh) * 2018-01-19 2018-08-03 西安中为光电科技有限公司 一种具有发射和接收光信号功能的芯片及其制作方法
CN109655806A (zh) * 2017-10-11 2019-04-19 迈来芯科技有限公司 传感器设备
CN110692171A (zh) * 2017-04-12 2020-01-14 感应光子公司 超小型垂直腔表面发射激光器(vcsel)的发射器结构以及包括该发射器结构的阵列

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3800335B2 (ja) * 2003-04-16 2006-07-26 セイコーエプソン株式会社 光デバイス、光モジュール、半導体装置及び電子機器
JP4400327B2 (ja) 2003-09-11 2010-01-20 セイコーエプソン株式会社 タイル状素子用配線形成方法
EP1523043B1 (en) * 2003-10-06 2011-12-28 Semiconductor Energy Laboratory Co., Ltd. Optical sensor and method for manufacturing the same
EP1667227A4 (en) 2004-01-28 2011-08-03 Panasonic Corp MODULE AND MOUNTING STRUCTURE USING THE SAME
US7202141B2 (en) * 2004-03-29 2007-04-10 J.P. Sercel Associates, Inc. Method of separating layers of material
US8294166B2 (en) 2006-12-11 2012-10-23 The Regents Of The University Of California Transparent light emitting diodes
WO2006011960A1 (en) * 2004-06-25 2006-02-02 Sun Microsystems, Inc. Integrated circuit chip that supports through-chip electromagnetic communication
JP4517144B2 (ja) * 2004-07-14 2010-08-04 国立大学法人広島大学 Mos電界効果トランジスタ型量子ドット発光素子の製造方法
CN100365810C (zh) * 2005-03-15 2008-01-30 李奕权 漫射和镭射光电偶合的集成电路信号线
US7564066B2 (en) * 2005-11-09 2009-07-21 Intel Corporation Multi-chip assembly with optically coupled die
KR100765465B1 (ko) * 2005-12-29 2007-10-09 한국광기술원 장파장 광원을 이용한 반도체 패키지 적층 구조
US8207589B2 (en) 2007-02-15 2012-06-26 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device and electronic device, and method for manufacturing photoelectric conversion device
US7919849B2 (en) * 2007-04-04 2011-04-05 Ibiden Co., Ltd. Package substrate and device for optical communication
JP2009218395A (ja) * 2008-03-11 2009-09-24 Panasonic Corp 集積回路パッケージ
KR20130008299A (ko) * 2011-07-12 2013-01-22 삼성전자주식회사 반도체 장치
TWI438375B (zh) * 2011-11-25 2014-05-21 Lextar Electronics Corp 光源模組及其光源組件
JP6959919B2 (ja) * 2015-12-04 2021-11-05 クロミス,インコーポレイテッド 加工基板上のワイドバンドギャップデバイス集積回路アーキテクチャ
CN109906518B (zh) * 2016-12-05 2022-07-01 歌尔股份有限公司 微激光二极管转移方法和微激光二极管显示装置制造方法
US20200006924A1 (en) * 2016-12-05 2020-01-02 Goertek, Inc. Micro Laser Diode Display Device and Electronics Apparatus
CN107104169B (zh) * 2017-04-13 2019-01-08 南京邮电大学 基于异质键合的微型水下可见光通信双工器件及制备方法
KR102059968B1 (ko) * 2018-04-05 2019-12-27 한국과학기술연구원 중적외선을 이용한 반도체 칩간 광통신 기술
GB2600045B (en) * 2019-06-28 2023-12-20 Massachusetts Inst Technology Integrated structure for an optoelectronic device and method of fabricating the same
US11592166B2 (en) 2020-05-12 2023-02-28 Feit Electric Company, Inc. Light emitting device having improved illumination and manufacturing flexibility
US11876042B2 (en) 2020-08-03 2024-01-16 Feit Electric Company, Inc. Omnidirectional flexible light emitting device

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4533833A (en) * 1982-08-19 1985-08-06 At&T Bell Laboratories Optically coupled integrated circuit array
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5073230A (en) * 1990-04-17 1991-12-17 Arizona Board Of Regents Acting On Behalf Of Arizona State University Means and methods of lifting and relocating an epitaxial device layer
US5198684A (en) * 1990-08-15 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device with optical transmit-receive means
US5357122A (en) * 1991-09-05 1994-10-18 Sony Corporation Three-dimensional optical-electronic integrated circuit device with raised sections
US5827751A (en) * 1991-12-06 1998-10-27 Picogiga Societe Anonyme Method of making semiconductor components, in particular on GaAs of InP, with the substrate being recovered chemically
US5266794A (en) * 1992-01-21 1993-11-30 Bandgap Technology Corporation Vertical-cavity surface emitting laser optical interconnect technology
WO1993021663A1 (en) * 1992-04-08 1993-10-28 Georgia Tech Research Corporation Process for lift-off of thin film materials from a growth substrate
US5244818A (en) * 1992-04-08 1993-09-14 Georgia Tech Research Corporation Processes for lift-off of thin film materials and for the fabrication of three dimensional integrated circuits
US5286335A (en) * 1992-04-08 1994-02-15 Georgia Tech Research Corporation Processes for lift-off and deposition of thin film materials
US5465009A (en) * 1992-04-08 1995-11-07 Georgia Tech Research Corporation Processes and apparatus for lift-off and bonding of materials and devices
US5280184A (en) * 1992-04-08 1994-01-18 Georgia Tech Research Corporation Three dimensional integrated circuits with lift-off
JPH06151720A (ja) 1992-11-12 1994-05-31 Nippon Telegr & Teleph Corp <Ntt> モノリシック集積回路の構成法
JPH06151946A (ja) 1992-11-12 1994-05-31 Nippon Telegr & Teleph Corp <Ntt> 半導体受光素子およびその製造方法
JP2950106B2 (ja) 1993-07-14 1999-09-20 松下電器産業株式会社 光素子実装体の製造方法
US5793115A (en) 1993-09-30 1998-08-11 Kopin Corporation Three dimensional processor using transferred thin film circuits
US5391257A (en) * 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
US5904545A (en) * 1993-12-17 1999-05-18 The Regents Of The University Of California Apparatus for fabricating self-assembling microstructures
US6033995A (en) * 1997-09-16 2000-03-07 Trw Inc. Inverted layer epitaxial liftoff process
US6845184B1 (en) 1998-10-09 2005-01-18 Fujitsu Limited Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making
US6214733B1 (en) * 1999-11-17 2001-04-10 Elo Technologies, Inc. Process for lift off and handling of thin film materials
JP3829594B2 (ja) * 2000-06-30 2006-10-04 セイコーエプソン株式会社 素子実装方法と光伝送装置
CN1131610C (zh) * 2001-09-28 2003-12-17 清华大学 一种基于微光机电系统的阵列式激光收发集成传感器

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102522455A (zh) * 2011-12-16 2012-06-27 哈尔滨工业大学(威海) 一种芯片垂直互联方法
CN104813598A (zh) * 2012-11-08 2015-07-29 株式会社V技术 光互连装置
CN104781932B (zh) * 2012-11-14 2018-07-03 高通股份有限公司 穿硅光学互连
CN104781932A (zh) * 2012-11-14 2015-07-15 高通股份有限公司 穿硅光学互连
CN104919731A (zh) * 2013-01-11 2015-09-16 株式会社V技术 光互联装置
CN106783744A (zh) * 2016-12-27 2017-05-31 成都海威华芯科技有限公司 一种InP PIN光电探测器集成器件的制作方法
US11061117B2 (en) 2017-04-12 2021-07-13 Sense Photonics, Inc. Devices with ultra-small vertical cavity surface emitting laser emitters incorporating beam steering
CN110692171A (zh) * 2017-04-12 2020-01-14 感应光子公司 超小型垂直腔表面发射激光器(vcsel)的发射器结构以及包括该发射器结构的阵列
CN110710072A (zh) * 2017-04-12 2020-01-17 感应光子公司 具有结合光束转向的超小型垂直腔表面发射激光发射器的器件
CN110869796A (zh) * 2017-04-12 2020-03-06 感应光子公司 包括集成检测器和超小型垂直腔表面发射激光发射器的器件
US11125862B2 (en) 2017-04-12 2021-09-21 Sense Photonics, Inc. Emitter structures for ultra-small vertical cavity surface emitting lasers (VCSELS) and arrays incorporating the same
CN107733524A (zh) * 2017-09-30 2018-02-23 天津大学 一种具有柔性薄膜pin光电二极管阵列的检测器
CN107733524B (zh) * 2017-09-30 2023-10-03 天津大学 一种具有柔性薄膜pin光电二极管阵列的检测器
CN109655806A (zh) * 2017-10-11 2019-04-19 迈来芯科技有限公司 传感器设备
CN109655806B (zh) * 2017-10-11 2024-01-26 迈来芯科技有限公司 传感器设备
CN108364909B (zh) * 2018-01-19 2021-01-26 西安中为光电科技有限公司 一种具有发射和接收光信号功能的芯片及其制作方法
CN108364909A (zh) * 2018-01-19 2018-08-03 西安中为光电科技有限公司 一种具有发射和接收光信号功能的芯片及其制作方法

Also Published As

Publication number Publication date
JP2004022901A (ja) 2004-01-22
CN100438027C (zh) 2008-11-26
US20040036074A1 (en) 2004-02-26
US6858872B2 (en) 2005-02-22

Similar Documents

Publication Publication Date Title
CN1469472A (zh) 光互联集成电路、光互联集成电路的制造方法、光电装置以及电子仪器
CN1305135C (zh) 半导体装置及其制造方法、光电装置和电子仪器
CN1251327C (zh) 半导体集成电路、信号传输装置、光电装置和电子仪器
KR102160225B1 (ko) 개별 부품들의 기판 상으로의 병렬적 조립
CN1268957C (zh) 光电混装配线模块、制造方法及组装件
US20150187987A1 (en) Method of manufacturing a quantum dot optical component and backlight unit having the quantum dot optical component
CN1181564C (zh) 带有光传输部件的装置
CN1523668A (zh) 半导体器件
US20230008806A1 (en) Laser printing of color converter devices on micro led display devices and methods
US10025026B2 (en) Lighting device with light sources positioned near the bottom surface of a waveguide
CN1838424A (zh) 半导体合成装置、打印头和成像装置
CN1574407A (zh) 发光器件
CN101044632A (zh) 发光光源及其制造方法以及发光装置
CN1706051A (zh) 光电混合集成模块和使用该模块作为部件的光输入/输出设备
CN1761107A (zh) 光电复合配线部件和使用该部件的电子设备
US11910686B2 (en) Array substrate, method for preparing array substrate, display panel and display apparatus
CN1536616A (zh) 半导体器件的制造方法、集成电路、电光装置和电子仪器
CN1794029A (zh) 用于形成光学波导片镜面的加工头及加工设备和方法
CN1673790A (zh) 光波导互连板及其制造方法、制造用母体及光电多功能板
CN1499615A (zh) 布线基板、电路基板、电光装置及其制造方法、电子设备
CN101958374A (zh) 发光元件及其制造方法
US20200006924A1 (en) Micro Laser Diode Display Device and Electronics Apparatus
Cheng et al. Quantum Dot Film Patterning on a Trenched Glass Substrate for Defining Pixel Arrays of a Full-color Mini/Micro-LED Display
CN115621377A (zh) 微型led芯片的转移方法、显示模组和显示装置
CN1272182A (zh) 备有微反射镜的光波导及其制造方法和光信息处理设备

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081126

Termination date: 20140616

EXPY Termination of patent right or utility model