CN1501453A - 低介电常数层的制造方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Abstract
一种低介电常数层的制造方法,利用等离子体处理已形成的低介电常数层,之后再进行一道去除步骤。其中,此去除步骤借以去除低介电常数层表面形成的致密层。去除步骤可利用例如化学机械抛光法、氩气溅射法、氟化氢气体工艺、湿式蚀刻法或干式蚀刻法等。
Description
技术领域
本发明涉及低介电常数(Low Dielectric Constant;Low K)层的制造方法,特别涉及可降低介电常数值的低介电常数层制造方法。
背景技术
随着半导体技术的进步,组件的尺寸也不断地缩小,当集成电路的集成度(Integration)增加时,芯片的表面无法提供足够的面积来制作所需的内连线。因此,为了配合组件缩小后所增加的内连线,目前超大规模集成电路(Very LargeScale Integration;VLSI)技术大都采用多层金属导体连线的设计。然而,随着金属导线层数目的增加及导线间的距离不断缩小,电子信号在金属连线间传送时,金属连线的电阻电容延迟时间(Resistance Capacitance Delay Time;RCDelay Time),已成为半导体组件速度受限的主要原因之一。此外,金属连线尺寸的缩小,也使得电迁移(Electromigration)的情况日趋严重。
为了降低信号传递的时间延迟,目前的发展方向除了以电阻率约为1、67μΩ-cm的铜金属来取代电阻率约为2、66μΩ-cm的铝金属成为导线的连线系统外,还可以利用低介电常数材料来作为导线间的绝缘层,借以降低金属与金属层之间的寄生电容大小,使组件在速度方面的性能提高,并且可以降低功率的消耗(Power Dissipation)及噪声干扰(Cross-talk Noise)。
然而,由于低介电常数薄膜通常为松散的孔洞(Pore)结构,导致低介电常数薄膜的机械强度较差,因此在工艺期间,低介电常数薄膜很容易因一些外力或能量而破裂,造成工艺合格率的降低。为了避免低介电常数薄膜的破裂,传统上都必须借由变更或修改低介电常数材料的前驱物(Precursor)来提高其破裂临界。目前,一般在低介电常数薄膜形成后,对此低介电常数薄膜进行后续的处理,来增加其结构强度。
发明内容
鉴于上述的背景技术中,为了实现超大规模集成电路组件良好的操作特性,低介电常数材料技术日趋重要,因此,本发明的目的,在于提供一种低介电常数层的制造方法,在用等离子体处理低介电常数层的步骤后,加入去除低介电常数层上的致密层(Dense Layer)的步骤。
根据以上所述的目的,本发明低介电常数层的制造方法包括:首先,在基材上形成低介电常数层;接着,对低介电常数层进行等离子体处理步骤;随后,去除低介电常数层表面的部分材料。其中,去除步骤可使用化学机械抛光法(Chemical Mechanical Polishing)、氩气溅射法(Ar Sputtering)、氟化氢气体(HFVapor)工艺、湿式蚀刻法或干式蚀刻法等。
由于等离子体工艺后,低介电常数层表面的致密层会导致整体低介电常数层的介电常数值提高,因此在加入去除步骤后,可降低整体低介电常数层的介电常数值。这样一来,可以改善金属连线的电阻电容延迟时间,同时提升集成电路的组件速度。
附图简要说明
下面结合附图对本发明的具体实施方式作进一步详细的描述。附图中,
图1至图3为应用本发明低介电常数层的制造方法的剖面示意图;
图4为本发明低介电常数层的制造流程图。
具体实施方式
本发明揭露一种低介电常数层的制造方法,使集成电路中应用低介电常数材料所构成的绝缘层具有较低的介电常数值,以降低金属导线层之间的寄生电容大小。为了使本发明的叙述更加详尽与完备,可参照下列描述并配合图1至图3与图4的图示。图1至图3为本发明低介电常数层的工艺剖面示意图,而图4为本发明低介电常数层的制造流程图,请一同参照图1至图3与图4。
首先,按照步骤50,利用例如化学气相沉积法(Chemical Vapor Deposition:CVD)或等离子体增强化学气相沉积法(Plasma Enhanced CVD;PECVD)在基材10上形成一层低介电常数层12,此低介电常数层12的材料可例如为氟化非晶碳(Fluorinated Amorphous Carbon;a-C:F)、有机的MSQ(Methyl Silsesquioxane)、以及无机的HSQ(Hydrogen Silsesquioxane)等。
当低介电常数层12形成后,按照步骤52,利用等离子体14对此低介电常数层12进行等离子体处理,此等离子体处理步骤可使得低介电常数层内的原子排列进行重整及化学反应,从而降低介电常数与其缺陷。其中,等离子体处理的反应气体可例如为氢气、氮气及其混合物等。
但是,经过等离子体14所处理的低介电常数层12却会在其表面形成一层致密层16,此致密层16的介电常数高于内部低介电常数材料。在此情况下,整体低介电常数层12的介电常数值会因此而增加。
在低介电常数材料的技术日趋重要的情况下,本发明还在等离子体处理步骤之后,揭露一道去除步骤。按照步骤54,利用例如化学机械抛光法(ChemicalMechanical Polishing)、氩气(Ar)的溅射法(Sputtering)、氟化氢气体(HF Vapor)工艺、以及利用化学品的湿式蚀刻法或干式蚀刻法等,将致密层16去除,从而形成低介电常数层12a。
其中,一般致密层的厚度介于约100至1500之间,因此可根据形成致密层的厚度及材料不同,调整去除步骤中例如抛光液种类、粒径、蚀刻化学品、工艺时间、蚀刻方法等工艺条件,本发明并不在此限制。
例如,在本发明一较佳实施例中,对厚度约为500的致密层,利用用来去除氧化物、并且其成分为含硅材料或其混合物的抛光液,进行约180秒的化学机械抛光步骤,可使得原本厚度为2700的低介电常数层,厚度减少至2200,这样可将其表面的致密层去除。
另外,由于上述步骤52的进行等离子体处理并非本发明的重点,因此其所使用的工艺参数,例如反应气体种类、反应气体流量、等离子体功率、压力、温度与工艺时间等,都可根据需要而加以改变,本发明不在此限制。
利用本发明低介电常数层的制造方法,不仅具有利用等离子体处理提高低介电常数层的机械强度的优点,也同时改善了因致密层而提高介电常数值的缺点。这样,由于提高制造低介电常数材料的技术,使得介电常数值降低,从而具有改善金属连线的电阻电容延迟时间与提升集成电路组件速度的效果。
如熟悉此领域技术的人员所了解的,以上所述仅为本发明的较佳实施例而已,并非用以限定本发明的权利要求;凡其它未脱离本发明所揭示的构思下所完成的等效改变或修饰,均应包含在权利要求内。
Claims (10)
1、一种低介电常数层的制造方法,至少包括:
形成一低介电常数层于一基材上;
对该低介电常数层进行一等离子体处理;以及
进行一去除步骤,借以去除部分该低介电常数层。
2、根据权利要求1所述的低介电常数层的制造方法,其中形成该低介电常数层的步骤为利用一化学气相沉积法。
3、根据权利要求1所述的低介电常数层的制造方法,其中形成该低介电常数层的步骤为利用一等离子体增强化学气相沉积法。
4、根据权利要求1所述的低介电常数层的制造方法,其中上述的等离子体处理步骤为使用一反应气体,并且该反应气体的成分选自于由氢气、氮气及其混合物所组成的一族群。
5、根据权利要求1所述的低介电常数层的制造方法,其中上述的去除步骤为利用一化学机械抛光法。
6、根据权利要求1所述的低介电常数层的制造方法,其中上述的去除步骤为利用一溅射法。
7、根据权利要求6所述的低介电常数层的制造方法,其中上述的去除步骤为利用一氩气溅射法。
8、根据权利要求1所述的低介电常数层的制造方法,其中上述的去除步骤为利用一氟化氢气体工艺。
9、根据权利要求1所述的低介电常数层的制造方法,其中上述的去除步骤为利用一湿式蚀刻法。
10、根据权利要求1所述的低介电常数层的制造方法,其中上述的去除步骤为利用一干式蚀刻法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/295,609 US6770570B2 (en) | 2002-11-15 | 2002-11-15 | Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer |
US10/295,609 | 2002-11-15 |
Publications (2)
Publication Number | Publication Date |
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CN1501453A true CN1501453A (zh) | 2004-06-02 |
CN1327494C CN1327494C (zh) | 2007-07-18 |
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Application Number | Title | Priority Date | Filing Date |
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CNB031027261A Expired - Lifetime CN1327494C (zh) | 2002-11-15 | 2003-01-16 | 低介电常数层的制造方法 |
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Country | Link |
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US (1) | US6770570B2 (zh) |
CN (1) | CN1327494C (zh) |
SG (1) | SG111148A1 (zh) |
TW (1) | TW578216B (zh) |
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US6753269B1 (en) * | 2003-05-08 | 2004-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for low k dielectric deposition |
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2002
- 2002-11-15 US US10/295,609 patent/US6770570B2/en not_active Expired - Lifetime
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2003
- 2003-01-08 TW TW092100364A patent/TW578216B/zh not_active IP Right Cessation
- 2003-01-16 CN CNB031027261A patent/CN1327494C/zh not_active Expired - Lifetime
- 2003-09-17 SG SG200305635A patent/SG111148A1/en unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108064411A (zh) * | 2015-06-19 | 2018-05-22 | 应用材料公司 | 经由物理气相沉积工艺沉积介电膜的方法 |
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US20040097099A1 (en) | 2004-05-20 |
TW578216B (en) | 2004-03-01 |
US6770570B2 (en) | 2004-08-03 |
TW200407979A (en) | 2004-05-16 |
CN1327494C (zh) | 2007-07-18 |
SG111148A1 (en) | 2005-05-30 |
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