CN1503372A - 具有多重闸极及应变的通道层的晶体管及其制造方法 - Google Patents

具有多重闸极及应变的通道层的晶体管及其制造方法 Download PDF

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CN1503372A
CN1503372A CNA031538916A CN03153891A CN1503372A CN 1503372 A CN1503372 A CN 1503372A CN A031538916 A CNA031538916 A CN A031538916A CN 03153891 A CN03153891 A CN 03153891A CN 1503372 A CN1503372 A CN 1503372A
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CN1253943C (zh
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杨育佳
杨富量
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

具有多重闸极及应变的通道层的晶体管的结构包括由垂直型半导体层构成的源极、汲极和通道区所构成的晶体管，以及用以使通道区中具有一应变的应力层。其中，闸极绝缘层位于垂直型鳍形半导体层的通道区表面，闸极电极位于闸极绝缘层上，并包覆对应于通道区的垂直型鳍形半导体层的两侧壁和一顶面。此外，本发明并提供具有多重闸极及应变的通道层的晶体管的制造方法。

Description

具有多重闸极及应变的通道层的晶体管及其制造方法
技术领域
本发明是有关于一种半导体组件，特别是有关于一种制造具有多重闸极(multiple-gate)及应变的通道层(strained channel layer)的晶体管，且可应用在25奈米(sub-nanometer)制程以下。
背景技术
为了提高金氧半导体场效应晶体管(metal-oxide-semiconductorfield effect transistors；MOSFET)的操作效能，传统常见的方法为缩小金氧半导体场效应晶体管的尺寸，如此除了可改善组件的操作效能外，还能同时提高组件的密度和降低制造成本。然而，由于传统块金氧半导体场效应晶体管(bulk MOSFET)的闸极长度(gate length)的缩小，便容易由于源极与汲极与其间的通道相互作用，而影响了闸极对于其通道的开启/关闭状态的控制能力，而进一步引起的所谓的短通道效应(short channel effects；SCE)。
为了抑制所衍生的短通道效应的问题，传统上，解决的方法有增加主体掺杂浓度、降低闸极氧化层的厚度、以及超浅源极/汲极接合面(ultra-shallow source/drain junction)等。
当闸极长度缩小至25奈米级时，利用上述传统的方法来解决传统块金氧半导体场效应晶体管的短通道问题是相当困难的。因此，有人提出双闸极金氧半场效晶体管的结构来解决上述的问题，所谓双闸极金氧半场效晶体管的结构是为在通道区的两侧设置闸极，使得通道区可以由其两侧的闸极获得控制，以降低短通道效应。此外，当此双闸极金氧半场效晶体管组件开启时，会形成两个反转层(inversion layers)，以允许更多的电流流通。同时，此种双闸极金氧半场效晶体管的结构还可以进一步提高组件的积集度。
另一种改善晶体管的效能的方法为利用应力来提高通道区的载子的迁移率(mobility)。如图1所示，借由在松弛的硅锗层(relaxed SiGelayer)14上磊晶成长一硅层16，以制备出具有应变的通道层的晶体管18。而松弛的硅锗层14是形成于硅基底10上的厚度厚且具有浓度梯度的硅锗缓冲层12表面而得。与松弛的硅相较，松弛的硅锗层14具有较大的晶格常数(lattice constant)，因此，在松弛的硅锗层14上磊晶成长出的薄硅层16会处于双轴拉伸应变(biaxial tensile strain)。在此情况下，电洞和电子载子两者在处于双轴拉伸应变的硅层16中的迁移速率会增加。
图1所示的具有应变的通道层的晶体管18的结构，与传统的金氧半晶体管的结构类似，然而两者的载子的迁移率相差甚多。通常，在松弛的硅锗层14上磊晶成长一硅层16后，利用传统的0.18微米的金氧半晶体管制程，可以制备出相当于正常晶格的硅块材上的0.13微米的金氧半场效晶体管组件的效能。虽然具有应变的通道层的晶体管18可以有效地提高组件的操作效能，然而，这样的结构无法有效达到提高组件积集度的目的。
发明内容
本发明的目的在于提供一种具有多重闸极及应变的通道层的晶体管，用以同时借由提高载子的迁移率来提高组件的效能，以及同时提高组件的积集度。
因此，本发明提供一种具有多重闸极及应变的通道层的晶体管。垂直型鳍形半导体层位于基底上，其具有源极、汲极以及位于源极和汲极之间的通道区，且垂直型鳍形半导体层中具有一应变。闸极绝缘层位于垂直型鳍形半导体层的通道区表面。闸极电极位于闸极绝缘层上，并包覆对应于通道区的垂直型鳍形半导体层的两侧壁和一顶面。
本发明并提供另一种具有多重闸极及应变的通道层的晶体管。垂直型鳍形半导体层位于基底上，其具有源极、汲极以及位于源极和汲极之间的通道区。闸极绝缘层位于垂直型鳍形半导体层的通道区表面。闸极电极位于闸极绝缘层上，并包覆垂直型鳍形半导体层的两侧壁和一顶面的通道区。应力膜层位于源极和汲极上，借以将应力导入垂直型鳍形半导体层中，使垂直型鳍形半导体层具有一应变。
在上述具有多重闸极及应变的通道层的晶体管中，垂直型鳍形半导体层中的应变可为拉伸应变或压缩应变。若为拉伸应变，其拉伸应变强度约为0.01％至2％，应力膜层的热膨胀系数大于垂直型鳍形半导体层的热膨胀系数。若为压缩应变，其压缩应变强度约为0.01％至2％，应力膜层的热膨胀系数小于垂直型鳍形半导体层的热膨胀系数。
本发明另提供一种具有多重闸极及应变的通道层的晶体管的制造方法，其方法简述如下。提供一基底，其至少包括半导体层/绝缘层的迭层结构。定义半导体层以形成一鳍形半导体层，并在鳍形半导体层表面形成一闸极介电层。接着，在闸极介电层上形成一导电层，并定义导电层以形成一跨于鳍形半导体层两侧壁和顶面的闸极电极。之后，形成源极和汲极于闸极电极两侧的鳍形半导体层中。最后，沉积一应力膜层于源极和汲极上，以将机械应变导入鳍形半导体层中。
附图说明
图1是表示传统借由硅锗缓冲层的使用而制备出的具有应变通道层的晶体管的剖面示意图；
图2A至图2G是表示本发明的具有多重闸极及应变的通道层的晶体管的制造流程图；
图3是表示经过源极/汲极的淡掺杂制程和浓掺杂制程后所形成的具有多重闸极及应变的通道层的晶体管的上视图。
符号说明：
硅基底：10
硅锗缓冲层：12
松弛的硅锗层：14
硅层：16
晶体管：18
硅层/氧化硅层迭置型基底：20
硅基底：22
埋入式氧化硅层：24
硅层：26
鳍形硅层：26a
罩幕层：28
闸极介电层：30
闸极电极：32
图案化罩幕层：34
间隙壁：36
导电层：38
应力膜层：40
具体实施方式
为让本发明的上述目的、特征及优点能更明显易懂，下文特举一较佳实施例，并配合附图，作详细说明如下。
以下将配合图2A至图2G详细说明本发明的具有多重闸极及应变的通道层的晶体管的制造方法。
请参照图2A，首先提供半导体层/绝缘层迭置型基底，例如为硅层/氧化硅层迭置型基底(silicon on insulator substrate；SOI substrate)20，其包括硅基底22、埋入式氧化硅层24和硅层26，在此实施例中是以该种型式的基底为例。当然半导体层的材质和绝缘层的材质并不限定于此，例如硅锗亦可做为半导体层。
接着请参照图2B，于硅层26中定义出鳍形硅层(silicon fins)26a，以做为通道层之用。其中鳍形硅层26a的宽度约为50埃至500埃左右，高度约为200埃以上。
定义鳍形硅层26a的方法例如是于硅层26上形成一罩幕层28，并以该罩幕层28为蚀刻罩幕，以将该罩幕层28的图案转移至其下方的硅层26中。此罩幕层28可为光阻层(photoresist layer)、能量敏感层(energysensitive layer)、氧化硅层、氮化硅层、或其它材质的罩幕层。
接着，对鳍形硅层26a进行侧表面平滑化处理，以降低鳍形硅层26a侧表面的粗糙度。侧表面平滑化处理的方法为牺牲性氧化处理和侧壁处理，其中侧壁处理的方法例如是在1000℃含氢(H2)的环境下进行高温回火。当鳍形硅层26a的侧表面经牺牲性氧化处理时，会于表面氧化生成一层氧化硅，借此修复表面于蚀刻过程中所受到的伤害，并将上部边角圆滑化，再将氧化硅移除。表面平滑化的目的在于使组件具有好的载子迁移率，以及利于后续形成可靠度佳的闸极绝缘层。
接着如图2C所示，将具有干净且平整表面的鳍形硅层26a上方的罩幕层28移除。移除的方法可为电浆蚀刻或湿蚀刻，湿蚀刻所使用的蚀刻剂可为稀释的氢氟酸(DHF)。在此蚀刻过程中，硅层26a底部可能发生底切(undercut)或凹槽(notch)。
接着，于鳍形硅层26a表面形成一层闸极介电层30，其形成方法例如是热氧化法、化学气相沉积法、溅镀等。通常，鳍形硅层26a的侧壁和顶部的闸极介电层30具有不同的厚度，通常是顶部的闸极介电层30的厚度较侧壁为厚。其材质可为氧化硅、或氮氧化硅，其厚度约为3埃至100埃，较佳的是10埃以下，顶部部份的厚度较佳的是20埃以下；或者为高介电常数的材质，例如氧化铝(Al2O5)、氧化铪(HfO2)、氧化锆(ZrO2)、或其它类似此性质者，其等效氧化层厚度(equivalent oxidethickness)约为3至100埃。
接着，形成一层导电层于闸极介电层30上，其材质可为多晶硅、多晶硅锗、耐火金属(refractory metal)、类金属化合物、或其它导电材质，其中耐火金属可为钼(Mo)、钨(W)等，类金属化合物可为氮化钛。
接着于导电层上覆盖一图案化罩幕层34，并借由蚀刻，将图案化罩幕层34的图案转移至导电层中，以形成闸极电极32，如图2D所示。以材质为多晶硅的导电层以及材质为氮氧化硅的闸极介电层30为例，其蚀刻条件例如是含氯和溴的蚀刻气体进行电浆蚀刻，其多晶硅对氮氧化硅的蚀刻选择比超过2000。
在完成闸极电极32的定义后，则移除其上方的图案化罩幕层34。
接着，进行源极/汲极的淡掺杂制程，其形成方法例是以离子植入、电浆侵入式离子植入(plasma immersion ion implantation，PIII)、或是其它的技术来进行。
接着，借由沉积以及选择性非等向性地蚀刻介电材质，以于闸极电极32以及鳍形硅层26a的侧壁形成间隙壁36，间隙壁36的材质可为氮化硅或氧化硅。位于鳍形硅层26a侧壁的间隙壁可以利用另外的蚀刻制程加以移除，如图2E所示。之后进行源极/汲极的浓掺杂制程，其形成方法例是以离子植入、电浆侵入式离子植入、固体源扩散(solid sourcediffusion)、或是其它的技术。在此步骤中，亦可以根据需要，同时将离子掺杂入闸极电极26a，借此提高其导电性。任何植入的伤害或非晶化可借由后续高温回火制程而获得改善。
经过上述的源极/汲极的淡掺杂制程和浓掺杂制程后，于闸极电极26a两侧的鳍形硅层26a中形成具有浅掺杂汲极结构(lightly dopeddrain)LDD的源极/汲极S/D，如图3的上视图所示。
接着请参照图2F，为了降低源极/汲极S/D的片电阻，因此在源极/汲极S/D表面形成一层导电层38，意即，此导电层38形成于鳍形硅层的顶部和侧壁。导电层38的材质例如是以自动对准金属硅化物制程(self-aligned silicide process，salicide process)形成的金属硅化物，例如硅化钴。该材质亦可为金属、多晶硅、或是磊晶硅。
之后，沉积一层高应力膜层40覆盖于闸极电极32上和导电层38上，其厚度约为50～1000埃，如图2G所示。由于鳍形硅层26a和高应力膜层40两者之间的热膨胀系数(thermal expansion coefficient)及杨氏系数(Young’s modulus)有很大的差异(见表一)，使得在经过半导体制程中所需的高温沉积或热回火制程后，高应力膜层40自高温降温时的收缩速度和鳍形硅层26a的收缩速度会有很大的差异，因此会将应力导入鳍形硅层26a的通道区中，产生的应力可能是数百MPa甚至超过1GPa。
表一  可以选择用于制备高应力膜层40的绝缘
材质的热膨胀系数及杨氏系数
                              热膨胀系数     杨氏系数
                               α(K-1)       E(GPa)
氧化锆(zirconium oxide)         1.11×10-5   200
块滑石(steatite；MgOSiO2)       8.0×10-6    -
氧化铝(aluminum oxide)          7.7×10-6    390
氮化铝(aluminum nitride)          5.1×10-6             380
碳化硅(silicon carbide)           4.3×10-6             400
氮化硅(silicon nitride)           2.8×10-6～3.6×10-6 306
硅(silicon)                       2.0×10-6             156
氧化硅(silicon oxide)             5.0×10-7             -
如果高应力膜层40的热膨胀系数小于鳍形硅层26a，则鳍形硅层26a会感受到压缩应变(compressive strain)。若高应力膜层40施与通道区的应变为压缩应变，则电洞载子的迁移率可获得提升。因此，覆盖于高应力膜层40下方的闸极电极36和源极/汲极S/D构成的晶体管为PMOS晶体管。上述的应变是指沿源极至汲极方向的压缩应变，鳍形硅层26a中的压缩应变强度为0.01％至2％，较佳的是0.1％至2％，更佳的是1％至2％。
如果高应力膜层40的热膨胀系数大于鳍形硅层26a，则鳍形硅层26a会感受到拉伸应变(tensile strain)。若高应力膜层40施与通道区的应变为拉伸应变，则电子和电洞载子两者的迁移率均可获得提升。因此，覆盖于高应力膜层40下方的闸极电极36和源极/汲极S/D构成的晶体管可为PMOS晶体管和NMOS晶体管。上述的应变是指沿源极至汲极方向的拉伸应变，鳍形硅层26a中的拉伸应变强度为0.01％至2％，较佳的是0.1％至2％，更佳的是1％至2％。
就高应力膜层40而言，借由控制形成的条件，可以调整所形成的膜层的应力大小，根据研究，可控制应力的因素有温度、压力或制程气体的流速比。举例而言，利用电浆增强型化学气相沉积的氮化硅(plasma-enhanced chemical vapor deposited silicon nitride)可以导入至通道区中的应力可为拉伸应力或压缩应力，端视沉积的条件而定。此外，若选择氧化硅制备高应力膜层40，还可以借由改变掺杂的物质及掺杂的浓度来改变其热膨胀系数及杨氏系数，可以掺杂的物质例如是锗(Ga)、氮(N)或耐火的金属(refractory metal)。
如上所述，本发明的具有多重闸极及应变的通道层的晶体管，借由其垂直型的结构，使晶体管的积集度可以有效地提升；并借由应力膜层的覆盖，使应力导入通道区中而引发拉伸应变或压缩应变，以提高载子的迁移率，进而提升组件的操作效能。
本发明的具有多重闸极及应变的通道层的晶体管，可视为三个并联的晶体管，分别位于鳍形硅层两侧及顶面。该结构可有效提高组件的电流量。

Claims (25)

1.一种具有多重闸极及应变的通道层的晶体管，其特征在于所述晶体管包括：
一基底；
一垂直型鳍形半导体层位于该基底上，该垂直型鳍形半导体层具有一源极、一汲极以及位于该源极和该汲极之间的一通道区，且该垂直型鳍形半导体层中具有一应变；
一闸极绝缘层位于该垂直型鳍形半导体层的该通道区表面；以及
一闸极电极位于该闸极绝缘层上，并包覆对应于该通道区的该垂直型鳍形半导体层的两侧壁和一顶面。
2.根据权利要求1所述的具有多重闸极及应变的通道层的晶体管，其特征在于：该应变为沿该源极至该汲极方向的拉伸应变。
3.根据权利要求2所述的具有多重闸极及应变的通道层的晶体管，其特征在于：该垂直型鳍形半导体层中的该拉伸应变强度为0.01％至2％。
4.根据权利要求2所述的具有多重闸极及应变的通道层的晶体管，其特征在于：更包括一应力膜层位于该源极和该汲极上，该应力膜层的热膨胀系数大于该垂直型鳍形半导体层的热膨胀系数。
5.根据权利要求1所述的具有多重闸极及应变的通道层的晶体管，其特征在于：该应变为沿该源极至该汲极方向的压缩应变。
6.根据权利要求5所述的具有多重闸极及应变的通道层的晶体管，其中该垂直型鳍形半导体层中的该压缩应变强度为0.01％至2％。
7.根据权利要求5所述的具有多重闸极及应变的通道层的晶体管，其特征在于：更包括一应力膜层位于该源极和该汲极上，该应力膜层的热膨胀系数小于该垂直型鳍形半导体层的热膨胀系数。
8.一种具有多重闸极及应变的通道层的晶体管，其特征在于所述晶体管包括：
一基底；
一垂直型鳍形半导体层位于该基底上，该垂直型鳍形半导体层具有一源极、一汲极以及位于该源极和该汲极之间的一通道区；
一闸极绝缘层位于该垂直型鳍形半导体层的该通道区表面；
一闸极电极位于该闸极绝缘层上，并包覆该垂直型鳍形半导体层的两侧壁和一顶面的该通道区；以及
一应力膜层位于该源极和该汲极上，借以将应力导入该垂直型鳍形半导体层中，使该垂直型鳍形半导体层具有一应变。
9.根据权利要求8所述的具有多重闸极及应变的通道层的晶体管，其特征在于：该应变为沿该源极至该汲极方向的拉伸应变。
10.根据权利要求9所述的具有多重闸极及应变的通道层的晶体管，其特征在于：该垂直型鳍形半导体层中的该拉伸应变强度为0.01％至2％。
11.根据权利要求9所述的具有多重闸极及应变的通道层的晶体管，其特征在于：更包括该应力膜层的热膨胀系数大于该垂直型鳍形半导体层的热膨胀系数。
12.根据权利要求8所述的具有多重闸极及应变的通道层的晶体管，其特征在于：该应变为沿该源极至该汲极方向的压缩应变。
13.根据权利要求12所述的具有多重闸极及应变的通道层的晶体管，其特征在于：该垂直型鳍形半导体层中的该压缩应变强度为0.01％至2％。
14.根据权利要求12所述的具有多重闸极及应变的通道层的晶体管，其特征在于：该应力膜层的热膨胀系数小于该垂直型鳍形半导体层的热膨胀系数。
15.一种具有多重闸极及应变的通道层的晶体管的制造方法，包括：
提供一基底，该基底包括一半导体层和一位于该半导体下的绝缘层；
定义该半导体层以形成一鳍形半导体层；
在该鳍形半导体层表面形成一闸极介电层；
在该闸极介电层上形成一导电层；
定义该导电层以形成一跨于该鳍形半导体层两侧壁和顶面的闸极电极；
形成一源极和一汲极于该闸极电极两侧的该鳍形半导体层中；以及
沉积一应力膜层于该源极和该汲极上，以将机械应变导入该鳍形半导体层中。
16.根据权利要求15所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中在形成该鳍形半导体层后且在形成该闸极介电层之前，更包括对该鳍形半导体层进行一表面平滑化处理。
17.根据权利要求16所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中该表面平滑化处理包括牺牲式氧化以及在含氢的环境下进行高温回火。
18.根据权利要求15所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中该源极和该汲极的形成方法包括：
进行淡掺杂制程，以于未为该闸极电极覆盖的该鳍形半导体层中形成浅掺杂区；
于该闸极电极两侧形成一间隙壁；以及
进行浓掺杂制程，以于未为该闸极电极和该间隙壁覆盖的该鳍形半导体层中形成浓掺杂区。
19.根据权利要求15所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中在形成该源极和该汲极之后且在沉积该应力膜层之前，更包括于该鳍形半导体层中的该源极和该汲极的表面形成一导电层。
20.根据权利要求15所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中该应变为沿该源极至该汲极方向的拉伸应变。
21.根据权利要求20所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中该垂直型鳍形半导体层中的该拉伸应变强度为0.01％至2％。
22.根据权利要求20所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中该应力膜层的热膨胀系数大于该垂直型鳍形半导体层的热膨胀系数。
23.根据权利要求15所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中该应变为沿该源极至该汲极方向的压缩应变。
24.根据权利要求23所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中该垂直型鳍形半导体层中的该压缩应变强度为0.01％至2％。
25.根据权利要求23所述的具有多重闸极及应变的通道层的晶体管的制造方法，其中位于该闸极电极和该闸极绝缘层上的该应力膜层的热膨胀系数小于该垂直型鳍形半导体层的热膨胀系数。
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