CN1507071A - 具有受应力通道的场效应晶体管及其制造方法 - Google Patents

具有受应力通道的场效应晶体管及其制造方法 Download PDF

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CN1507071A
CN1507071A CNA031597173A CN03159717A CN1507071A CN 1507071 A CN1507071 A CN 1507071A CN A031597173 A CNA031597173 A CN A031597173A CN 03159717 A CN03159717 A CN 03159717A CN 1507071 A CN1507071 A CN 1507071A
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布鲁斯·B·多丽丝
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杜尔塞蒂·奇达姆巴拉奥
泽维尔·贝依
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杰克·A·曼德尔曼
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德文德拉·K·萨达纳
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多米尼克·J·谢皮斯
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Abstract

本发明公开了一种具有由于电流通道22中的应力而增大的电荷载流子迁移率的场效应晶体管。应力沿电流流动方向(纵向)。在PFET器件中，应力为压力；而在NFET器件中，应力为拉力。应力通过通道下区域32中的压缩膜34而建立。压缩膜向上推起通道22，并导致了通道22的弯曲。在PFET器件中，压缩膜位于通道的端部31下(即位于源极和漏极下)，从而导致通道上部22A中的压缩。在NFET器件中，压缩膜位于通道的中部40下(即位于栅极下)，从而导致通道上部中的拉伸。因此，NFET和PFET器件都可被增强。本发明还公开了一种制造该器件的方法。

Description

具有受应力通道的场效应晶体管及其制造方法
技术领域
本发明一般性地涉及诸如CMOS晶体管的场效应晶体管。更加特别地，本发明涉及一种用于形成具有受应力通道区(stressed channel region)的场效应晶体管的方法，受应力通道区提供了增大的驱动电流能力以及其它的优点。
背景技术
诸如CMOS晶体管的场效应晶体管已被广泛地应用于电子行业。在几乎每一种应用电子电路中都采用了场效应晶体管(FET)，诸如信号处理、计算以及无线通信。一直以来，存在着对于改进场效应晶体管性能的要求。感兴趣的性能指标包括开关速度(switching speed)、开态电流容量(on-statecurrent capability)、以及开态对闭态(off-state)的电流比。这些指标倾向于通过增大FET的电荷载流子迁移率而得到改善。进而，研究人员已经对用于增大FET的电荷载流子迁移率的技术进行了研究。
已发现，施加至FET电流通道的机械应力可增大电荷载流子迁移率。例如，IEEE Transactions on Electron Devices，Vol.38，No.4，1991年4月，作者为Hamada等人的“A New Aspect of Mechanical Stress Effects in ScaledMOS Devices”中介绍了一些实验结果，其中P型FET(PFET)和N型FET(NFET)MOS晶体管的性能特征被作为机械应力的函数来测量。其报道了，PFET器件中的纵向(沿电流流动方向)压缩(compression)使载流子迁移率增大，并且NFET器件中的纵向拉伸(tension)使载流子迁移率增大。
然而，将机械应力引入微制造(microfabricated)的FET和CMOS器件已被证明存在一定的困难。过去，研究人员简单地弯折晶体管衬底。然而，这种技术对于大规模生产的集成电路是不适用的。施加应力的一个显著的问题是，PFET和NFET器件需要相反的应力。另外，用于在器件中产生应力的技术必须与现有的FET制造习惯以及封装技术兼容。
提供具有受应力通道区的FET将成为本领域的重大进步。能够生产在同一衬底上具有相反应力的PFET和NFET，从而同时改善了PFET和NFET器件将产生特别的好处。另外，能够利用传统的FET制造工艺制造具有受应力通道区的FET将带来极大的进步。
发明内容
本发明包括一种场效应晶体管，其具有电流通道、通道下的底切区、设置于通道上方的栅极电极。压缩膜设置于底切区中，并且压缩膜在电流通道中建立了纵向(电流流动方向)应力。
优选，应力的类型(压缩或拉伸)选择为使得晶体管具有增大的电荷载流子迁移率。具体地，在PFET晶体管中，应力应为压力，在NFET晶体管中为拉力。为建立PFET晶体管中的压应力，压缩膜应位于通道端部下。为建立NFET晶体管中的拉应力，压缩膜应位于通道中部下。
该压缩膜可由诸如氧化的多晶硅、氧化的非晶硅、氮化硅、氧化的SiGe的多种材料材料，或其它压缩膜制成。
本发明包括一种用于制造具有纵向应力的场效应晶体管的方法。该方法包括在通道下形成底切区；以及在底切区中形成压缩膜。底切区中的压缩膜向上推起通道，从而建立通道中的应力。通道可在中部被释放。底切区可通过蚀刻通道下的埋入氧化层形成。
另外，本发明包括一种场效应晶体管，其具有埋入氧化层、设置于埋入氧化层上的通道、通道下的底切区、以及设置于通道上方的栅极。压缩膜设置于底切区中，并且压缩膜在通道中建立了纵向应力。该底切区通过蚀刻埋入氧化层而形成。
附图说明
图1示出了根据本发明的PFET；
图2示出了根据本发明的NFET；
图3A至8B示出了一种用于制造根据本发明的PFET的方法；以及
图9A至13C示出了一种用于制造根据本发明的NFET的方法。
具体实施方式
本发明提供了具有用于增强电荷载流子迁移率的受应力通道区的NFET和PFET场效应晶体管(例如，CMOS器件)。本发明还提供了一种用于制造具有受应力通道的FET的方法。在本发明中，通道区的边缘被底切(undercut)掉(例如，利用等向性的蚀刻剂)。然后，在底切区中沉积压缩膜。压缩膜向上将通道从底切区中推起，从而使通道弯曲，并且将应力引入通道。根据压缩薄膜的设置，通道中的纵向应力将为压缩的或拉伸的。选择应力的类型(例如压缩或拉伸的)从而产生期望的FET中性能的变化。具体地说，PFET器件需要纵向压缩应力来增大电荷迁移率，而NFET器件需要纵向拉伸应力来增大电荷迁移率。
图1示出了根据本发明的PFET的侧视图。埋入氧化层(BOX)设置在衬底20上。衬底20可由硅或其它材料制成，而BOX可由二氧化硅制成。电流通道22设置在BOX上。源极区24和漏极区26连接至通道22。栅极28设置在通道22上方，并且通过栅极绝缘体30与通道隔开，栅极绝缘体30例如可由热氧化物制成。蚀刻BOX(例如，通过等向性蚀刻)，使得底切区32出现在通道22的端部31A和31B处。压缩薄膜34位于底切区32中。压缩薄膜34可包括例如，汽相沉积的多晶硅或非晶硅或锗硅(其在沉积后被氧化)、氮化硅、或二氧化硅。纵向(即电流穿过通道22流动的方向)由箭头36指示。在硅通道的情况下，纵向36可沿<110>方向取向，并且晶片表面应为[100]平面，如现有技术中所知。本发明还可应用于具有其它晶体取向的晶体管。图1不必为机能器件；图2中未示出的额外的层(例如钝化层)以及电学接触和引线可在最终的机能器件中出现。
在图1的器件中，通道22的上部22A沿纵向受压缩应力，而通道22的下部22B沿纵向受拉伸应力。通道上部和下部中的应力由底切区32中的压缩薄膜34产生。具体地说，压缩薄膜34向上推起通道22的端部31A和31B，导致通道22如示地弯曲(即通道弯曲为从上面观察向下凹陷)。上部22A中的纵向压力使得电荷载流子迁移率增大，因为图1的器件为PFET。电荷载流子迁移率的增大也通过增大开态电流容量并不增加闭态电流而使开关速度增大。增大的电荷载流子迁移率的其它好处已为本领域所公知。
图2示出本发明的实施例，其中器件为NFET。在NFET中，需要纵向拉伸应力以增大电荷载流子迁移率。图2的实施例具有源极24、漏极26、栅极28、BOX和栅极绝缘体30。在该NFET中，底切区32设置于通道的中部40中，其紧接在栅极28下。通道22(位于源极24和漏极26下)的端部31A和31B未被底切。压缩薄膜34设置于底切区32中。
在图2的NFET中，压缩薄膜34向上推起通道的中部40，导致了通道22如示地在其中部40处向上弯曲。结果，通道弯曲为从上面观察通道22向上凸起。结果，上部22A受纵向拉伸应力，而下部22B受压缩应力。上部中的纵向拉伸应力提供了电荷载流子迁移率的增大。电荷载流子迁移率将正常地在下部22B中减小，由于其具有载流子迁移率增加所需的相反的应力。
应注意，在大多数FET中，通道的仅仅一部分承载电流。具体地说，电流在栅极28下的薄层(例如，约2至20nm厚)中流动。优选地，本器件设计为使得通道22的电流承载容量完全地或主要地位于上部22A其中。上部22A在PFET器件中处于压力下，而在NFET器件中处于拉力下。若电流承载层很厚，则上部22A就应该很厚。在一些器件中，电流承载层始终朝BOX沿伸。在此情况下，上部22A可始终朝BOX沿伸。对于上部22A设计为承载全部电流，就可以确保增加电荷载流子迁移率。
下面介绍用于制造根据本发明的PFET(图1的器件)的方法。图3A至8B示出了该方法的步骤。“B”图为“A”图沿点线41切开的横截面图；“A”图为顶视图。
图3A、3B：图3A为用于制造本发明器件的起始结构的顶视图，而图3B为其截面图。本技术领域已公知如何制造图3A和3B的结构。图3B沿为图3A的点线41的截面图。如本领域所公知，浅沟槽隔离材料(STI)与通道和垫片相邻地沉积。STI材料通常为通过高密度等离子体工艺沉积的邻四硅酸盐(TEOS)或二氧化硅。通道22可由硅制成，而垫片44可由氮化硅制成。通道具有与垫片相同的形状，如在图3A的顶视图中所见(通道可使用垫片44作为掩模形成)。通道可具有较宽范围的宽度，如2至200nm。
图4A、4B：沉积并构图掩模层46。掩模46具有开口48，其露出垫片44的端部和STI42的U形区。例如，掩模46可由光致抗蚀剂或图案化的硬掩模材料制成。开口48位于通道22将要沉积压缩膜34的端部的周围。
图5A、5B：进行蚀刻(例如非等向性等离子体蚀刻)，从而从开口48中去除STI，并且露出BOX。垫片44未被蚀刻。
图6A、6B：蚀刻BOX，从而通道22在底切区32中被底切掉。图6A中的点线45示出了底切区32的边界。底切区32位于通道22的端部，其适于制造PFET器件。还可在此工艺期间蚀刻STI，这导致了STI层底角的圆化。在替代的实施例中，氮化硅间隔壁形成于STI 42的侧壁上，用于保护STI侧壁不被蚀刻。在另一个替代的实施例中，BOX在一些位置被完全地去除，从而露出衬底。
图7A、7B：在底切区32中沉积压缩膜34。压缩膜34优选为保形的，如通过低压化学汽相沉积工艺形成的。压缩薄膜34沿箭头50的方向向上推起通道22，使得从上面观察时，通道具有向下凹陷的形状。由于压缩膜34的推动，通道的上部22A处于压缩下，而下部22B处于拉伸下。在压缩膜为氧化的硅或氧化的SiGe时，压缩薄膜可具有例如范围约5至1000nm的厚度。厚度是依据通道中期望的应力量和压缩膜34中固有压缩的量。
图8A、8B：孔中填充类似氧化物49的材料，并随后平整化(例如通过化学机械平整(CMP))器件。然后，进行垫片去除、栅极氧化、栅极叠层构图、间隔壁、源极漏极注入、活化退火和硅化，从而建立机能FET，如微电子制造领域所公知。通常也可增加钝化层和引线图案。
下面介绍一种用于制造根据本发明的NFET(图2的器件)的方法。图9A至13C示出了该方法的步骤。“B”图为“A”图沿点线43切开的横截面图；“A”图为顶视图。“B”图为清晰而被放大2倍。
图9A、9B：在图3A和3B的结构的顶上沉积掩模46。掩模46被构图以具有通道22的中部40上方的开口52，这将有利于NFET的制造。开口52比通道22和垫片44更宽，使得一些STI 42被暴露出来。
图10A、10B：进行蚀刻(例如非等向性等离子体蚀刻)，从而从开口52中去除STI，并且露出BOX。垫片44未被蚀刻。
图11A、11B：等向性蚀刻BOX，从而通道22在其中部40处被底切掉，并形成底切区32。点线55示出了底切区32的边缘。底切区32位于通道22的中部。在替代的实施例中，氮化硅间隔壁形成于STI 42的侧壁上，用于保护STI侧壁不被蚀刻。在替代的实施例中，蚀刻BOX直至底切区32被结合，并且中部40从衬底释放出来。
图12A、12B：压缩膜34沉积在底切区32中。压缩膜34在通道22的中部40中向上推起通道22。
图13A、13B：孔中用氧化物49填充，并且随后平整化器件。然后，形成源极和漏极的接触，形成栅极，并添加杂质以形成机能场效应晶体管，如微电子制造领域所公知。
图13C为图13A沿点线57切开的横截面图。压缩膜34沿箭头59的方向在通道22的中部40向上推起。这产生了通道上部中的纵向拉伸应力，该部分为通道承载电流的部分。进而，增大NFET的载流子迁移率。
PFET和NFET器件可在同时制造。例如，掩模46对于PFET和NFET器件可以为相同的掩模，而压缩膜34在PFET和NFET器件中可采用相同的步骤沉积。这提供了制造根据本发明的晶体管的有效方法。
在本发明的优选实施例中，压缩薄膜包括氧化的多晶硅或氧化的非晶硅，尽管其它的压缩膜材料也是适用的。
本发明中提供的纵向应力可提供与无纵向应力的等效晶体管相比的10％至20％的开关速度和开态电流容量的增加。性能的改善是显著的，并且将有助于降低成本和增加电子电路的功能性。
本晶体管的通道可由多种材料制成，包括除硅以外的，诸如锗、碳化硅或砷化镓的材料。应注意，在这些和其它的材料中，迁移率对应力的依赖关系可能与在硅中的不同。例如，在一些材料体系中，PFET的迁移率可通过纵向拉伸应力增大，而NFET的迁移率可通过纵向压缩应力增大。在此情况下，此处示出的PFET和NFET结构可反过来。还应注意，晶体取向可影响应力对通道的依赖。另外，不同的材料可需要与电流相关的不同的晶体取向，以实现施加应力的好处。
对本领域技术人员，显而易见，上述实施例可按多种方式变化，而不脱离本发明的范围。因此，本发明的范围应由所附权利要求和其等效范围确定。

Claims (15)

1.一种场效应晶体管，包括：
a)通道；
b)通道下的底切区；
c)设置于通道上方的栅极电极；以及
d)底切区中的压缩膜，其中，压缩膜在通道位于栅极电极下的区域中建立了纵向应力。
2.如权利要求1所述的晶体管，其中，该晶体管为PFET，并且通道的上部处于纵向压缩应力下。
3.如权利要求1所述的晶体管，其中，该晶体管为NFET，并且通道的上部处于纵向拉伸应力下。
4.如权利要求1所述的晶体管，其中，该晶体管为PFET，并且底切区设置于通道的端部下。
5.如权利要求1所述的晶体管，其中，该晶体管为NFET，并且底切区设置于通道的中部下。
6.如权利要求1所述的晶体管，其中，该晶体管为PFET，并且晶体管包括源极下的底切区和漏极区下的底切区。
7.如权利要求1所述的晶体管，其中，该压缩膜利用从由氧化的多晶硅、氧化的非晶硅、氮化硅、氧化的SiGe和热氧化硅构成的组中选取的材料制成。
8.一种用于制造具有受纵向应力的电流通道的场效应晶体管的方法，包括步骤：
a)在通道下形成底切区；以及
b)在底切区中形成压缩膜，从而在通道中建立纵向应力。
9.如权利要求8所述的方法，其中，该底切区位于通道端部处。
10.如权利要求8所述的方法，其中，该底切区位于通道中部的下面。
11.如权利要求10所述的方法，其中，该通道在中部被释放。
12.如权利要求8所述的方法，其中，该底切区通过从通道下蚀刻埋入氧化层而建立。
13.如权利要求8所述的方法，其中，该压缩膜通过沉积多晶硅并随后氧化该多晶硅而形成。
14.一种场效应晶体管，包括：
a)埋入氧化层；
b)设置于埋入氧化层上的通道；
c)通道下的底切区；
d)设置于通道上方的栅极电极；以及
e)底切区中的压缩膜，其中，压缩薄膜在通道位于栅极电极下的区域中建立了纵向应力。
15.如权利要求14所述的晶体管，其中，该底切区为被蚀刻的埋入氧化材料的区域。
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