CN1516903A - 减小结电容的soi器件 - Google Patents

减小结电容的soi器件 Download PDF

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CN1516903A
CN1516903A CNA02811244XA CN02811244A CN1516903A CN 1516903 A CN1516903 A CN 1516903A CN A02811244X A CNA02811244X A CN A02811244XA CN 02811244 A CN02811244 A CN 02811244A CN 1516903 A CN1516903 A CN 1516903A
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buried oxide
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silicon
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古川俊治
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Core Usa Second LLC
GlobalFoundries Inc
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands

Abstract

一种硅/绝缘体(SOI)场效应晶体管(FET)包含硅衬底，其硅层在氧化物埋层上，氧化物埋层有掺杂区和未掺杂区。掺杂区的介电常数不同于未掺杂区。硅层中还有一本体区将硅层中的源/漏区分开。源/漏区安排在掺杂区上面，而本体区安排在未掺杂区上面。栅介电层在本体区上面，而栅导体层在栅介电层上面。

Description

减小结电容的SOI器件
技术领域
本发明涉及到硅/绝缘体(SOI)场效应晶体管(FETs)领域，更确切地说，涉及到一种减小结区电容的SOI FET和所述器件的制作方法。
背景技术
在SOI技术中，硅层制作在绝缘层如氧化硅上，而绝缘层则制作在衬底上。此绝缘层常称为氧化物埋层(BOX)或简称BOX。晶体管的源区和漏区是，例如，在薄硅层中离子注入n型或p型掺杂剂而成的，在源与漏间形成本体区。栅极则由，例如，在薄硅层表面上淀积栅介电层和导体层，接着光刻图形并腐蚀而成。
SOI技术的FET比采用硅体材料技术构造的FET有很大的优越性。SOI技术的优点有减小短沟道效应、较低的寄生电容和增大漏极开态电流。然而，随着SOI FET尺寸日益缩小带来的优点是，例如，减小结区电容，而随着BOX的缩小(减薄)，结区电容增大。结区电容的增大又引起器件性能退降。
转至图1，图1为SOI FET的部分剖面图，说明了各种有源和寄生电容。FET 100包含硅衬底105、制作在衬底上的BOX 110、以及制作在BOX上面的薄硅层115。FET 100还包含制作在硅层115中的源/漏区120以及也制作在硅层中使源/漏分开的本体区125。FET 100还包含栅介电层130、栅导体层135、以及制作在栅导体层135侧壁145上的侧壁隔层140。从硅层115上表面150，经硅层延伸至BOX 110的是浅沟道隔离层(STI)155。
有源和寄生电容的位置如下。在栅导体层135与本体区125之间存在有前栅电容160。前栅电容160的介电层是栅介电层130。在源/漏区120各自与衬底105间存在有结区电容165。在本体区125与衬底105间存在有背栅电容170。结区电容165和背栅电容170的介电层为BOX 110。这些电容的容量由熟知的公式给出：
C＝ε0εOX/TOX
式中C为电容，ε0为自由空间的介电常数，εOX为介电层的介电常数，和TOX为介电层的厚度。希望前栅电容160要大，以增大开态电流和减小关态电流。这是由减小栅介电层130的厚度或使用介电常数更高的材料作为栅介电层来实现的。出于上述原因，希望结区电容165要小。然而，又同时希望背栅电容170要大。希望背栅电容170大的原因是改善对关态电流的控制和阈值电压的控制。由于结区电容165和背栅电容170的介电层都是BOX 110，显然不能同时优化结区电容和背栅电容。
图2为说明各种有源和寄生电容的双BOX SOI FET的部分剖面图。图2的目的是说明双BOX SOI器件仍有上述单BOX器件的问题。FET 200包含硅衬底205、制作在衬底上的第一厚BOX 210、制作在第一BOX上的第一薄硅层215，掺杂至1018-1019原子/cm3、制作在第一硅层上的第二薄BOX 220、以及制作在第二BOX上的第二薄硅层225。FET 200还包含制作在第二硅层225中的源/漏区230和也制作在第二硅层中使源/漏区分开的本体区235。FET 200还包含栅介电层240、栅导体层245、以及制作在栅导体层245侧壁255上的侧壁隔层250。从第二硅层225上表面255，经第二硅层、第二BOX220、第一硅层215延伸至第一BOX 210的是STI 260。
其有源和寄生电容的位置如下。在栅极245与本体区235间存在有前栅电容265。前栅电容265的介电层是栅介电层240。在源/漏区230各自与第一硅层215间存在有结区电容270。在本体区235与第一硅层215间存在有背栅电容275。结区电容270和背栅电容275的介电层是第二BOX 220。在第一硅层215与衬底205间存在有衬底电容280。衬底电容280的介电层是第一BOX 210。虽然第一BOX210可为厚层以减小衬底电容280的容量，又由于结区电容270和背栅电容275的介电层都是第二BOX 220，显然，不能同时优化结区电容和背栅电容。
因此，需要一种制作SOI FET的方法，该FET具有小的结区电容和大的背栅电容，以在缩小尺寸时获得SOI技术的所有益处。
发明内容
本发明的第一方面为一种半导体结构，该结构包含：介电层，此介电层具有第一和第二区，第一介电区具有第一介电常数，第二介电区具有与第一介电常数不同的第二介电常数。
本发明的第二方面为一种SOI FET，包含：硅衬底，其硅层在具有掺杂区和未掺杂区的氧化物埋层上面，未掺杂区的介电常数与掺杂区的介电常数不同；硅层中的源/漏区被硅层中的本体区分开，源/漏区安排在掺杂区上面，本体区安排在未掺杂区上面；以及在本体区上面的栅介电层和在栅介电层上面的栅导体层。
本发明的第三方面为一种制作半导体结构的方法，包括：提供介电层；在此介电层中制作第一区，此第一区具有第一介电常数；以及在第二介电层中制作第二区，此第二区具有不同于第一介电常数的第二介电常数。
本发明的第四方面为一种制作SOI FET的方法，包括：提供硅衬底，其硅层在氧化物埋层上面；在硅层上制作栅介电层；在栅介电层上制作栅导体层；在硅层中制作源/漏区；源和漏区被硅层中的本体区分开，此本体区安排在栅极下面；以及在氧化物埋层中制作掺杂区，此掺杂区安排在源/漏区下面，且其介电常数不同于氧化物埋层未掺杂区的介电常数。
附图说明
本发明的特点在所附权利要求中做了描述。然而参照下面对所示实施方式的详细描述并结合附图，将可最好地了解此发明，其中：
图1为说明各种有源和寄生电容的SOI FET的部分剖面图；
图2为说明各种有源和寄生电容的双BOX SOI FET的部分剖面图；
图3A-3E为说明根据本发明第一种实施方式制作SOI FET的部分剖面图；
图4为说明根据本发明第一种实施方式制作的双BOX SOI FET的部分剖面图；
图5A-5F为说明根据本发明第二种实施方式制作SOI FET的部分剖面图；
图6为说明根据本发明第二种实施方式制作的双BOX SOI FET的部分剖面图；
图7为说明根据本发明第三种实施方式制作SOI FET的部分剖面图。
具体实施方式
参见图3A-3E，这是说明根据本发明第一种实施方式制作SOIFET器件的部分剖面图。此制作方法始于图3A，硅衬底300含有薄硅层310和衬底之间的BOX 305。从硅层310上表面315，经硅层延伸至BOX 305的是STI 320。STI 320可由以下步骤形成：先进行光刻，接着由硅衬底300的反应离子刻蚀(RIE)形成降至BOX 305的沟槽，再淀积绝缘体填充沟槽，然后进行化学机械抛光(CMP)打平表面来制成上表面315。在一个实例中，BOX 305是用离子注入氧来制成50-500厚的氧化硅，而硅层310为50-500厚，n型或p型掺杂至1016-1018原子/cm3。制作在上表面315上面的是栅介电层325。在一个实例中，栅介电层325为氧化硅，是用热氧化或化学汽相沉积(CVD)制作的，厚约10-50。在另一个实例中，栅介电层325为氮氧化硅，是用热氧化接着用遥控等离子体氮化(RPN)或非耦合等离子体氮化(DPN)使氧化物氮化而成的。在还有一个实例中，栅介电层325为高κ值材料，如用CVD制作的氧化铝或氧化铪。制作在栅介电层325上面的是栅导体层330，制作在栅导体层上面的是硬掩模335。在一个实例中，栅导体层330为用CVD制作的多晶硅，厚约500-2000，硬掩模335为用氧化或CVD制作的氧化硅、CVD制作的氮化硅、或其组合，厚100-1000。硬掩模335用来防止以后的离子注入过程透入栅导体层330或栅介电层325，如图3D所示和下面所述。制作在硬掩模335上的是光致抗蚀剂340。对光致抗蚀剂340刻制FET的栅极图形，使之安排在STI 320间的硅层310上。
在图3B中，用RIE工艺使光致抗蚀剂图形340转换为栅导体层330和硬掩模335的图形，然后除去光致抗蚀剂。在栅极330/硬掩模335的侧壁350上制作侧壁隔层345。侧壁隔层345可用保形(conformal)淀积介电材料然后进行RIE工艺而成。在一个实例中，侧壁隔层345为氮化硅，在侧壁隔层345/栅介电层325的界面360处其宽度为约100-2000。
在图3C中，源/漏区365已制作在硅层310中，是用离子注入n型或p型掺杂剂至浓度为1019-1021原子/cm3，接着进行退火而成的。侧壁隔层345限制了源/漏区365在栅极330下面的扩展。硅层310在源/漏区365之间和栅极330下面的区域现在为本体区370。显然，对于PFET，源/漏区365为p型掺杂，本体区370为n型，而对于NFET，源/漏区365为n型掺杂，本体区370为p型。应看到，图3C说明的是全耗尽型器件，但也可说明部分耗尽型器件。
在图3D中，进行氟的离子注入，在BOX 305中产生富氟氧化物区375。侧壁隔层345限制了富氟氧化物区375在栅极330下面的扩展。氟的注入是在这样的条件下进行的，即，其能量使注入分布的峰值在BOX 305内，并有充足的剂量使BOX 305在图3E说明并如下面所述的退火步骤后，其介电常数降低5-25％。在一个实例中，氟注入的剂量为约1×1014-1×1017原子/cm2，能量为约2-40Kev。
在图3E中，为了激活氟，在氮气或其他惰性气氛中在600-1100℃下进行退火。氟的激活驱使氟进入氧化硅晶格而产生氟化BOX380。氟化BOX 380在本体区370中没有明显的扩展。在一个实例中，BOX 305的介电常数为3.9，而氟化BOX 380的介电常数为约3.7-2.9。参见图1和图3E，由于BOX 305和氟化BOX 380的TOX是相同的，但BOX 305的εOX高于氟化BOX 380的εOX，则由源/漏区365、氟化BOX 380和衬底300组成的结区电容的容量小于由本体区370、BOX 305和衬底300组成的背栅电容的容量。
图4为说明根据本发明第一种实施方式制作双BOX SOI FET的部分剖面图，并且除了添加在BOX 305和氟化BOX 380下面的第二硅层385和在第二硅层与衬底300间的第二BOX 390之外，与图3E相同。此外，STI 320经氟化BOX 380、第二硅层385延伸至第二BOX 390。
图5A-5F为说明根据本发明的第二种实施方式制作SOI FET的部分剖面图。图5A-5C与上述的图3A-3C相同。此制作方法始于图5A，硅衬底400含有介于薄硅层410和衬底之间的BOX 405。从硅层410上表面415，经硅层延伸至BOX 405的是STI 420。在一个实例中，BOX 405包含厚约50-500的氧化硅，硅层410厚50-500，p型或n型掺杂至约1015-1018原子/cm3。制作在上表面415上面的是栅介电层425。在一个实例中，栅介电层425是厚为约10-50的二氧化硅。制作在栅介电层425上面的是栅导体层430，制作在栅导体层上面的是硬掩模435。在一个实例中，栅导体层430为多晶硅，厚约500-2000，硬掩模435为氧化硅、氮化硅或其组合，厚100-1000。硬掩模435用来防止以后的离子注入过程透入栅导体层430或栅介电层425，如图5E所示和下面所述。制作在硬掩模435上面的是光致抗蚀剂440。对光致抗蚀剂440刻制FET栅极图形，并使之安排在STI 420间的硅层410上。
在图5C中，源/漏区465已制作在硅层410中，是用离子注入n型或p型掺杂剂至浓度为约1019-1021原子/cm3，接着进行退火而成的。侧壁隔层445限制了源/漏区465在栅极430下面的扩展。硅层410在源/漏区465之间和栅极430下面的区域现在为本体区470。应看到，图5C说明的是全耗尽型器件，但也可说明部分耗尽型器件。
在图5D中，第二侧壁隔层475制作在第一侧壁隔层445的侧面480上。在一个实例中，第二侧壁隔层475为氮化硅，在第二侧壁隔层475/栅介电层425的界面485处其宽度为约100-2000。
在图5E中，进行氟的离子注入，以在BOX 405中产生富氟氧化物区490。氟的注入是在这样的条件下进行的，即，其能量使注入分布的峰值在BOX 405内，并有充足的剂量使BOX 405在图3E说明的退火步骤后并如下面所述，其介电常数降低约5-25％。在一个实例中，氟注入的剂量为约1×1014-1×1017原子/cm2，能量为约2-40Kev。
在图5F中，为了激活氟，在氮气或其他惰性气氛中在600-1100℃下进行退火。氟的激活驱使氟进入氧化硅晶格而产生氟化BOX495。氟化BOX 495在本体区470中没有明显的扩展。在一个实例中，BOX 405的介电常数为3.9，而氟化BOX 495的介电常数为约3.7-2.9。参见图2和图5F，由于BOX 405和氟化BOX 495的TOX是相同的，但BOX 405的εOX高于氟化BOX 495的εOX，则由源/漏区465、氟化BOX 495和衬底400组成的结区电容的容量小于由本体区470、BOX 405和衬底400组成的背栅电容的容量。
图6为说明根据本发明第二种实施方式制作双BOX SOI FET的部分剖面图，并且除了在BOX 405和BOX 495下面添加第二硅层500和在第二硅层与衬底400间添加第二BOX 505外，与图5E相同。此外，STI 420经氟化BOX 495、第二硅层500延伸至第二BOX505。
图7为说明根据本发明第三种实施方式制作SOI FET的部分剖面图。图7拟更换图3D所示和上述的工艺。此外，去掉了制作硬掩模335的步骤。在图7中，在栅极330和栅介电层325的上表面515上制作第二光致抗蚀剂层510。对光致抗蚀剂层510刻制稍大于图3A所示的FET栅极图形，并安排得使侧壁520处于隔层345与STI320之间的源/漏区365上。这种实施方式特别适于具有长的栅长的大FET器件。
第二光致抗蚀剂层510的侧壁520限制了富氟氧化物区375在栅极330下面的扩展。氟的注入是在这样的条件下进行的，即，其能量使注入分布的峰值在BOX 305内，并有充足的剂量使BOX 305在图3E说明的退火步骤后，其介电常数降低约5-25％。在一个实例中，氟注入的剂量为约1×1014-1×1017原子/cm2，能量为约2-40Kev。
上面给出了对本发明各实施方式的描述以了解本发明。将会了解，本发明不只是此处所描述的特定实施方式，而是能够作出各种修改、重新安排和代换而不超出本发明的范围，对于本技术领域的熟练人员这都是明显的。例如，本发明可适用于凸起源/漏区的FET，其中的氟注入和退火步骤可在制作凸起的源/漏区之前或之后进行。此外，可将在制作源/漏区之前进行氟注入和退火步骤代之以在氟注入和退火后制作栅极，然后制作源/漏区隔层、注入和退火。

Claims (18)

1.一种硅/绝缘体(SOI)场效应晶体管(FET)包含：
硅衬底(300)，其硅层(310)在氧化物埋层(305)上面，氧化物埋层具有掺杂区(380)和未掺杂区(305)，所述未掺杂区的介电常数不同于所述掺杂区的介电常数；
在所述硅层中的源/漏区(365)，由所述硅层中的本体区(370)分开，所述源/漏区安排在所述掺杂区上面，而所述本体区安排在所述未掺杂区上面；以及
在所述本体区上面的栅介电层(325)和在所述栅介电层上的栅极(330)。
2.在权利要求1的SOI FET中，所述掺杂区的所述介电常数小于所述未掺杂区的所述介电常数。
3.在权利要求2的SOI FET中，所述掺杂区的所述介电常数比所述未掺杂区的所述介电常数小5-25％。
4.任何前述权利要求的SOI FET，其所述掺杂区是掺氟的。
5.在任何前述权利要求的SOI FET中，所述氧化物埋层为第一氧化物埋层，还包含在第二氧化物埋层上面的第二硅层，所述第二硅层和所述第二氧化物埋层处于所述第一氧化物埋层与所述衬底之间。
6.在权利要求1-5任一个的SOI FET中，所述硅层为50-500厚，所述氧化物埋层为50-500厚。
7.一种制作硅/绝缘体(SOI)场效应晶体管(FET)的方法，包括：
提供硅衬底(300)，其硅层(310)在氧化物埋层(305)上面；
在硅层上面制作栅介电层(325)；
在所述栅介电层上面制作栅导体层(330)；
在所述硅层中制作源/漏区(365)，所述源/漏区被所述硅层中的本体区分开，所述本体区安排在所述栅极下面；以及
在所述氧化物埋层中制作掺杂区(380)，所述掺杂区安排在所述源/漏区之下，且其介电常数不同于所述氧化物埋层未掺杂区(305)的所述介电常数。
8.在权利要求7的方法中，所述掺杂区通过注入氟而掺氟。
9.在权利要求8的方法中，氟的注入是在注入能量足以使氟注入分布的峰值处于所述氧化物埋层中的条件下进行的。
10.权利要求8或9的方法，还包括在600-1100℃的温度范围对所述SOI FET进行退火。
11.在权利要求7-10的任何方法中，所述掺杂区的所述介电常数比所述未掺杂埋层氧化物的所述介电常数低5-25％。
12.权利要求8-10的任何方法，还包括在所述栅极侧壁上制作第一隔层，以限制所述源/漏区和所述氟注入在所述栅极下面的扩展。
13.权利要求12的方法，还包括在所述第一隔层的侧面上制作第二隔层，以限制所述氟注入在所述栅极下面的扩展。
14.权利要求7的方法，还包括在所述栅极上面制作硬掩模。
15.权利要求8-10的任何方法，还包括在所述栅极上面刻制光致抗蚀剂图形层，所述光致抗蚀剂层的边缘扩展并安排至所述源/漏区上，以限制所述氟注入在所述栅极下面的扩展。
16.在权利要求7-15的任何方法中，所述硅层为50-500厚，所述氧化物埋层为50-500厚。
17.在权利要求7的方法中，所述氧化物埋层是第一氧化物埋层，还包含在第二氧化物埋层上的第二硅层，所述第二硅层和所述第二氧化物埋层处于所述第一氧化物埋层与所述衬底之间。
18.在权利要求8-10的任何方法中，所述氟的注入剂量为1×1014-1×1017原子/cm2，能量为2-40Kev。
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US20020185675A1 (en) 2002-12-12
US20030199128A1 (en) 2003-10-23
ATE456157T1 (de) 2010-02-15
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