CN1528018A - 倒装芯片的高性能硅接触 - Google Patents

倒装芯片的高性能硅接触 Download PDF

Info

Publication number
CN1528018A
CN1528018A CNA02807548XA CN02807548A CN1528018A CN 1528018 A CN1528018 A CN 1528018A CN A02807548X A CNA02807548X A CN A02807548XA CN 02807548 A CN02807548 A CN 02807548A CN 1528018 A CN1528018 A CN 1528018A
Authority
CN
China
Prior art keywords
layer
integrated circuit
dielectric layer
forms
shell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA02807548XA
Other languages
English (en)
Inventor
L・福尔贝斯
L·福尔贝斯
阿恩
K·Y·阿恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN1528018A publication Critical patent/CN1528018A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10252—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10271—Silicon-germanium [SiGe]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor

Abstract

本发明提供了一种半导体基片(12)，它包含前(14)、后(16)表面并有穿过基片在前(14)、后(16)表面之间伸展的小孔(18、20、22)。小孔(18、20、22)部分地由内壁部分界定并形成外部导电壳层。在贴近至少是一些内壁部分处形成导电材料(54)。接着，在孔内在导电材料上面径向朝内形成一层电介质材料(56)。然后在孔内在电介质材料层(56)上面径向朝内形成一层第二导电材料(60)。后一导电材料构成内部导电同轴线部件。

Description

倒装芯片的高性能硅接触
发明领域
本发明涉及集成电路的互连线，特别涉及穿过晶片的集成电路互连线。
相关技术的讨论
半导体器件一般是制造在一块晶片上，随后进行测试并分开成为分立的管芯或芯片。然后将分立的管芯进行封装。接着一般是在一块印刷电路板(PCB)上将封装的芯片装配在一起，并使其电互连以形成所要求的功能。分开制成的芯片的电互连通常是出现在分立芯片的外部。尽管PCB技术有利于使分开制成和装配的芯片组合在一起，可是这样作也带来了某些不易克服的问题。例如，与装在其上的芯片电路相比，PCB耗费了大量的实体空间。这样的PCB就提出了缩小实体空间的要求。此外，确保PCB上所装芯片之间电互连的牢固性也是一项挑战。而且，在某些应用当中，由于牵涉到信号损失或耗散和受到其它集成电路器件的干扰需要缩短器件之间电互连的实体长度。
半导体工业中的一项不断的挑战就是要谋求有一种新的、创造性的、而且是有效的方法，使与制造在相同或不同管芯上的电路器件及其之间形成电互连。与此相关的是，提出了不断的挑战以谋求和/或改进用于封装集成电路器件的封装技术，特别是在器件尺寸不断缩小的情况下尤为如此。
发明概要
本发明提供了更可靠而且更加适应缩小的电路尺寸的同轴互连线以及一种形成这种同轴互连线的方法。
提供一块包括前后表面的半导体基片，并且穿透基片在前后表面之间伸展一个小孔。小孔部分地是由其内壁部分界定的。在贴近至少是一些内壁部分处形成导电材料。此导电材料提供了一外部同轴线部件。随后，在小孔内，在导电材料上面径向朝内形成一层电介质材料。接着在小孔内的电介质材料层上面径向朝内形成第二导电材料。后一导电材料构成内部导电同轴线部件。
在一项优选方案中，通过在小孔内形成第一导电材料形成内部导电同轴线部件。在至少是以第二材料作为籽晶层的情况下，在第一材料上面形成第二材料。随后，在籽晶层上电镀一层含金属层。
可以将基片用作芯片的载体，或是基片可以有制造在它上面的电路部件以及它本身就可以形成为一块集成电路芯片。
附图简要说明
从如下结合附图所提供的详细说明中将会对本发明的上述优点与特征了解得更加清楚。
图1为本发明在一次工艺步骤时一块半导体晶片的片断剖视图；
图2为图1所示随后的工艺步骤时半导体晶片的片断剖视图；
图3为图1所示随后的工艺步骤时半导体晶片的片断剖视图；
图4为图3所示随后的工艺步骤时半导体晶片的片断剖视图；
图5为图4所示随后的工艺步骤时半导体晶片的片断剖视图；
图6为图5所示随后的替换工艺步骤时半导体晶片的片断剖视图；
图7为图6所示随后的工艺步骤时半导体晶片的片断剖视图；
图8为图7所示随后的工艺步骤时半导体晶片的片断剖视图；
图9为包含制造在晶片上的电路器件的图8半导体晶片的片断剖视图；
图10为包含安装在晶片上的集成电路芯片的图8半导体晶片的片断剖视图；以及
图11为在采用本发明一项典型实施方案的穿孔、同轴互连基于处理器的系统。
本发明的详细说明
下面将结合附图对本发明的典型实施方案进行说明。在不偏离本发明的精神或范围的情况下，可以用于其它的实施方案和对它进行结构或逻辑的修改。尽管下面描述了形成各种材料层的典型工艺条件，这些只属于代表性的并不意味着视为对本发明的限制。全部附图用相同的标号标注相同的项目。
以下说明中所用“基片”一词可以包含任何具有一露出的半导体表面的基于半导体的结构。基于半导体的结构必须理解成包括硅、电介质体上的硅(SOI)、蓝宝石上的硅(SOS)、掺杂和未掺杂的半导体、由基体半导体结构底座支撑的硅外延层以及其它的半导体结构。基于半导体的结构不一定就是基于硅的结构。半导体可以是硅-锗、锗或砷化镓。当在以下说明中提到基片时，可以是已在基体半导体或底座之内或上面利用先前的工艺步骤形成了区域或结。
参阅图1，一块半导体晶片的片断概括地以10表示并包含一个半导体基片12。基片12包括第一或前表面14和第二或后表面16。一方面，基片12是具有第一和第二外向表面14、16的半导体结构，两个外向表面中至少有一个是能够支撑所制造的集成电路的。基片12可以是由一块单晶硅晶片制成的。
参阅图2，在基片12内在前后表面14、16之间形成多个小孔或通道18、20和22。每个小孔或通道至少是部分地由相应的内壁部分19、21和23界定的。所图示的内壁部分构成小孔的内表面，它们与第一和第二表面14、16连接。小孔18、20和22可以是用参照图3和图4的下述任一合适的工艺技术形成的。
参阅图3，所示基片12在图2的结构之前在图1的结构上所应用的一工艺步骤。将一层诸如光刻胶的掩模材料24形成在前表面14上面并进行合适的图形加工，以界定多个窗孔26、28和30。窗孔26、28和30是形成在要在其中形成小孔18、20和22(图2)的基片区上面。可以进行一次碱性刻蚀，有效地形成预定刻蚀坑32、34和36的图形。接着，去除掩模材料层24。
参阅图4，接着用高密度低压(HDLP)的反应离子刻蚀(RIE)用SF6/C4F8以约2.2μm/min的速率进行一次穿透晶片的硅管沟刻蚀以形成小孔18、20和22。在此次刻蚀中可以用一层光刻胶作为掩模。采用连续的刻蚀/钝化循环以实现各向异性、深宽比高的管沟。在一项实施方案中，示例性深宽比可以大于100左右。更好的深宽比可以大于200左右。
参阅图5，在小孔或通道18、20和22的内部以及在相应内壁部分19、21和23的上面形成导电的外壳层50。外壳层50最好是在基片上、在小孔内及其相应孔壁部分19、20和23上面淀积一层含金属材料层54形成的。可以采用任何适合于设置这种含金属层的方法。一项示例性方法包括自限制工艺的低压化学汽相淀积(LPCVD)钨，它通过硅还原设置一层钨膜。于是小孔18、20和22内的硅材料被反应气体WF6中的钨原子取代，伴随着的是反应生成物SiF4被抽出或另外的从淀积室中排除。随后，这可随之以WF6的硅烷或聚合硅烷的还原，直至达到所需的导体厚度为止。在一项优选实施方案中薄层54的厚度为0.3μm左右至0.5μm左右。与上述情况相对应的淀积速度取决于温度和反应气体流速。在300℃左右温度下以及在冷壁的CVD反应器中以4sccm的WF6流速，示例性淀积速度为每分钟1微米。
参阅图6，在薄层54上面和小孔18、20和22内形成一层电介质材料层56。部分电介质层56被用来径向朝内形成内壁部分19、21和23以及导电外壳层50。一种示例性电介质材料是SiO2。替代地，电介质层56可以包含一层诸如Si3N4的含氮化物层，它被安排在贴近相应内壁部分19、21和23。在含氮化物层上面形成一层含氧化物层以便在小孔内设置一层SiON电介质层。在一项优选方案中，氮化物层是经化学气相淀积形成的，而氧化物层则是通过将基片曝露在氧化条件下产生的。具体地说，在优选方案中，电介质层56组成一层再氧化的LPCVD氮化物膜，它形成所举并优选的SiON电介质层。一项示例性工艺方案包括有在950℃下在氨气氛中进行原位氮化。在700℃下用二氯甲硅烷和氨气进行氮化物的低压化学汽相淀积直至填充小孔直径约三分之二时为止。随后在900℃至950℃之间的温度下进行氮化物的再氧化。
参阅图7，在电介质层56上面以及各自对应的小孔18、20和22内形成第一层导电材料58。按照一项优选方式，这样一层第一导电材料是经过合适的化学汽相淀积技术产生的多晶硅构成。于是，这样一层第一导电材料是在小孔18、20和22内径向朝内形成在电介质材料层56上面。第二层导电材料60则是形成在基片12和第一材料58的上面。按照一种方式，第二导电材料60包括不同于第一导电材料58的一种金属材料。按照一项优选方式，第二导电材料60构成一层铜的籽晶层，它形成在第一导电材料58上面。这样的材料或薄膜可以经过合适的溅射或蒸发技术进行淀积。可以利用机械掩模确定更为特定的区域，在其上面淀积优选的铜籽晶层。第二材料60最好是在前后表面14、16上面淀积达到约20至约40nm的厚度。接着，一层金属层，最好是铜层电镀在籽晶层60上形成完全填充小孔18、20和22内的薄层62。最好是使薄层62形成达2-3μm左右的厚度。
参阅图8，将薄层54、55、58、60和62相对于基片12进行平整，并隔离在各自的小孔18、20和22内。这一步骤可以通过任意合适的工艺技术完成。示例性技术有如通过化学机械抛光研磨基片。
此后，对诸如同轴集成电路互连线的集成电路连线的形成方法进行描述。提供一块半导体基片，它包括前后表面，并在前后表面之间伸展穿过基片形成小孔。小孔部分地是由内壁部分界定的。在贴近至少是一些内壁部分处形成导电材料，以形成一层外部导电层。随后，在小孔内、在导电材料上面径向朝内形成一层电介质材料。然后在小孔内在电介质材料层上面径向朝内形成一层第二导电材料。后一导电材料构成一条内部导电同轴线部件。在一项优选方案中，内部导电同轴线部件是通过在小孔内形成一层第一导电材料形成的。在至少以第二材料作籽晶层的情况下，在第一导电材料上面形成一层第二导电材料。随后，在籽晶层上电镀一层含金属层。
参阅图9和10，基片12还可以支撑制成的电路器件64和多层连线图形，并可以用单个集成封装中的密封剂68密封。在这样的方案中设置了多个外部引线端70，用于使内部封装的导线与外部的电路连接。此外，基片12可以是一个载体，用它安装、支撑以及互连安装在表面14、16的一面或两面上的其它集成电路芯片66。
图11绘示一个处理器系统102，它包括中央处理器(CPU)112，RAM和ROM存储器件108、110，输入/输出(I/O)装置104、106，软盘驱动器114和CD ROM驱动器116。所有上述部件在一条或多条总线系统118上互相连通。一个或多个中央处理器(CPU)112、RAM和ROM存储器件108、110制造在基片12上或是作为IC芯片如图9和10中绘示的按照本发明的穿孔、同轴互连安装在基片12载体上。此外，RAM 108可以由一个或多个存储器模块组成，它们各含具有按本发明制成的同轴互连的一个或多个存储电路。
尽管已经结合典型实施方案对本发明作了以上说明，但在不偏离本发明的精神与范围的情况下显然仍能作出许多修改与取代。因此，本发明并不认为受到前述说明的限制，而仅仅是受所附权利要求范围的限制。

Claims (53)

1.一种形成同轴集成电路互连线的方法，包括：
提供一具有前、后表面的基片；
形成以侧壁由所述前表面到所述后表面穿过所述基片伸展的小孔；
在所述侧壁上形成外部导电同轴壳层；
在所述外部导电同轴壳层上面径向朝内形成同轴电介质层；以及
在所述同轴电介质层上面径向朝内形成内部同轴线。
2.权利要求1的方法，其中所述形成内部同轴线的操作还包括以下操作：
形成内部导电层；
在所述内部导电层上面形成籽晶层；以及
在所述籽晶层上电镀金属。
3.权利要求1的方法，其中所述导电壳层是钨壳层。
4.权利要求3的方法，其中所述导电壳层是通过低压化学汽相淀积形成的。
5.权利要求4的方法，其中所述淀积是以每分钟约1微米的速度进行的。
6.权利要求1的方法，其中所述壳层形成达约0.3μm至约0.5μm的厚度。
7.权利要求1的方法，其中所述电介质层包含二氧化硅。
8.权利要求1的方法，其中所述电介质层形成达约0.5μm至约0.8μm的厚度。
9.权利要求1的方法，其中所述电介质层包括含氮化物层。
10.权利要求9的方法，其中所述含氮化物层是由低压化学汽相淀积形成的。
11.权利要求2的方法，其中所述内部导电层是多晶硅层。
12.权利要求2的方法，其中所述籽晶层形成达约20nm-40nm的厚度。
13.权利要求2的方法，其中所述金属是铜。
14.权利要求2的方法，其中所述电镀层约为2-3μm厚。
15.权利要求1的方法，还包括在所述基片上制造电路器件的操作。
16.权利要求1的方法，还包括在所述基片上安装集成电路芯片的操作。
17.权利要求16的方法，还包括包封所述集成电路芯片和基片的操作。
18.一种集成电路互连线，包括：
一具有前、后表面的基片；
以侧壁由所述前表面到所述后表面穿过所述基片伸展的小孔；
在所述侧壁上形成的外部导电同轴壳层；
在所述外部同轴线上面径向朝内形成同轴电介质层；以及
在所述同轴电介质层上面径向朝内形成的导电内部同轴线。
19.权利要求18的互连线，其中所述内部导电同轴线还包括：
一层内部导电层；
在所述内部导电层上面设置的一层籽晶层；以及
在所述籽晶层上的电镀金属层。
20.权利要求18的互连线，其中所述导电壳层包括钨层。
21.权利要求18的互连线，其中所述导电壳层形成达约0.3μm至约0.5μm的厚度。
22.权利要求18的互连线，其中所述电介质层包括二氧化硅。
23.权利要求18的互连线，其中所述电介质层形成达约0.5μm至约0.8μm的厚度。
24.权利要求18的互连线，其中所述电介质层包括含氮化物层。
25.权利要求18的互连线，其中所述电介质层包括氮化硅。
26.权利要求19的互连线，其中所述内部导电层是多晶硅层。
27.权利要求19的互连线，其中所述籽晶层形成达约20nm-40nm的厚度。
28.权利要求19的互连线，其中所述金属是铜。
29.权利要求19的互连线，其中所述电镀层约为2-3μm厚。
30.一种处理器系统，包括：
一处理器；以及
一与所述处理器耦连的集成电路，所述集成电路与处理器中至少一个包括：
一基片，具有前、后表面并具有一以侧壁由所述前表面到所述后表面穿过所述基片伸展的小孔；
一在所述侧壁上形成的导电外部同轴壳层；
在所述外部同轴壳层上面径向朝内形成的一层同轴电介质层；以及
在所述同轴电介质层上面径向朝内形成的一内部导电同轴线。
31.权利要求30的系统，其中所述内部同轴线还包括：
一层内部导电层；
在所述内部导电层上面设置的一层籽晶层；以及
在所述籽晶层上的一层电镀金属层。
32.权利要求30的系统，其中所述导电壳层是钨壳层。
33.权利要求30的系统，其中所述壳层形成达约0.3μm至约0.5μm的厚度。
34.权利要求30的系统，其中所述电介质层包括二氧化硅。
35.权利要求30的系统，其中所述电介质层形成达约0.5μm至约0.8μm的厚度。
36.权利要求30的系统，其中所述电介质层包括含氮化物层。
37.权利要求30的系统，其中所述电介质层包括氮化硅。
38.权利要求31的系统，其中所述内部导电层是多晶硅层。
39.权利要求31的系统，其中所述籽晶层形成达约20nm-40nm的厚度。
40.权利要求31的系统，其中所述金属是铜。
41.权利要求31的系统，其中所述电镀层约为2-3μm厚。
42.一种集成电路封装，包括：
一基片，支撑至少一片集成电路芯片，所述基片具有前、后表面和至少一以侧壁由所述前表面到所述后表面穿过所述基片伸展的小孔；
在所述侧壁上形成的一层外部导电同轴壳层；
在所述外部导电同轴壳层上面径向朝内形成一层同轴电介质层；和
在所述同轴电介质层上面径向朝内形成一内部导电同轴线；以及
一封装，包封住所述基片和所述至少一片芯片。
43.权利要求42的集成电路，其中所述内部同轴线还包括：
一层内部导电层；
在所述内部导电层上面设置的一层籽晶层；以及
在所述籽晶层上的电镀金属层。
44.权利要求42的集成电路，其中所述导电壳层是钨壳层。
45.权利要求42的集成电路，其中所述壳层形成达约0.3μm至约0.5μm的厚度。
46.权利要求42的集成电路，其中所述电介质层包括二氧化硅。
47.权利要求42的集成电路，其中所述电介质层形成达约0.5μm至约0.8μm的厚度。
48.权利要求42的集成电路，其中所述电介质层包括含氮化物层。
49.权利要求42的集成电路，其中所述电介质层包括氮化硅。
50.权利要求43的集成电路，其中所述内部导电层是多晶硅层。
51.权利要求43的集成电路，其中所述籽晶层形成达约20nm-40nm的厚度。
52.权利要求43的集成电路，其中所述金属是铜。
53.权利要求43的集成电路，其中所述电镀层约为2-3μm厚。
CNA02807548XA 2001-02-08 2002-02-01 倒装芯片的高性能硅接触 Pending CN1528018A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/778,913 US6737740B2 (en) 2001-02-08 2001-02-08 High performance silicon contact for flip chip
US09/778,913 2001-02-08

Publications (1)

Publication Number Publication Date
CN1528018A true CN1528018A (zh) 2004-09-08

Family

ID=25114748

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA02807548XA Pending CN1528018A (zh) 2001-02-08 2002-02-01 倒装芯片的高性能硅接触

Country Status (7)

Country Link
US (3) US6737740B2 (zh)
EP (1) EP1360723A2 (zh)
JP (1) JP4295509B2 (zh)
KR (1) KR100552551B1 (zh)
CN (1) CN1528018A (zh)
AU (1) AU2002243735A1 (zh)
WO (1) WO2002063686A2 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376689A (zh) * 2011-09-09 2012-03-14 华中科技大学 具有台阶的硅通孔结构及其制备工艺
CN102646778A (zh) * 2006-12-21 2012-08-22 Lg电子株式会社 发光器件包及其制造方法
CN103367285A (zh) * 2013-07-26 2013-10-23 中国科学院微电子研究所 一种通孔结构及其制作方法
CN107706173A (zh) * 2017-09-30 2018-02-16 成都嘉纳海威科技有限责任公司 硅通孔互联结构及其制备方法以及硅通孔射频传输结构

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6737740B2 (en) * 2001-02-08 2004-05-18 Micron Technology, Inc. High performance silicon contact for flip chip
US6750516B2 (en) * 2001-10-18 2004-06-15 Hewlett-Packard Development Company, L.P. Systems and methods for electrically isolating portions of wafers
JP2003273155A (ja) * 2002-03-18 2003-09-26 Fujitsu Ltd 半導体装置及びその製造方法
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
WO2004114397A1 (en) * 2003-06-20 2004-12-29 Koninklijke Philips Electronics N.V. Electronic device, assembly and methods of manufacturing an electronic device
US7230318B2 (en) 2003-12-24 2007-06-12 Agency For Science, Technology And Research RF and MMIC stackable micro-modules
US7866038B2 (en) * 2004-07-06 2011-01-11 Tokyo Electron Limited Through substrate, interposer and manufacturing method of through substrate
TWI250596B (en) * 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7560395B2 (en) 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
CA2607885A1 (en) * 2005-05-18 2006-11-23 Kolo Technologies, Inc. Through-wafer interconnection
CA2607916A1 (en) 2005-05-18 2006-11-23 Kolo Technologies, Inc. Micro-electro-mechanical transducers
US7510983B2 (en) * 2005-06-14 2009-03-31 Micron Technology, Inc. Iridium/zirconium oxide structure
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7884483B2 (en) 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
US7534722B2 (en) * 2005-06-14 2009-05-19 John Trezza Back-to-front via process
US8796901B2 (en) * 2005-06-17 2014-08-05 Kolo Technologies, Inc. Micro-electro-mechanical transducer having an insulation extension
JP4552770B2 (ja) * 2005-06-21 2010-09-29 パナソニック電工株式会社 半導体基板への貫通配線の形成方法
US7510907B2 (en) * 2005-06-22 2009-03-31 Intel Corporation Through-wafer vias and surface metallization for coupling thereto
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US9601474B2 (en) * 2005-07-22 2017-03-21 Invensas Corporation Electrically stackable semiconductor wafer and chip packages
DE102005039068A1 (de) * 2005-08-11 2007-02-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Halbleitersubstrat und Verfahren zur Herstellung
WO2007023416A1 (en) * 2005-08-26 2007-03-01 Philips Intellectual Property & Standards Gmbh Electrically shielded through-wafer interconnect
US7772115B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure
US8154105B2 (en) * 2005-09-22 2012-04-10 International Rectifier Corporation Flip chip semiconductor device and process of its manufacture
US7798817B2 (en) * 2005-11-04 2010-09-21 Georgia Tech Research Corporation Integrated circuit interconnects with coaxial conductors
US20080122040A1 (en) * 2006-06-29 2008-05-29 Icemos Technology Corporation Varying Pitch Adapter and a Method of Forming a Varying Pitch Adapter
US7605030B2 (en) 2006-08-31 2009-10-20 Micron Technology, Inc. Hafnium tantalum oxynitride high-k dielectric and metal gates
DE602007013281D1 (de) * 2006-12-12 2011-04-28 Nxp Bv Verfahren zur herstellung von öffnungen in einem substrat, insbesondere von durchgangslöchern durch ein substrat
US7705440B2 (en) * 2007-09-07 2010-04-27 Freescale Semiconductor, Inc. Substrate having through-wafer vias and method of forming
US7923808B2 (en) * 2007-11-20 2011-04-12 International Business Machines Corporation Structure of very high insertion loss of the substrate noise decoupling
WO2010035379A1 (ja) * 2008-09-26 2010-04-01 パナソニック株式会社 半導体装置及びその製造方法
US8062975B2 (en) * 2009-04-16 2011-11-22 Freescale Semiconductor, Inc. Through substrate vias
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
US8955215B2 (en) 2009-05-28 2015-02-17 Hsio Technologies, Llc High performance surface mount electrical interconnect
US9536815B2 (en) 2009-05-28 2017-01-03 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
WO2011139619A1 (en) 2010-04-26 2011-11-10 Hsio Technologies, Llc Semiconductor device package adapter
US9093767B2 (en) 2009-06-02 2015-07-28 Hsio Technologies, Llc High performance surface mount electrical interconnect
WO2010141298A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US8610265B2 (en) 2009-06-02 2013-12-17 Hsio Technologies, Llc Compliant core peripheral lead semiconductor test socket
US9231328B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc Resilient conductive electrical interconnect
WO2012078493A1 (en) 2010-12-06 2012-06-14 Hsio Technologies, Llc Electrical interconnect ic device socket
WO2010141295A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed flexible circuit
US8970031B2 (en) 2009-06-16 2015-03-03 Hsio Technologies, Llc Semiconductor die terminal
US8987886B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
WO2010141297A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US9184527B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Electrical connector insulator housing
US9603249B2 (en) 2009-06-02 2017-03-21 Hsio Technologies, Llc Direct metalization of electrical circuit structures
US8525346B2 (en) 2009-06-02 2013-09-03 Hsio Technologies, Llc Compliant conductive nano-particle electrical interconnect
US9054097B2 (en) 2009-06-02 2015-06-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US8912812B2 (en) 2009-06-02 2014-12-16 Hsio Technologies, Llc Compliant printed circuit wafer probe diagnostic tool
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
WO2011002712A1 (en) 2009-06-29 2011-01-06 Hsio Technologies, Llc Singulated semiconductor device separable electrical interconnect
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
US8955216B2 (en) 2009-06-02 2015-02-17 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor package
WO2010141296A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit semiconductor package
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US8928344B2 (en) 2009-06-02 2015-01-06 Hsio Technologies, Llc Compliant printed circuit socket diagnostic tool
US8789272B2 (en) 2009-06-02 2014-07-29 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor test socket
US9232654B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc High performance electrical circuit structure
WO2010141264A1 (en) 2009-06-03 2010-12-09 Hsio Technologies, Llc Compliant wafer level probe assembly
WO2011002709A1 (en) 2009-06-29 2011-01-06 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
US9699906B2 (en) 2009-06-02 2017-07-04 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
WO2010147782A1 (en) 2009-06-16 2010-12-23 Hsio Technologies, Llc Simulated wirebond semiconductor package
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
KR101585216B1 (ko) * 2009-10-28 2016-01-13 삼성전자주식회사 반도체 패키지, 이를 이용한 웨이퍼 스택 패키지 및 그 제조방법
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US8758067B2 (en) 2010-06-03 2014-06-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US8492878B2 (en) * 2010-07-21 2013-07-23 International Business Machines Corporation Metal-contamination-free through-substrate via structure
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
KR101215648B1 (ko) * 2011-02-11 2012-12-26 에스케이하이닉스 주식회사 반도체 칩 및 그 제조방법
USD692896S1 (en) * 2011-11-15 2013-11-05 Connectblue Ab Module
USD689053S1 (en) * 2011-11-15 2013-09-03 Connectblue Ab Module
USD680545S1 (en) * 2011-11-15 2013-04-23 Connectblue Ab Module
USD680119S1 (en) * 2011-11-15 2013-04-16 Connectblue Ab Module
USD668659S1 (en) * 2011-11-15 2012-10-09 Connectblue Ab Module
USD668658S1 (en) * 2011-11-15 2012-10-09 Connectblue Ab Module
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9470710B2 (en) 2013-02-27 2016-10-18 Texas Instruments Incorporated Capacitive MEMS sensor devices
US9351081B2 (en) 2013-02-27 2016-05-24 Texas Instruments Incorporated Capacitive micromachined ultrasonic transducer (CMUT) with through-substrate via (TSV) substrate plug
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
CN103745966B (zh) * 2014-01-23 2016-04-13 无锡江南计算技术研究所 封装基板表层铜柱电镀的辅助图形结构
US9755335B2 (en) 2015-03-18 2017-09-05 Hsio Technologies, Llc Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction
US11521923B2 (en) * 2018-05-24 2022-12-06 Intel Corporation Integrated circuit package supports
CN116093567A (zh) * 2023-02-20 2023-05-09 中国电子科技集团公司第十研究所 射频介质集成同轴长距离传输结构

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58201347A (ja) * 1982-05-20 1983-11-24 Unie Kurisutaru Kk リ−ドレスチツプ部品及びその製造方法
JPS61161746A (ja) * 1985-01-10 1986-07-22 Nec Corp 混成集積回路
JPS6239032A (ja) * 1985-08-14 1987-02-20 Matsushita Electric Works Ltd 電子素子用チツプキヤリア
JPS62241361A (ja) * 1986-04-14 1987-10-22 Hitachi Ltd 半導体装置
JPH0228358A (ja) * 1988-07-18 1990-01-30 I O Data Kiki:Kk 集積回路素子の実装方法
JP2925609B2 (ja) * 1989-11-30 1999-07-28 沖電気工業株式会社 半導体装置の製造方法
DE69122570T2 (de) * 1990-07-25 1997-02-13 Hitachi Chemical Co Ltd Leiterplatte mit Verbindung von Koaxialleitern untereinander
US5166097A (en) 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
JP3004071B2 (ja) 1991-04-16 2000-01-31 日本特殊陶業株式会社 集積回路用パッケージ
US5156998A (en) * 1991-09-30 1992-10-20 Hughes Aircraft Company Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal barrier layer to block migration of tin through via holes
JP3507251B2 (ja) * 1995-09-01 2004-03-15 キヤノン株式会社 光センサｉｃパッケージおよびその組立方法
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6130161A (en) * 1997-05-30 2000-10-10 International Business Machines Corporation Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity
US6143616A (en) 1997-08-22 2000-11-07 Micron Technology, Inc. Methods of forming coaxial integrated circuitry interconnect lines
EP0926729A3 (en) * 1997-12-10 1999-12-08 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package and process for the production thereof
US6114240A (en) 1997-12-18 2000-09-05 Micron Technology, Inc. Method for fabricating semiconductor components using focused laser beam
US6107109A (en) 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US6344413B1 (en) * 1997-12-22 2002-02-05 Motorola Inc. Method for forming a semiconductor device
US6198168B1 (en) 1998-01-20 2001-03-06 Micron Technologies, Inc. Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same
US5985759A (en) * 1998-02-24 1999-11-16 Applied Materials, Inc. Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers
US6122187A (en) 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US6404061B1 (en) * 1999-02-26 2002-06-11 Rohm Co., Ltd. Semiconductor device and semiconductor chip
US6452117B2 (en) * 1999-08-26 2002-09-17 International Business Machines Corporation Method for filling high aspect ratio via holes in electronic substrates and the resulting holes
US6610151B1 (en) * 1999-10-02 2003-08-26 Uri Cohen Seed layers for interconnects and methods and apparatus for their fabrication
US6565730B2 (en) 1999-12-29 2003-05-20 Intel Corporation Self-aligned coaxial via capacitors
US6368954B1 (en) * 2000-07-28 2002-04-09 Advanced Micro Devices, Inc. Method of copper interconnect formation using atomic layer copper deposition
US6737740B2 (en) * 2001-02-08 2004-05-18 Micron Technology, Inc. High performance silicon contact for flip chip

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646778A (zh) * 2006-12-21 2012-08-22 Lg电子株式会社 发光器件包及其制造方法
CN102376689A (zh) * 2011-09-09 2012-03-14 华中科技大学 具有台阶的硅通孔结构及其制备工艺
CN103367285A (zh) * 2013-07-26 2013-10-23 中国科学院微电子研究所 一种通孔结构及其制作方法
CN103367285B (zh) * 2013-07-26 2015-10-14 华进半导体封装先导技术研发中心有限公司 一种通孔结构及其制作方法
CN107706173A (zh) * 2017-09-30 2018-02-16 成都嘉纳海威科技有限责任公司 硅通孔互联结构及其制备方法以及硅通孔射频传输结构

Also Published As

Publication number Publication date
US20020105087A1 (en) 2002-08-08
WO2002063686A2 (en) 2002-08-15
US20020175423A1 (en) 2002-11-28
US6737740B2 (en) 2004-05-18
KR100552551B1 (ko) 2006-02-14
US6828656B2 (en) 2004-12-07
WO2002063686A3 (en) 2003-02-20
JP4295509B2 (ja) 2009-07-15
US6812137B2 (en) 2004-11-02
US20030207566A1 (en) 2003-11-06
AU2002243735A1 (en) 2002-08-19
JP2004527903A (ja) 2004-09-09
EP1360723A2 (en) 2003-11-12
KR20030079987A (ko) 2003-10-10

Similar Documents

Publication Publication Date Title
CN1528018A (zh) 倒装芯片的高性能硅接触
US7626257B2 (en) Semiconductor devices and methods of manufacture thereof
US5275973A (en) Method for forming metallization in an integrated circuit
US20020081838A1 (en) Interposer and method of making same
US20020167057A1 (en) Integrated decoupling capacitors
CN105870102A (zh) 镶嵌结构的结构和形成方法
US7544605B2 (en) Method of making a contact on a backside of a die
KR100378771B1 (ko) 공기 유전체 형성용 반-희생 다이어몬드
US11043469B1 (en) Method of forming three dimensional semiconductor structure
KR100421824B1 (ko) 반도체 장치의 제조방법
US20030008493A1 (en) Interconnect structure manufacturing
US9269586B2 (en) Selective metal deposition over dielectric layers
US6277705B1 (en) Method for fabricating an air-gap with a hard mask
EP3082161B1 (en) Method of forming inter-level dielectric structures on semiconductor devices
KR100282232B1 (ko) 반도체장치의 배선 형성방법
CN101330041A (zh) 金属前介质层内连接孔及其形成方法
US11631585B2 (en) Etching mask, method for fabricating the same, and method for fabricating a semiconductor structure using the same
CN115172325B (zh) 半导体结构及其形成方法、堆叠结构
US20230016977A1 (en) Self-aligning spacer tight pitch via
US20230187510A1 (en) Angled via for tip to tip margin improvement
US6284645B1 (en) Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process
WO1999013505A1 (en) In-situ deposition of stop layer and dielectric layer during formation of local interconnects
CN117558706A (zh) 一种半导体器件及其制作方法
CN117038639A (zh) 用于转接板的基底结构以及转接板的制造方法
WO2024010694A1 (en) Vias including an unsymmetric tapered through-hole, devices including the vias, and methods for fabricating the vias

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication