CN1529343A - Gold-tin-eutectic-based silicon/silicon bonding method - Google Patents
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- CN1529343A CN1529343A CNA200310111228XA CN200310111228A CN1529343A CN 1529343 A CN1529343 A CN 1529343A CN A200310111228X A CNA200310111228X A CN A200310111228XA CN 200310111228 A CN200310111228 A CN 200310111228A CN 1529343 A CN1529343 A CN 1529343A
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Abstract
Structure of films in multiple layer of Au/Sn is adopted in the method. Au/Sn eutectic linkage is realized through warming and pressing mode on electric hot plate. Since gold film is coated on stannum layer (stannum and gold coating is completed once in vacuum), in short time of hot linkage procedure, adding inert gases in hot plate area reduces oxidation of stannum layer. A fire resistant flexible underlayer in linkage substrate can prevent fragmentation of linkage piece effectively induced by uneven local stress or too large pressure caused from uneven thickness of silicon chip. Adjusting thickness of Au, Sn films complete Au/Sn eutectic linkage between silicon chips with larger areas. Comparing with prior art, the invention overcomes issues: linkage quality influenced by oxidable surface of stannum, and feasible linkage only for small area. The invention possesses features of fast speed and low cost, and without need of vacuum condition to carry out encapsulation.
Description
Technical field
The field is MEMS (micro electro mechanical system) (MEMS) and integrated circuit (IC) encapsulation technology under the present invention, is specifically related to a kind of silicon based on Sn/Au eutectic/silicon bonding method.
Prior art
MEMS (micro electro mechanical system) (MEMS) is the product that microelectronics and micro mechanics merge mutually, it combines silicon Micrometer-Nanometer Processing Technology in integrated circuit (IC) manufacturing process and the micromachining technology in the mechanical industry, produces the new unit of mechanical, electrical one even light, mechanical, electrical one.Through ten years development, the MEMS chip is quite ripe, but a lot of chip does not but obtain practical application as product, and its main cause is not solve the encapsulation problem.In fact have only the MEMS device that has encapsulated just can become product, just can come into operation, otherwise can only rest on laboratory stage.Present MEMS encapsulation technology is mostly by development of integrated circuit encapsulation technology and differentiation, but the MEMS encapsulation is different from the traditional IC encapsulation fully.The purpose of traditional IC encapsulation provides the physical support of IC chip, protects its interference that is not subjected to environment and destruction, realizes the electric interconnection with extraneous signal, the energy and ground connection simultaneously.MEMS device or system should the perception external world, simultaneously make movement response according to sensing results again to the external world, because that the reciprocation of this and external environment condition relation and the labyrinth of self make is interconnected except the multilayer that high-density packages faced to the encapsulation of MEMS, the heat dissipation problem, integrity problem, testability problem, also will consider MEMS chip, encapsulation and operational environment are designed as an interactive system encapsulation of MEMS.Therefore, the MEMS packaging cost is very high, generally accounts for about 70% of whole M EMS device cost.
Bonding is an important technology in MEMS and the IC technology.In existing packaging technology, for example fusion and anode linkage all are faced with the temperature height, and the time is long, and flatness requires high and may be to problems such as circuit cause damage.For example: silicon/Si direct bonding requires the bonding temperature of two plane bottom plates above 1000 ℃.The silicon/glass anode linkage will be succeedd and then be required surface roughness＜1 μ m.On the other hand, although the solder reflow of scolder solder technology under cryogenic conditions is possible, and the application facet in MEMS encapsulation also is feasible, yet the scaling powder of usefulness brings a series of pollution problems for level Hermetic Package in order to improve moistureproof ability in scolder in the past.In order to improve current bonding technology, new solder technology must be towards low temperature, and is low-cost and not too responsive these aspects of surface roughness are improved.
The chip bonding material of extensive use at present has four kinds: alloy hard solder, alloy slicken solder, glass solder and organic scolder.Because organic scolder is cheap and functional, thereby occupy an leading position in application facet.But, thereby still be extensive use of solder than higher occasion at reliability requirement because organic scolder is in the obvious deficiency of aspects such as mechanics, conduction, heat conduction, air-tightness.Alloy hard solder and slicken solder have pluses and minuses separately.Though slicken solder can be used for the welding of large chip, because welding process needs scaling powder, and serviceability temperature is low, seldom is used for the MEMS bonding.Hard solder bonding temperature height, speed is fast, does not generally need scaling powder, and layer intensity is high and can tolerate higher serviceability temperature, but because the residual thermal stress in the layer is big, easily causes chip cracks, so only be applicable to that generally chip size is less than 1 * 1mm
2, and the bonding under the thermal coefficient of expansion of chip and the substrate situation about being more or less the same.The most frequently used hard solder is Au/Si and Au/Sn eutectic solder.The Au/Si bonding usually with chromium or titanium as the intermediate layer, sputter between silicon (silica) matrix and the golden film, to obtain adhesive property good between gold and the silicon.The Au/Si bonding be a kind of annealed after, produce the bonding of Au/Si eutectic reaction between the silicon chip, have eutectic silicide bonding to form mutually between the bonding face.Because the pollution of bonding face and the realization that oxidation will have a strong impact on bonding, so the Au/Si bonding needs to carry out in vacuum or inert gas environment, cost is higher.
The Au/Sn eutectic bonding is because fusing point lower (Au/20Sn, expression contains the tin of 20% weight in the alloy, its eutectic temperature is 280 ℃), and the bond strength height is used more in microelectronics Packaging.Document 1 ([1] Ricky W.Chuang, Dongwook Kim, Jeony Park, et.al, A fluxlessAu-Sn bonding process of tin-rich compositions achieved in ambientair, 2002 Electronic components and technology conference.pp134-137) introduced a kind of Au/Sn eutectic soldering method that adopts multi-layer film structure, two kinds of alloy proportions, owing to carry out this bonding in tube furnace, pressure control during intensification and measurement be difficulty relatively; Because easily oxidation in air of metallic tin, document 2,3 ([2] Goran S.Matuasevic, Chen Y.Wang, Chin C.Lee, Void free bonding of large silicon dice using gold-tinalloys, IEEE transactions on components, hybrids and manufacturingtechnology.pp 1128-1134, Vol.13, No.4, Dec.1990) [3] MasanoriNishiguchi, Noboru Goto and Hideaki Nishizawa, Highly reliable Au-Sneutectic bonding with background GaAs LSI chips, IEEE transactionson components, hybrids and manufacturing technology.pp 1128-1134, Vol.14, No.3, Sept.1991) the Au/Sn weld tabs of employing eutectic composition is respectively at filling N
2Annealing furnace and blow H
2The bonding machine in realized Au/Sn eutectic weldering, remove surface oxide layer by manual wiping examination method (scrubbingaction), the bonding quality height brings inconvenience that (solder sheet thickness is 20-50um but aim at for the bonding that figure is arranged, be difficult to operation), and cost is higher; Document 4 (is seen [4] ViorelAvramescu, klas Hjort.Epitaxial layer transfer using thin film Snsoldering, suitable for hybrid integration in a coplanartechnology[J] .IEEE transactions on components, hybrids andmanufacturing technology.p 395-398, Vol.24, No.3, Sept.2001) adopting thickness is that the metallic tin layer of 0.9um has been realized InP and Si bonding on electric hot plate, because the tin layer is thinner, bonding area only is 1mm
2
The isothermal solidification process is the phase counterdiffusion of liquid/solid, the process of reaction.In this course, the diffusion that reacts under than the slightly high temperature of the fusing point of low melting point element of a kind of low melting point element and a kind of high-melting-point element finally can form fusing point intermetallic compound or the solid solution higher than diffusion temperature.Because the appearance of liquid phase in the course of reaction, this process is more faster than general solid-state diffusion.Document 5 (is seen [5] Wang Tiebing, Shi Jianzhong thanks to bright .Au/In isothermal solidification chips welding technical study [J] dawn. functional material and device journal, Vol.5, No.4,1999.12) introduced on silicon substrate and ferroalloy substrate Au/In bonding based on the isothermal solidification principle.
Summary of the invention
The objective of the invention is to propose a kind of silicon based on Sn/Au eutectic/silicon bonding method, this method has overcome two hang-ups that above-mentioned Au/Sn eutectic bonding exists: the easy oxidation affects bonding quality of tin surfaces and can only realize the small size bonding.
A kind of silicon based on Sn/Au eutectic provided by the invention/silicon bonding method may further comprise the steps successively:
(1) cleans the silicon chip surface for the treatment of bonding;
(2) silicon cap layer preparation:, plate the thick Cr film of 10-20nm on the surface, bonding place for the treatment of of cap layer, then evaporation or the thick Au film of plating 3-10um by sputtering method;
(3) silicon substrate preparation: by sputtering method, plate thick Cr film of 10-20nm and the thick Au film of 200-500nm successively, plate Sn film and the thick Au film of 100-200nm of 2-8um then by evaporation or galvanoplastic on the surface, bonding place for the treatment of of substrate;
(4) the plated film face of silicon substrate and silicon cap layer is relative and be placed on the electric hot plate that is used for bonding, the electric hot plate energising is warming up to 320-350 ℃, and apply the pressure of 0.2-1.0MPa, be 3-5 minute pressing time, remove pressure then, the bonding silicon chip continues to be retained on the electric hot plate until the AuSn sufficient reacting, can obtain the Sn/Au eutectic bonding pad after the cooling; In bonding process, feed inert gas, to prevent the Sn oxidation to the electric hot plate district.
The present invention utilizes the isothermal solidification process of metallic tin and Sn/Au eutectic weldering principle to carry out silicon/silicon bonding.It adopts the multi-layer film structure of Au/Sn, has realized the Au/Sn eutectic bonding by the pressing mode of heating on electric hot plate.Because the tin laminar surface is coated with certain thickness golden film (zinc-plated, gold-plated film is once finished in a vacuum), in short time heating bonding process,, reduced the oxidation of tin layer by logical inert gas in the hot plate district.By adjusting Au, Sn thicknesses of layers, finished the Au/Sn eutectic bonding between the larger area silicon chip.The present invention has overcome in the prior art the easy oxidation affects bonding quality of tin surfaces and can only realize the problem of small size bonding, and need not encapsulate under vacuum condition, has advantages such as bonding speed is fast, production cost is low.
Description of drawings
Fig. 1-1 is silicon cap layer membrane structure figure, and 1-2 is silicon substrate film layer structure figure;
Fig. 2 is cap laminar surface ESEM (SEM) photo (10000 *);
Fig. 3 is substrate ESEM (SEM) photo (10000 *);
Fig. 4 cuts ESEM (SEM) photo (5000 *) on back substrate surface open for example 1 bonding face;
Fig. 5 cuts back substrate surface microphoto (400 *) open for example 2 bonding faces.
Embodiment
Example 1:
1) cleaning silicon chip: P type＜100 of single-sided polishing〉silicon wafer adopts the silicon chip cleaning liquid heating of the concentrated sulfuric acid and hydrogen peroxide (volume ratio is 4: 1) configuration to boil 10min, use acetone ultrasonic cleaning 10min again, use absolute ethyl alcohol ultrasonic cleaning 10min then, use the ultrasonic 10min of deionized water (DI) again, use the DI rinsing clean at last, drying on the sol evenning machine and heating on hot plate and dry, hot plate temperature is 120 ℃, time 10min;
2) cap layer preparation: at the thick Cr film 2 of silicon garden sheet 3 surface plating 10nm, evaporate the thick Au film 1 of 3um then by sputtering method.Cap tunic structure as Figure 1-1, microstructure is as shown in Figure 2;
3) substrate preparation: plate thick Cr film 7 of 20nm and the thick Au film 6 of 200nm successively on sheet 8 surfaces, silicon garden by sputtering method, plate Sn film 5 and the thick Au film 4 of 200nm of 2um then by evaporation.Substrat structure is shown in Fig. 1-2, and microstructure as shown in Figure 3;
4) silicon wafer that plated film is finished cuts into the scribing of 1cm * 1cm size;
5) will place the electric hot plate energising on the base plate to be warming up to 330 ± 10 ℃, the substrate and the cap layer of (the plated film face is relative) of will matching then is placed on the electric hot plate together, apply the pressure (pressure passes through determination of pressure sensor) of 1.0MPa by regulating spring, inhomogeneous for preventing the local pressure that is caused because of the silicon wafer thickness inequality, or the excessive bonding pad that causes of pressure is cracked, at bonded substrate sheet underlay last layer thickness is the polytetrafluoroethylraw raw material band of 0.1mm, be 3min pressing time, remove pressure then, bonding pad continues to be retained in certain hour on the electric hot plate so that the AuSn sufficient reacting can obtain complete Sn/Au eutectic sheet after the cooling.Lead to N to the electric hot plate district in the bonding process
2To prevent the Sn oxidation, gas flow is 1-2l/min.
This step can adopt eutectic chip mounter or other bonding apparatus to finish.
According to the method and the step of above-mentioned introduction, the actual silicon of finishing the big chip of 1cm * 1cm/silicon bonding, after testing, bonding area reaches more than 90%, and the shear strength of bonding face reaches 3.5MPa.Stereoscan photograph after bonding face is cut open (SEM) as shown in Figure 4.
Example 2:
Carry out according to example 1 technology, the adjustment content is: adopt galvanoplastic to obtain Au film 1 in the preparation of cap layer, thickness is 7um, sputter Au film 6 thickness are 500nm in the substrate preparation, and electroplating Sn film 5 thickness is 5um, and electric plate temperature is 340 ± 10 ℃ during bonding, exert pressure and be 0.5MPa, be 5min pressing time, and the shear strength of resulting bonding face is 3.7MPa, and other parameter such as figure example 1 are identical.Micrograph after bonding face breaks as shown in Figure 5.
Example 3:
Carry out according to example 1 technology, the adjustment content is: adopt galvanoplastic to obtain Au film 1 in the preparation of cap layer, thickness is 10um, sputter Au film 6 thickness are 500nm in the substrate preparation, electroplating Sn film 5 thickness is 8um, and electric plate temperature is 340 ± 10 ℃ during bonding, exerts pressure to be 0.2MPa, be 5min pressing time, and the shear strength of resulting bonding face is 4.0MPa.Other parameter such as figure example 1 are identical.
Among the present invention, the Au layer thickness sum on silicon cap layer and the silicon substrate is about at 3: 2 o'clock with the ratio of Sn layer thickness, and its technique effect is better.
Claims (3)
1, a kind of silicon based on Sn/Au eutectic/silicon bonding method may further comprise the steps successively:
(1) cleans the silicon chip surface for the treatment of bonding;
(2) silicon cap layer preparation:, plate the thick Cr film of 10-20nm on the surface, bonding place for the treatment of of cap layer, then evaporation or the thick Au film of plating 3-10um by sputtering method;
(3) silicon substrate preparation: by sputtering method, plate thick Cr film of 10-20nm and the thick Au film of 200-500nm successively, plate Sn film and the thick Au film of 100-200nm of 2-8um then by evaporation or galvanoplastic on the surface, bonding place for the treatment of of substrate;
(4) the plated film face of silicon substrate and silicon cap layer is relative and be placed on the electric hot plate that is used for bonding, the electric hot plate energising is warming up to 320-350 ℃, and apply the pressure of 0.2-1.0MPa, be 3-5 minute pressing time, remove pressure then, the bonding silicon chip continues to be retained on the electric hot plate until the AuSn sufficient reacting, can obtain the Sn/Au eutectic bonding pad after the cooling; In bonding process, feed inert gas, to prevent the Sn oxidation to the electric hot plate district.
2, method according to claim 1 is characterized in that: in the step (4), at silicon substrate underlay one deck high-temperature flexible thin layer.
3, method according to claim 1 and 2 is characterized in that: in step (2) and (3), the thickness ratio of the Au/Sn film in the coating process in control silicon substrate and the silicon cap layer is about 3: 2.
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| CN101819076A (en) * | 2010-04-21 | 2010-09-01 | 中国电子科技集团公司第二十四研究所 | Sn/Au eutectic based chip partial vacuum packaging method of resonance type pressure sensor |
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| CN101601123B (en) * | 2007-02-16 | 2010-12-22 | 硅绝缘体技术有限公司 | Method of bonding two substrates |
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