CN1533603A - 半导体装置及其制造方法、电路基板以及电子仪器 - Google Patents

半导体装置及其制造方法、电路基板以及电子仪器 Download PDF

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CN1533603A
CN1533603A CNA038007061A CN03800706A CN1533603A CN 1533603 A CN1533603 A CN 1533603A CN A038007061 A CNA038007061 A CN A038007061A CN 03800706 A CN03800706 A CN 03800706A CN 1533603 A CN1533603 A CN 1533603A
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semiconductor device
manufacture method
semiconductor substrate
groove
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CN1279604C (zh
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宫泽郁也
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

在半导体基板(10)上从第一面(20)形成凹部(22)。在凹部(22)的底面以及内壁面上设置绝缘层(28)。在绝缘层(28)的内侧设置导电部(30)。通过具有对半导体基板(10)的蚀刻量大于对绝缘层(28)的蚀刻量的性质的第一蚀刻剂，对半导体基板(10)的第二面(28)进行蚀刻，在由绝缘层(28)覆盖的状态下使导电部(30)突出。通过具有在导电部(30)上不留有残留物地对绝缘层(28)进行蚀刻的性质的第二蚀刻剂，对绝缘层(28)上至少形成在凹部(22)的底面上的部分进行蚀刻，使导电部(30)突出。

Description

半导体装置及其制造方法、电路基板以及电子仪器
技术领域
本发明涉及一种半导体装置及其制造方法、电路基板以及电子仪器。
背景技术
三维的安装形态的半导体装置正在开发。而且，为了能够进行三维的安装，公知的是在半导体芯片上形成贯通电极。贯通电极从半导体芯片上突出地形成。在这种公知的贯通电极的形成方法中，通过对由贯通电极周围的Si构成的部分进行蚀刻，使贯通电极突出。在这种情况下，要使贯通电极的突出部分不被蚀刻屑污染很困难。
发明内容
本发明是为了解决上述问题而提出的，其目的在于形成高品质的贯通电极。
(1)本发明的半导体装置的制造方法包括下述工序：
(a)在形成了集成电路的半导体基板上从第一面形成凹部，
(b)在上述凹部的底面以及内壁面上设置绝缘层，
(c)在上述绝缘层的内侧设置导电部，
(d)通过具有对上述半导体基板的蚀刻量大于对上述绝缘层的蚀刻量的性质的第一蚀刻剂，对上述半导体基板上与上述第一面相反一侧的第二面进行蚀刻，在由上述绝缘层覆盖的状态下使上述导电部突出，
(e)通过具有在上述导电部上不形成残留物地至少对上述绝缘层进行蚀刻的性质的第二蚀刻剂，对上述绝缘层上至少形成于上述凹部的上述底面上的部分进行蚀刻，使上述导电部露出。
根据本发明，可以在(d)工序中使导电部突出，在(e)工序中使导电部露出。这样一来，通过导电部，可形成从半导体基板上突出的贯通电极。而且，在(e)工序中，由于当使导电部从绝缘层上露出时，在导电部上不留有残留物，所以可形成高品质的贯通电极。
(2)在这种半导体装置的制造方法中，上述第一蚀刻剂可以是SF6或CF4或Cl2气体。
(3)在这种半导体装置的制造方法中，可以使用干式蚀刻装置进行上述(d)工序。
(4)在这种半导体装置的制造方法中，上述第一蚀刻剂可以是氟酸以及硝酸的混合液，或者氟酸、硝酸、以及醋酸的混合液。
(5)在这种半导体装置的制造方法中，上述第二蚀刻剂可以是Ar、CF4的混合气体，或者O2、CF4的混合气体。
(6)在这种半导体装置的制造方法中，可以使用干式蚀刻装置进行上述(e)工序。
(7)在这种半导体装置的制造方法中，上述第二蚀刻剂可以是氟酸或氟酸和氟化铵的混合液。
(8)在这种半导体装置的制造方法中，可以由SiO2或SiN形成上述绝缘层。
(9)在这种半导体装置的制造方法中，可以在上述(e)工序中也对上述导电部的外层部进行蚀刻。
(10)在这种半导体装置的制造方法中，上述导电部的上述外层部可以由与中心部不同的材料形成。
(11)在这种半导体装置的制造方法中，可以由Cu、W、掺杂多晶硅中任一种形成上述导电部的上述中心部。
(12)在这种半导体装置的制造方法中，可以由TiW、TiN或TaN形成上述导电部的上述外层部的至少一部分。
(13)在这种半导体装置的制造方法中，还可以包括在上述(d)工序之前将上述半导体基板的上述第二面研磨到上述绝缘层之前的工序。
(14)在这种半导体装置的制造方法中，可以是上述(e)工序的蚀刻与上述(d)工序的蚀刻相比，对上述半导体基板的蚀刻速度慢。
(15)在这种半导体装置的制造方法中，可以是上述半导体基板是半导体晶片，形成多个上述集成电路，与各上述的集成电路相对应地形成上述凹部，并且还包括切断上述半导体基板的工序。
(16)在这种半导体装置的制造方法中，上述切断半导体基板的工序可以包括在上述第一面上形成沿着上述半导体基板的切断线的槽，以及从上述第二面上除去上述槽的底部而使上述槽成为狭缝。
(17)在这种半导体装置的制造方法中，可以通过切削形成上述槽。
(18)在这种半导体装置的制造方法中，可以通过蚀刻形成上述槽。
(19)在这种半导体装置的制造方法中，在上述(a)工序中，可以由与上述凹部相同的工艺形成上述槽。
(20)在这种半导体装置的制造方法中，可以还包括在上述(d)工序之前将上述半导体基板的上述第二面研磨到上述绝缘层之前的工序，比上述凹部深地形成上述槽，通过上述半导体基板的上述第二面的研磨，除去上述槽的底部。
(21)在这种半导体装置的制造方法中，可以在上述(b)工序中，在上述槽内也设置上述绝缘层。
(22)在这种半导体装置的制造方法中，可以在上述(d)中，使在上述槽的底部上形成的上述绝缘层从上述第二面突出，在上述(e)工序中，通过上述第二蚀刻剂，将形成在上述槽的底部上的上述绝缘层蚀刻除去。
(23)在这种半导体装置的制造方法中，可以在上述半导体基板的材料露出在上述槽内的状态下进行上述除去槽的底部的工序。
(24)在这种半导体装置的制造方法中，可以在上述(d)工序中，通过上述第一蚀刻剂，将由上述半导体基板的一部分构成的上述槽的底部蚀刻除去。
(25)在这种半导体装置的制造方法中，可以为了被切断的多个半导体芯片不脱落，将上述半导体基板的上述第一面贴在保持板上进行上述切断半导体基板的工序。
(26)在这种半导体装置的制造方法中，可以是上述槽仅在划分具有上述多个集成电路的多个半导体芯片的区域形成。
(27)本发明的半导体装置的制造方法包括将由上述方法制造的多个半导体装置叠层，通过上述导电部实现电连接。
(28)本发明的半导体装置由上述的方法制造而成。
(29)本发明的电路基板由安装上述半导体装置而成。
(30)本发明的电子仪器具有上述半导体装置。
附图说明
图1A～图1D为说明适用本发明的第一实施方式的半导体装置的制造方法的附图。
图2A～图2D为说明适用本发明的第一实施方式的半导体装置的制造方法的附图。
图3A～图3D为说明适用本发明的第一实施方式的半导体装置的制造方法的附图。
图4为说明适用本发明的第一实施方式的半导体装置的制造方法的附图。
图5为说明适用本发明的第一实施方式的半导体装置的制造方法的附图。
图6为表示本发明第一实施方式的电路基板的附图。
图7为表示本发明第一实施方式的电子仪器的附图。
图8为表示本发明第一实施方式的电子仪器的附图。
图9A～图9C为说明适用本发明的第二实施方式的半导体装置的制造方法的附图。
图10A～图10B为说明适用本发明的第三实施方式的半导体装置的制造方法的附图。
图11A～图11B为说明适用本发明的第四实施方式的半导体装置的制造方法的附图。
图12为说明适用本发明的第五实施方式的半导体装置的制造方法的附图。
图13为说明适用本发明的第六实施方式的半导体装置的制造方法的附图。
具体实施方式
以下，参照附图对本发明的实施方式加以说明。
(第一实施方式)
图1A～图3C为说明适用本发明的第一实施方式的半导体装置的制造方法的附图。在本实施方式中使用半导体基板10。图1A所示的半导体基板10也可以是作为半导体晶片的半导体芯片。在半导体基板10上至少形成一个(半导体晶片上为多个，半导体芯片上为一个)集成电路(例如具有晶体管或储存器的电路)12。在半导体基板10上形成有多个电极(例如发射极)14。各电极14电连接在集成电路12上。各电极14也可以由氧化铝形成。虽然对电极14的表面形状没有特别的限制，但多为矩形。在半导体基板10为半导体晶片的情况下，在多个成为半导体芯片的各区域上形成两个以上(一组)的电极14。
在半导体基板10上形成有一层或者一层以上的钝化膜16、18。钝化膜16、18例如可由SiO2、SiN、聚酰胺树脂等形成。在图1A所示的例子中，在钝化膜16上形成有电极14、集成电路12、和连接电极的配线(未图示)。而且，其他的钝化膜18是避开电极14的表面上至少一部分地形成的。钝化膜18也可以在覆盖电极14的表面形成后对其一部分进行蚀刻，使电极14的一部分露出。在蚀刻中可以采用干式蚀刻和湿式蚀刻的任一种。在钝化膜18的蚀刻时，也可以将电极14的表面蚀刻。
在本实施方式中，在半导体基板10上，从其第一面20形成凹部22(参照图1C)。第一面20为形成有电极14一侧的面，凹部22避开集成电路12的元件和配线地形成。如图1B所示，也可以在电极14上形成贯通孔24。在贯通孔24的形成上也可以适用蚀刻(干式蚀刻或湿式蚀刻)。蚀刻可以在通过平板印刷工序而形成图形化了的保护膜(未图示)之后进行。在电极14之下形成有钝化膜16的情况下，在其上也可以形成贯通孔26(参照图1C)。在电极14的蚀刻止于钝化膜16的情况下，在贯通孔26的形成上也可以将电极14的蚀刻中使用的蚀刻剂更换成其他的蚀刻剂。在这种情况下，也可以再次通过平板印刷工序形成图形化的保护膜(未图示)。
如图1C所示，为了与贯通孔24(以及贯通孔26)连通，在半导体基板10上形成凹部22。也可以将贯通孔24(以及贯通孔26)和凹部22合起来称为凹部。在凹部22的形成上也可以适用蚀刻(干式蚀刻或湿式蚀刻)。蚀刻也可以在通过平板印刷工序形成了图形化的保护膜(未图示)之后进行。或者，在凹部22的形成上使用激光(例如CO2激光器、YAG激光器等)。激光也适用于贯通孔24、26的形成。也可以通过一种蚀刻剂或者激光连续地进行凹部22以及贯通孔24、26的形成。
如图1D所示，在凹部22的内侧上形成绝缘层28。绝缘层28也可以是氧化膜。例如，在半导体基板10的基材为Si的情况下，绝缘层28既可以是SiO2、也可以是SiN。绝缘层28形成在凹部22的底面上。绝缘层28形成在凹部22的内壁面上。但是，绝缘层28是不埋入凹部22地形成的。即，由绝缘层28形成凹部。绝缘层28既可以形成在钝化膜16的贯通孔26的内壁面上。绝缘层28也可以形成在钝化膜18上。
绝缘层28也可以形成在电极14的贯通孔24的内壁面上。绝缘层28避开电极14的一部分(例如其上表面)地形成。还可以覆盖电极14的全部表面地形成绝缘层28，对其一部分进行蚀刻(干式蚀刻或湿式蚀刻)，使电极14的一部分露出。蚀刻也可以在通过平板印刷工序形成了图形化的保护膜(未图示)之后进行。
然后，在绝缘层28的内侧上设置导电部30(参照图2B)。导电部30可以由Cu或W等形成。可以在如图2A所示形成了导电部30的外层部32后形成其中心部34。中心部34可由Cu、W、掺杂多晶硅(例如低温多晶硅)中的任一种形成。外层部32也可以至少含有阻挡层。阻挡层用于防止中心部34或者后述的晶种层的材料扩散到半导体基板10(例如Si)中。阻挡层也可以由与中心部34不同的材料(例如TiW、TiN、TaN)形成。在通过电镀形成中心部34的情况下，外层部32也可以含有晶种层。晶种层在形成了阻挡层之后形成。晶种层由与中心部34相同的材料(例如铜)形成。另外，导电部30(至少其中心部34)也可以通过非电镀或喷溅方式形成。
如图2B所示，在钝化膜18上也形成了外层部32的情况下，则如图2C所示，对外层部32的钝化膜18上的部分进行蚀刻。在形成了外层部32后，可通过形成中心部34而形成导电部30。导电部30的一部分位于半导体基板10的凹部22内。由于在凹部22的内壁面和导电部30之间存在绝缘层28，所以两者的电连接被隔断。导电部30与电极14电连接。例如，导电部30与电极14从绝缘层28露出的露出部接触也可以。导电部30的一部分也可以位于钝化膜18上。导电部30也可以仅设置在电极14的区域内。导电部30也可以至少在凹部22的上方突出。例如，导电部30可以比钝化膜18更突出。
另外，作为变形例，也可以在外层部32残留在钝化膜18上的状态下形成中心部34。在这种情况下，由于与中心部34连续的层也形成在钝化膜18的上方，所以该层进行蚀刻。
如图2D所示，也可以在导电部30上设置钎料焊料层36。钎料焊料层36例如由焊锡形成，可由软钎料焊料及硬钎料焊料中的任一种形成。钎料焊料层36可以由保护膜覆盖导电部30之外的区域地形成。通过以上的工序，能够由导电部30或者在其上添加钎料焊料层30而形成突起。
在本实施方式中，如图3A所示，可通过例如机械研磨、磨削以及化学研磨、磨削的至少一种方法对半导体基板10的第二面(与第一面相反一侧的面)38进行切削。该工序在凹部22上形成的绝缘层28露出之前进行。另外，也可以省略图3A中所示的工序，进行以下图3B所示的工序。
如图3B所示，将半导体基板10的第二面38蚀刻到使绝缘层28露出。而且，将半导体基板10的第二面38蚀刻到导电部30(详细地说是凹部22内的部分)在由绝缘层28覆盖的状态下突出。蚀刻通过具有相对于半导体基板(例如以Si作为基材)10的蚀刻量比相对于绝缘层(例如由SiO2形成)28的蚀刻量大的性质的第一蚀刻剂进行。第一蚀刻剂也可以是SF6或CF4或Cl2气体。蚀刻也可以采用干式蚀刻装置进行。或者第一蚀刻剂也可以是氟酸及硝酸的混合液或者氟酸、硝酸、以及醋酸的混合液。
如图3C所示，对绝缘层28上至少形成在凹部22底面上的部分进行蚀刻。而且使导电部30露出。也可以是导电部30的前端面露出，导电部30的前端部外周面由绝缘层28覆盖。导电部30的外层部32(例如阻挡层)也可以进行蚀刻。蚀刻通过具有不会在导电部30上形成残留物、至少对绝缘层28进行蚀刻的性质的第二蚀刻剂进行。第二蚀刻剂也可以使用不与导电部30的材料(例如Cu)反应(或者反应很小)的材料。第二蚀刻剂也可以是Ar、CF4的混合气体或者O2、CF4的混合气体。蚀刻也可以使用干式蚀刻装置进行。或者，第二蚀刻剂也可以是氟酸液体或氟酸和氟化铵的混合液。第二蚀刻剂进行的蚀刻可以是与第一蚀刻剂进行的蚀刻相比，对半导体基板10的蚀刻速度慢。
另外，图3A～图3C中的至少一个工序可以是在半导体基板10的第一面20一侧上设置了例如由树脂层或树脂带构成的加强材料后进行。
通过以上的工序，可使导电部30从半导体基板10的第二面38突出。突出的导电部30成为突起电极。导电部30也成为第一以及第二面20、38的贯通电极。根据本实施方式，在使导电部30从绝缘层28露出时，由于在导电部30上不留有残留物，所以可形成高品质的贯通电极。
如图4所示，在半导体基板10为半导体晶片的情况下，也可以与各集成电路12(参照图1A)对应地形成凹部22，并将半导体基板10切断(例如切块)。在切断上可使用刀具(例如剪切机)40或激光(例如CO2激光器、YAG激光器等)。
通过以上的工序可制造半导体装置。而且，如图5所示，可将通过上述的方法制造的多个半导体装置叠层，通过导电部30分别实现电连接。本实施方式在进行这种三维安装时是有效的。图5中所示的半导体装置具有多个半导体基板10。位于第一面20的方向上最外侧(图5中最下侧)的半导体基板10具有外部端子(例如焊点)42。外部端子42设置在形成于树脂层(例如应力缓和层)44上的配线46上。配线46在第一面20一侧连接在导电部30上。
图6中示出安装了多个半导体芯片叠层而成的半导体装置1的电路基板1000。多个半导体芯片通过上述的导电部30而电连接。作为具有上述的半导体装置的电子仪器，图7中示出了笔记本型计算机2000，图8中示出了携带电话3000。
(第二实施方式)
图9A～图9C为说明适用本发明的第二实施方式的半导体装置的制造方法的附图。在本实施方式中，在半导体基板10(具体地说是第一面20)上形成槽100。槽100是沿着半导体基板10的切断线形成。槽100既可以通过切削形成，也可以通过蚀刻形成。槽100可以在图1C所示的形成凹部22的工序中通过与凹部22相同的工艺(例如同时)形成。可将绝缘层28设置在槽100内。槽100既可以是与凹部22大致相同的深度，也可以是比凹部22深，还可以是比凹部22浅。
之后，进行第一实施方式所说明的图3A～图3C的工序。图9A～图9C分别是表示进行图3A～图3C所示的工序时槽100附近的结构的附图。例如，进行图3A所示的工序，将半导体基板10的第二面38研磨到绝缘层28之前(参照图9A)。而且，进行图3B所示的工序，如图9B所示，使槽100的底部上形成的绝缘层28从第二面38突出。
而且，进行图3C所示的工序，如图9C所示，通过第二蚀刻剂将在槽100的底部上形成的绝缘层28蚀刻除去。这样一来，槽100的底部从第二面上除去，槽100成为狭缝102。即，半导体基板10沿着槽100被切断。
根据本实施方式，可简单地切断半导体基板10。而且，由于半导体基板10的最终切断可通过第二蚀刻剂进行，所以不易产生碎屑。另外，在本实施方式中，由于在槽100内形成绝缘层28，所以半导体芯片在侧面上具有绝缘层28。因此，这种半导体芯片不易产生边缘短路。其他的内容相当于第一实施方式所说明的内容。
(第三实施方式)
图10A～图10B为说明适用本发明的第三实施方式的半导体装置的制造方法的附图。在本实施方式中，如图10A所示，在半导体基板10的材料露出在槽100内的状态下进行槽100的底部除去工序。例如，既可以在进行了图1D所示的在凹部22内形成绝缘层28的工序之后形成槽100，也可以预先在槽100内设置抗蚀剂膜使绝缘层28不附着，还可以将进入槽100内的绝缘层28除去。除此之外的内容相当于第二实施方式所说明的内容。
在本实施方式中，进行第一实施方式所说明的图3B的工序，通过第一蚀刻剂，将由半导体基板10的一部分构成的槽100的底部蚀刻除去。这样一来，如图10B所示，槽100的底部从第二面上除去，槽100成为狭缝102。即，半导体基板100沿着槽100被切断。其他内容相当于第一和第二实施方式所说明的内容。
(第四实施方式)
图11A～图11B为说明适用本发明的第四实施方式的半导体装置的制造方法的附图。在本实施方式中，如图11A所示，比凹部22深地形成槽110。比凹部22深的槽110可利用蚀刻的性质(宽度越大越深地进行的性质)容易地形成。
然后，如图11B所示，通过半导体基板10的第二面38的研磨(参照利用图3A的说明)，除去槽110的底部。这样一来，槽110的底部从第二面上除去，槽110成为狭缝112。即，半导体基板100沿着槽110被切断。其他内容相当于第一、第二、以及第三实施方式所说明的内容。而且，在本实施方式中，虽然是在槽110内形成了绝缘层28的状态下切断半导体基板10的，但也可以在半导体基板10的材料露出在槽110内的状态下进行半导体基板10的切断。
(第五实施方式)
图12为说明适用本发明的第五实施方式的半导体装置的制造方法的附图。本实施方式的内容也可以适用于第二至第四实施方式中的任一种中。在本实施方式中，槽120仅形成在划分具有多个集成电路12(参照图1A)的多个半导体芯片的区域上。这样一来，半导体基板10的不要部分(例如外周端部)不会凌乱，可防止成为产品的半导体芯片的破损。
(第六实施方式)
图13为说明适用本发明的第六实施方式的半导体装置的制造方法的附图。在本实施方式中，切断半导体基板10的工序是将半导体基板10的第一面20贴在保持板130上进行的。保持板130可以是粘接带或粘接片。因此，即使切断半导体基板10，多个半导体芯片也不脱落。本实施方式的内容也可以适用于第一至第五实施方式中的任一种中。
本发明并不仅限于上述的实施方式，也可以进行各种变更。例如，本发明包括与实施方式所说明的结构实质上相同的结构(例如功能、方法、以及结果相同的结构，或者目的和结果相同的结构)。而且，本发明也包括将实施方式中说明的结构中非本质的部分替换的结构。而且，本发明还包括能够起到与实施方式所说明的结构相同的作用效果的结构，或者能够达到相同目的的结构。而且，本发明还包括在实施方式所说明的结构中加上公知技术的结构。

Claims (33)

1.一种半导体装置的制造方法，包括下述工序：
(a)在形成了集成电路的半导体基板上从第一面形成凹部，
(b)在上述凹部的底面以及内壁面上设置绝缘层，
(c)在上述绝缘层的内侧设置导电部，
(d)通过具有对上述半导体基板的蚀刻量大于对上述绝缘层的蚀刻量的性质的第一蚀刻剂，对上述半导体基板上与上述第一面相反一侧的第二面进行蚀刻，在由上述绝缘层覆盖的状态下使上述导电部突出，
(e)通过具有在上述导电部上不形成残留物地至少对上述绝缘层进行蚀刻的性质的第二蚀刻剂，对上述绝缘层上至少形成于上述凹部的上述底面上的部分进行蚀刻，使上述导电部露出。
2.如权利要求1所述的半导体装置的制造方法，上述第一蚀刻剂是SF6或CF4或Cl2气体。
3.如权利要求2所述的半导体装置的制造方法，使用干式蚀刻装置进行上述(d)工序。
4.如权利要求1所述的半导体装置的制造方法，上述第一蚀刻剂是氟酸以及硝酸的混合液，或者氟酸、硝酸、以及醋酸的混合液。
5.如权利要求1所述的半导体装置的制造方法，上述第二蚀刻剂是Ar、CF4的混合气体，或者O2、CF4的混合气体。
6.如权利要求5所述的半导体装置的制造方法，使用干式蚀刻装置进行上述(e)工序。
7.如权利要求1所述的半导体装置的制造方法，上述第二蚀刻剂是氟酸或氟酸和氟化铵的混合液。
8.如权利要求1所述的半导体装置的制造方法，由SiO2或SiN形成上述绝缘层。
9.如权利要求1所述的半导体装置的制造方法，在上述(e)工序中也对上述导电部的外层部进行蚀刻。
10.如权利要求9所述的半导体装置的制造方法，上述导电部的上述外层部由与中心部不同的材料形成。
11.如权利要求10所述的半导体装置的制造方法，由Cu、W、掺杂多晶硅中任一种形成上述导电部的上述中心部。
12.如权利要求10所述的半导体装置的制造方法，由TiW、TiN或TaN形成上述导电部的上述外层部的至少一部分。
13.如权利要求1所述的半导体装置的制造方法，还包括在上述(e)工序之前将上述半导体基板的上述第二面研磨到上述绝缘层之前的工序。
14.如权利要求1所述的半导体装置的制造方法，上述(e)工序的蚀刻与上述(d)工序的蚀刻相比，对上述半导体基板的蚀刻速度慢。
15.如权利要求1所述的半导体装置的制造方法，
上述半导体基板是半导体晶片，形成多个上述集成电路，与各上述的集成电路相对应地形成上述凹部，
并且还包括切断上述半导体基板的工序。
16.如权利要求15所述的半导体装置的制造方法，上述切断半导体基板的工序包括在上述第一面上形成沿着上述半导体基板的切断线的槽，以及从上述第二面上除去上述槽的底部而使上述槽成为狭缝。
17.如权利要求16所述的半导体装置的制造方法，通过切削形成上述槽。
18.如权利要求16所述的半导体装置的制造方法，通过蚀刻形成上述槽。
19.如权利要求16所述的半导体装置的制造方法，在上述(a)工序中，由与上述凹部相同的工艺形成上述槽。
20.如权利要求16所述的半导体装置的制造方法，
还包括在上述(d)工序之前将上述半导体基板的上述第二面研磨到上述绝缘层之前的工序，
比上述凹部深地形成上述槽，
通过上述半导体基板的上述第二面的研磨，除去上述槽的底部。
21.如权利要求16所述的半导体装置的制造方法，在上述(b)工序中，在上述槽内也设置上述绝缘层。
22.如权利要求21所述的半导体装置的制造方法，
在上述(d)工序中，使在上述槽的底部上形成的上述绝缘层从上述第二面突出，
在上述(e)工序中，通过上述第二蚀刻剂，将形成在上述槽的底部上的上述绝缘层蚀刻除去。
23.如权利要求16所述的半导体装置的制造方法，在上述半导体基板的材料露出在上述槽内的状态下进行上述除去槽的底部的工序。
24.如权利要求23所述的半导体装置的制造方法，在上述(d)工序中，通过上述第一蚀刻剂，将由上述半导体基板的一部分构成的上述槽的底部蚀刻除去。
25.如权利要求16所述的半导体装置的制造方法，为了被切断的多个半导体芯片不脱落，将上述半导体基板的上述第一面贴在保持板上进行上述切断半导体基板的工序。
26.如权利要求16所述的半导体装置的制造方法，上述槽仅在划分具有上述多个集成电路的多个半导体芯片的区域形成。
27.一种半导体装置的制造方法，将由权利要求1至权利要求26中的任一项所述的方法制造的多个半导体装置叠层，通过上述导电部实现电连接。
28.一种半导体装置，由权利要求1至权利要求26中任一项所述的方法制造而成。
29.一种半导体装置，由权利要求27所述方法的制造而成。
30.一种电路基板，由安装权利要求28所述的半导体装置而成。
31.一种电路基板，由安装权利要求29所述的半导体装置而成。
32.一种电子仪器，具有权利要求28所述的半导体装置。
33.一种电子仪器，具有权利要求29所述的半导体装置。
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