CN1538531A - 肖特基势垒晶体管及其制造方法 - Google Patents
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Abstract
本发明提供一种肖特基势垒晶体管及其制造方法。该方法包括在衬底上形成栅极绝缘层和栅极,在栅极侧壁上形成隔离壁,在栅极和衬底上使用选择性硅生长分别生长多晶硅层和单晶硅层。金属沉积在多晶硅层和单晶硅层上。然后,金属与多晶硅层和单晶硅层中的硅反应以形成自对准金属硅化物层。因此,在硅化后用来去除未反应的金属的选择性湿法刻蚀可被省略。此外,在单晶硅层的生长过程中,形成隔离壁所引起的刻蚀损伤可被减小,因此改进了器件的电特性。
Description
本申请要求2003年4月16日在韩国知识产权局提出的韩国专利申请第2003-23969号的优先权,这里引用它的全部公开内容作为参考。
技术领域
本发明涉及一种晶体管及其制造方法。更具体地,本发明涉及一种使用形成在金属和半导体之间的肖特基势垒(schottky barrier)的肖特基势垒晶体管(以下称为“SB”晶体管),及其制造方法。
背景技术
目前,半导体器件制造技术已经达到了能够制造出短沟道长度小于100nm的晶体管的水平。但是,仅仅通过减小晶体管的尺寸来实现集成化引发了许多问题。最重要的问题是由于器件的尺度缩小和与源极/漏极电阻减小相关的源极/漏极掺杂而造成的短沟道效应(SCE)。
特别是,通过离子注入形成源极/漏极的传统晶体管制造方法伴随着下列问题。首先,很难调节结的深度。由于杂质扩散发生于深度方向和沟道方向,所以短沟道效应很难防止。在这一点上,已经提出将快速热工艺(RTP)、激光退火、固相扩散(SPD)等等作为离子注入的替代工艺。但是,很难达到防止短沟道效应所要求的小于10nm的沟道深度。其次,饱和电流不可避免地减小。也就是说,随着器件的集成度增加,结会变得更浅、表面电阻增大,因此饱和电流减小。第三,为了活化源极/漏极中注入的杂质,800℃以上的高温热处理是必须的。因此,不能使用金属栅极。第四,结界面的软错误率(soft error)高并产生浮体效应(floating body effect)。
为了解决上述问题,已经提出了一种使用金属硅化物作为源极/漏极的材料的SB晶体管制造技术。按照这一技术,由于由源极/漏极掺杂导致的问题不再发生,源极/漏极电阻可大大减小。此外,可省略高温热处理工序。因此,这一技术与为满足器件的低功耗/快处理速度而使用金属作为栅电极的工艺相兼容。
在传统的SB晶体管制造方法中,源极/漏极通过加热沉积的金属以导致硅化,然后通过选择性湿法刻蚀去除未反应的金属来形成。硅化和选择性湿法刻蚀是本领域公知的硅化物工艺。然而,自从近来对用SB晶体管作为对纳米电子器件的替代的兴趣提高,SB晶体管的结构和制造工艺的优化依然未获得。在这一点上,有效调节肖特基势垒的高度且同时优化超小器件的制造工艺是必要的,该高度极大地影响器件的特性。
特别地,SB晶体管制造方法中一个重要并且有难度的工序是用于仅去除未反应金属的选择性湿法刻蚀。选择性湿法刻蚀的难度因金属的类型和腐蚀图案而不同。但是,使用贵金属和形成精细图形加大了选择性湿法刻蚀的难度。
SB晶体管制造方法中另一个重要并且有难度的工序是刻蚀损伤的去除。SB晶体管中,金属硅化物层和硅衬底之间的界面特性是非常重要的。栅极侧壁隔离壁的形成过程中产生的刻蚀损伤是有害地影响金属硅化物层和硅衬底之间的界面特性的主要因素。到目前为止,还没有刻蚀损伤的有效解决办法。
发明内容
本发明提供一种因消除了对选择性湿法刻蚀的需要且降低了刻蚀损伤而具有优化的电特性的SB晶体管。
本发明还提供一种能够消除对选择性湿法刻蚀的需要且降低刻蚀损伤的SB晶体管的制造方法。
根据本发明的一个方面,提供一种SB晶体管。该SB晶体管包括形成在衬底上的栅极,以及栅极和衬底之间的栅极绝缘层。隔离壁形成在栅极侧壁上以使栅极上边缘暴露出来。抬高的硅化物源极/漏极形成在衬底上邻近栅极。多晶硅层形成在隔离壁上并覆盖栅极的上表面和上边缘。
根据本发明的另一方面,提供一种SB晶体管的制造方法。该方法包括:在衬底上形成栅极,且栅极和衬底之间具有栅极绝缘层;在栅极侧壁上形成隔离壁;利用选择性硅生长分别在栅极和衬底上生长多晶硅层和单晶硅层;在多晶硅层和单晶硅层上沉积金属;以及使金属与多晶硅层和单晶硅层的硅反应以形成自对准的金属硅化物层。
根据本发明,通过选择性硅生长使多晶硅层形成在栅极顶部。多晶硅层覆盖栅极上表面和上边缘。因此,隔离壁产生一遮蔽区域(shadow area),也就是其上没有沉积用于硅化的金属的区域。由于遮蔽区域电绝缘栅极和源极/漏极,因此可以省略去除未反应金属的选择性湿法刻蚀工艺。另外,生长在衬底上的单晶硅层可减小隔离壁蚀刻过程中引起的刻蚀损伤。
附图说明
参照附图,从本发明示例性实施例的下列描述中,本发明的上述和其它特点以及优点将更为明显。这些附图中:
图1是根据本发明一个实施例的SB晶体管的剖面图;
图2-11是根据本发明的一个实施例说明SB晶体管制造工序的剖面图;以及
图12是根据本发明的一个实验性的实施例经历选择性硅生长的衬底的扫描电子显微镜(SEM)的图像。
具体实施方式
现在,将参照其中示出本发明的优选实施例的附图更加全面地描述本发明。然而本发明可以以许多不同的形式实施,并不局限于在此提出的实施例。相反,提供这些实施例以全面彻底地揭示本发明,并将本发明的范围完整地传递给本领域的普通技术人员。在附图中,为了清楚,放大了元件的形式。为便于理解,尽可能使用相同的附图标记来表示附图中的相同元件。
图1是根据本发明的一个实施例的SB晶体管的剖面图。参照图1,整个结构形成在绝缘体上硅(silicon on insulator)(SOI)晶片1上。SOI晶片1具有基底硅层5、作为绝缘层的掩埋氧化物层(buried oxide layer)10和超薄单晶硅层20的顺序堆叠结构。栅极60a形成在SOI晶片1上,同时栅极绝缘层30置于栅极60a和SOI晶片1之间。栅极60a可以由高浓度杂质掺杂的多晶硅制成,也可由诸如钨或铝的金属制成。由绝缘材料制成的隔离壁80a形成在栅极60a的侧壁上,使得栅极60a的上边缘暴露出来。
通过在SOI晶片1上生长硅单晶层,随后进行硅化,抬高的硅化物源极/漏极130得以形成在SOI晶片1上邻近栅极60a。隔离壁80a防止栅极60a和源极/漏极130之间的短路。
多晶硅层100形成于隔离壁80a之上并覆盖栅极60a的上表面和上边缘。硅化物层120a可以形成在多晶硅层100上。这里,源极/漏极130和硅化物层120a由诸如钴、钨、镍、钯、铂、或钛硅化物的金属硅化物制成。
形成在栅极60a的顶部的多晶硅层100覆盖栅极60a的上表面和上边缘。因此,当沉积用于硅化的金属时,隔离壁80a形成了遮蔽区域,也就是没有沉积金属的区域。遮蔽区域阻止硅化物层120a和源极/漏极130之间的连接,这使得可以省略硅化后用于去除剩余金属的选择性湿法刻蚀工序。
图2-11是说明按照本发明一个实施例的SB晶体管的制造工序的剖面图。
可以采用传统的硅衬底。但是,考虑到可以优选制造具有最小漏电流的超小SB晶体管,优选使用SOI晶片。参照图2,SOI晶片1通常是通过在基底硅层5上形成掩埋氧化物层10和在掩埋氧化物层10上形成超薄单晶硅层20而获得。
参照图3,栅极绝缘层30形成在SOI晶片1上,用于形成栅极电极的导电层40形成在栅极绝缘层30上。栅极绝缘层30可以是例如氧化硅层、氧化钛层或氧化钽层的氧化物层。栅极绝缘层30可以采用传统沉积方法诸如化学气相沉积(CVD),低于大气压的(sub-atmospheric)CVD(SACVD),低压CVD(LPCVD),或等离子体增强CVD(PECVD)形成。或者,栅极绝缘层30可以是通过热氧化单晶硅层20而形成的氧化物层。导电层40可以是高浓度杂质掺杂的多晶硅层或者是金属层。高浓度杂质掺杂的多晶硅层可以采用LPCVD在500-700℃下形成。由于沉积纯的多晶硅,随后进行砷(As)或磷(P)的离子注入,所以高浓度杂质掺杂的多晶硅层可以具有导电性。或者,可以在沉积的过程中进行杂质的原位(in-situ)掺杂。导电层40可以由钨或铝制成。然后在导电层40上镀覆光致抗蚀剂,随后通过曝光和显影,形成用于构图栅极的掩模50。
导电层40利用掩模50通过反应离子刻蚀法(RIE)刻蚀形成栅极60。图4示出了去除掩模50后的晶片结构。
对于完成SB晶体管结构,形成绝缘隔离壁以防止栅极和源极/漏极之间的短路是必不可少的。在这一点上,图5和6、以及图7和8分别示出了两种形成隔离壁的方法。参照图5和6,按照第一种方法,绝缘层70利用LPCVD在栅极60上形成(参见图5),然后通过RIE得以各向异性刻蚀而在栅极60的侧壁上形成隔离壁70a(参见图6)。绝缘层70可以是氮化硅层。在这种情况下,氮化硅层通过SiH4和NH3在500-850℃的温度下的反应而形成。刻蚀绝缘层70的深度与栅极60的高度成正比。可是,考虑到随后的工艺,优选的是进一步刻蚀衬底,也就是说刻蚀单晶硅层20多达200-500的厚度d。同样优选形成隔离壁70a使栅极60上边缘的栅极材料暴露出来。通过如后所述的适度湿法刻蚀、或者选择性硅生长的起始阶段的原位清洗,栅极的上边缘也可以在形成隔离壁70a后暴露出来。
参照图7和8,根据第二种方法,对栅极60进行热氧化以形成热氧化层80(参见图7),随后通过RIE法,形成隔离壁80a(参见图8)。虽然图7和8所示的热氧化工艺是高温工艺,但是由于形成窄宽度的栅极60a,该工艺是有利的。类似于上述第一种方法,刻蚀热氧化层80的深度与栅极60a的高度成正比。但是,优选进一步刻蚀单晶硅层20多达200-500的厚度d。同样,优选形成隔离壁80a,使栅极60a上边缘的栅极材料暴露出来。栅极的上边缘也可以通过适度湿法刻蚀(mild wet etching)、或者选择性硅生长的起始阶段的原位清洗,在形成隔离壁80a后暴露出来。
图9-11示出图8的后续工艺。但是,本领域普通技术人员应当理解,图9-11的工艺可以是图6的后续工艺。
图9-11是本发明最为重要的工艺的顺序说明。如图9所示,形成了隔离壁80a后,通过选择性硅生长,多晶硅层100形成在栅极60a上,单晶硅层110形成在晶片上的预定形成源极/漏极的区域上。多晶硅层100的厚度形成为200-500。如上面所提到的,当图7的隔离壁80a的形成过程中栅极60a的上边缘的栅极材料没有暴露出来时,在进行选择性硅生长之前,进行适度的湿法刻蚀工艺或原位清洗工艺以暴露栅极60a的上边缘。
当在LPCVD系统中进行选择性硅生长时,为原位清洗工艺进行H2烘烤(H2-baking)以暴露栅极60a的上边缘。这时,优选在700-900℃下进行H2烘烤,H2的流速为0.5至50slm,压力为0.1至10Torr(乇),持续60至300秒。然后,使用二氯甲硅烷(dichlorosilane)(DCS,SiCl2H2)、HCl和H2作为反应气体(process gas)进行选择性硅生长。DCS的流速可以为0.1至2slm,HCl的流速可以为0至3slm,H2的流速可以为10至150slm,反应温度可以为780-930℃,反应压力可以为20-250Torr。特别地,优选在反应温度降低时降低反应压力。
当在超高真空化学气相沉积(UHV-CVD)系统中进行选择性硅生长时,也可以在UHV-CVD系统中而不是LPCVD系统中进行原位清洗。为原位清洗进行真空清洗以暴露栅极60a的上边缘。在此情况下,真空清洗可以在650-800℃的温度下,10Torr或更小压力的超高真空中进行60-300秒。选择性硅生长的反应气体可以是Si2H6或SiH4、Cl2和H2。Si2H6或SiH4的流速可以为1-10sccm,Cl2的流速可以为0-5sccm,H2的流速可以为0-20sccm,反应温度可以为500-750℃的范围,反应压力可以为0.1-50mTorr的范围。
当选择性硅生长在如上所述的工艺条件下进行时,从栅极60a的侧表面的上部横向生长的多晶硅层100的厚度比单晶硅层110的厚度大1.5-2倍。这是因为在用作栅极材料的高浓度杂质掺杂的多晶硅或者金属中促进了选择性硅生长。因此如图9所示,尖锐的负斜坡(sharp negative slope)102形成在多晶硅层100的下表面上。
选择性硅生长之后,如图10所示,沉积肖特基势垒金属120。由于多晶硅层100的负斜坡,隔离壁产生了相应于其上不沉积肖特基势垒金属的区域的遮蔽区122。肖特基势垒金属120可以是钴、钨、镍、钯、铂或钛。肖特基势垒金属120可以利用物理沉积法沉积,例如溅镀、蒸镀、分子束外延生长、离子簇沉积(ionized cluster beam deposition)(ICP)、或激光诱导物理沉积。肖特基势垒金属120的沉积厚度为50-500。
然后,如图11所示,当进行热处理时,硅化物层120a形成在栅极60a上。同时,由硅化物形成的抬高的源极/漏极130形成在SOI晶片的表面上,邻近栅极60a。形成硅化物的热处理可以在300-600℃下在热处理炉中进行0.5-2小时。或者,可以使用快速热处理系统。在此情况下,热处理可以在800-1200℃下进行1-30秒。
虽然肖特基势垒金属120残存于部分隔离壁80a上,但是遮蔽区122使栅极60a与源极/漏极130电绝缘。就是说,可以省略去除未反应金属的选择性湿法刻蚀工艺。单晶硅层110的生长降低了隔离壁80a形成过程中引起的刻蚀损伤,从而改进了器件的电特性。
图12是根据本发明的实验性实施例,经历了选择性硅生长的晶片的扫描电子显微镜(SEM)的图像。
从上面的描述中很明显,由于根据本发明的SB晶体管的制造过程中不包含离子注入,所以可以省去与离子注入相关的大量工艺。因此,生产成本的减小是可以预期的。同时,由于根据本发明的SB晶体管按照量子机理进行操作,因此可以有效地应用于量子器件。
此外,超小SB晶体管的制造中的选择性硅生长具有如下优点。
第一,可以优化工艺。多晶硅层的自栅极上边缘的生长产生了其上没有金属沉积的隔离壁区域。因此,可以省略去除未反应金属的选择性湿法刻蚀。衬底上的单晶硅层的生长降低了源极/漏极的隔离壁刻蚀损伤,因此改进了器件特性。虽然在使用贵金属或形成精细图形时不能进行传统的选择性湿法刻蚀,但是甚至在使用贵金属或形成精细图形时也可以应用本发明,因而扩展了器件的应用范围。
第二,制造工艺简单化,并确保了改善的器件特性,因此有利于制造超小高性能的半导体器件。
虽然参照本发明的示范性实施例具体地展示并描述了本发明,但本领域普通技术人员应当理解,在不脱离所附权利要求所限定的本发明的精神和范围的情况下,可以进行形式上和细节上的各种变化。
Claims (22)
1.一种肖特基势垒晶体管,包括:
形成在衬底上的栅极,具有该栅极和该衬底之间的栅极绝缘层;
形成在该栅极的侧壁上使得该栅极的上边缘暴露出来的隔离壁;
形成在该衬底上邻近该栅极的抬高的硅化物源极/漏极;以及
形成在该隔离壁上方并覆盖该栅极的上表面和该上边缘的多晶硅层。
2.根据权利要求1所述的肖特基势垒晶体管,还包括形成在该多晶硅层上的硅化物层。
3.根据权利要求1所述的肖特基势垒晶体管,其中该栅极由高浓度杂质掺杂的多晶硅或金属构成。
4.根据权利要求1所述的肖特基势垒晶体管,其中该衬底是绝缘体上硅晶片。
5.一种制造肖特基势垒晶体管的方法,包括:
在衬底上形成栅极,且栅极绝缘层位于该栅极和该衬底之间;
在该栅极的侧壁上形成隔离壁;
使用选择性硅生长,在该栅极和该衬底上分别生长多晶硅层和单晶硅层;
在该多晶硅层和该单晶硅层上沉积金属;以及
使该金属与该多晶硅层和该单晶硅层的硅反应而形成自对准金属硅化物层。
6.根据权利要求5所述的方法,其中该隔离壁通过该多晶硅层产生其上不沉积该金属的区域。
7.根据权利要求6所述的方法,其中该栅极上的该硅化物层和该衬底上的该硅化物层通过该隔离壁的其上不沉积该金属的该区域电绝缘。
8.根据权利要求5所述的方法,其中该栅极由高浓度杂质掺杂的多晶硅或者金属构成。
9.根据权利要求5所述的方法,其中该隔离壁的形成包括:
在该栅极上沉积绝缘层;以及
各向异性刻蚀该绝缘层。
10.根据权利要求5所述的方法,其中该隔离壁的形成包括:
热氧化该栅极以围绕该栅极形成氧化层;以及
各向异性刻蚀该氧化层。
11.根据权利要求10所述的方法,其中在该刻蚀过程中,刻蚀该衬底至200-500的深度。
12.根据权利要求11所述的方法,还包括采用适度湿法刻蚀工艺暴露该栅极的该上边缘。
13.根据权利要求11所述的方法,还包括在选择性硅生长的初始阶段使用原位清洗工艺暴露该栅极的该上边缘。
14.根据权利要求13所述的方法,其中该原位清洗工艺在低压化学气相沉积系统中进行,温度为700-900℃,H2的流速为0.5-50slm,压力为0.1-10Torr,进行时间为60-300秒。
15.根据权利要求14所述的方法,其中该多晶硅层和该单晶硅层的生长在低压化学气相沉积系统中进行,采用二氯甲硅烷、HCl和H2作为反应气体,二氯甲硅烷的流速为0.1-2slm,HCl的流速为0-3slm,H2的流速为10-150slm,反应温度为780-930℃,反应压力为20-250Torr。
16.根据权利要求15所述的方法,其中当反应温度降低时,该反应压力下降。
17.根据权利要求13所述的方法,其中该原位清洗在超高真空化学气相沉积中,在650-800℃的温度下,在10Torr或更小压力的超高真空下进行60-300秒。
18.根据权利要求17所述的方法,其中该多晶硅层和该单晶硅层的生长是在超高真空化学气相沉积系统中进行,使用Si2H6或SiH4、Cl2和H2为反应气体,Si2H6或SiH4的流速为1-10sccm,Cl2的流速为0-5sccm,H2的流速为0-20sccm,反应温度为500-750℃,并且反应压力为0.1-50mTorr。
19.根据权利要求5所述的方法,其中形成在该栅极上的该多晶硅层的厚度为200-500。
20.根据权利要求5所述的方法,其中该金属的沉积厚度为50-500。
21.根据权利要求5所述的方法,其中形成该自对准金属硅化物层是在300-600℃在热处理炉中进行0.5-2小时。
22.根据权利要求5所述的方法,其中形成该自对准金属硅化物层是在800-1200℃在快速热处理系统中进行1-30秒。
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- 2003-12-23 US US10/746,493 patent/US7005356B2/en not_active Expired - Fee Related
- 2003-12-26 JP JP2003435892A patent/JP4104541B2/ja not_active Expired - Fee Related
- 2003-12-26 TW TW092136989A patent/TWI224862B/zh not_active IP Right Cessation
- 2003-12-31 AT AT03258260T patent/ATE511214T1/de not_active IP Right Cessation
- 2003-12-31 EP EP03258260A patent/EP1469525B1/en not_active Expired - Lifetime
- 2003-12-31 CN CNB2003101147931A patent/CN1315196C/zh not_active Expired - Fee Related
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Also Published As
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EP1469525A2 (en) | 2004-10-20 |
US7005356B2 (en) | 2006-02-28 |
JP2004319963A (ja) | 2004-11-11 |
JP4104541B2 (ja) | 2008-06-18 |
KR100508548B1 (ko) | 2005-08-17 |
EP1469525B1 (en) | 2011-05-25 |
ATE511214T1 (de) | 2011-06-15 |
TWI224862B (en) | 2004-12-01 |
CN1315196C (zh) | 2007-05-09 |
US20040206980A1 (en) | 2004-10-21 |
TW200423400A (en) | 2004-11-01 |
EP1469525A3 (en) | 2007-12-05 |
KR20040090063A (ko) | 2004-10-22 |
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