CN1557016A - 使用纳米管带子的机电式存储阵列及其制法 - Google Patents
使用纳米管带子的机电式存储阵列及其制法 Download PDFInfo
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Abstract
揭示了机电式电路,如存储单元,及其制法。所述电路包括由电导轨线和从基质表面延伸的支持构成的结构,以及由穿过电导轨线的支持悬置的纳米管带子,其中各个带子包括一个或多个纳米管。所述机电式电路元件可由具有电导轨线和支持的结构制成,其中的支持从基质表面延伸。在支持上有一层纳米管,并选择性除去纳米管层的某些部分,形成穿过电导轨线的纳米管带子。每个带子包括一个或多个纳米管。
Description
相关申请的交叉引用
本申请与下列申请相关,它们都与本申请同日提交,并全部转让给本申请的受让人,而且它们全部参考结合于此:
具有纳米管机电式存储器的混合电路(美国专利申请系列号,尚未转让);
用纳米管技术制造的具有存储单元选择电路的机电式存储器(美国专利申请系列号,尚未转让)。
背景
1.技术背景
本发明一般涉及用作电子装置存储装置的非易失存储器,特别涉及使用机电式元件作为单个存储单元的非易失存储阵列。
2.相关技术的讨论
电子装置的存储单元的重要特性是低成本、非易失性、高密度、低功率和高速。常规的存储器包括只读存储器(ROM)、可编程序只读存储器(PROM)、电可编程序存储器(EPROM)、电可擦除可编程序存储器(EEPROM)、动态随机存取存储器(DRAM)和静态随机存取存储器(ERAM)。
ROM相对费用较低但无法改写。PROM可电子编程但只有一个写入周期。EPROM的阅读周期相对ROM和PROM的阅读周期快,但其擦去时间相对较长且只有几个迭代的读/写周期。EEPRO(或“闪存”)比较便宜,且是低功率的,但写入周期(ms)较长,且相对速度低于DRAM或SRAM。闪存也有限定数目的读/写周期,从而导致较低的长期可靠性。ROM、PROM、EPROM和EEPROM都是非易失的,即如果存储器的电源中断,存储器会保存存储单元中储存的信息。
DRAM将电荷存储在作为电容器的晶体管的门中,但每几个毫秒就必需电更新一次,这使系统设计复杂化,因为需要单独的电路来在电容器放电之前将存储内容“更新”。SRAM不需要更新,且相对于DRAM速度较快,但密度较低且更加昂贵。SRAM和DRAM都是易失的,即如果存储器的电源中断则将丢失存储单元中储存的信息。
因此,现有的技术要么是非易失的,但不是随机存储,且密度低、成本高,难以以高的电路功能可靠性多次写入,要么是易失的,系统设计复杂或密度较低。一些新兴的技术已经在试图解决这些问题。
例如,磁性RAM(MRAM)或铁磁RAM(FRAM)利用磁化的取向或铁磁区域来产生非易失的存储单元。MRAM采用磁阻性存储元件,其中包括各向异性的磁阻或铁磁材料的巨大磁阻来产生非易失性。这些类型的存储单元都有相对较高的电阻和低密度。另一种基于磁性隧道结的存储单元已经在试验,但还未用于大规模商业生产MRAM装置。FRAM采用与DRAM类似的电路,但其中使用了薄膜铁电电容器。这种电容器可在除去外部施加的电场后保留其电极化,从而产生非易失的存储器。FRAM的缺点在于存储单元尺寸过大,并且不易于作为大规模集成元件进行制造。参见美国专利4,853,893;4,888,630;5,198,994。
另一种具有非易失存储器的技术是相变储存器。这种技术通过含有如硒或碲元素的薄膜合金的结构相变来储存信息。这些合金在晶体状态和无定形状态下都保持稳定,从而形成了双稳开关。尽管满足了非易失条件,这种技术似乎有操作慢、制造困难、可靠性低和未达到商业规模的缺点。参见美国专利3,448,302;4,845,533;4,876,667;6,044,008。
还提出了电线纵横制存储器(MWCM)。参见美国专利6,128,214;6,159,620;6,198,655。这些存储器设想以分子作为双稳开关。两根电线(金属或半导体类型)之间有分子层或分子型化合物层。采用化学装配和电化学氧化或还原来产生“开”或“关”状态。由于氧化还原过程固有的不稳定性,这种存储器形式需要高度专一的电线连接,且可能无法保持非易失性。
最近提出了使用纳米电线,如单壁碳纳米管,形成纵横制结作为存储单元的存储装置。参见WO 01/03208,基于纳米电线的装置、阵列及其制造方法(NanoscopicWire-Based Devices,Arrays,and Methods of Their Manufacture);以及ThomasRueches等人的“用于分子计算的基于碳纳米管的非易失随机存取存储器”(CarbonNanotube-Based Nonvalatile Random Access Memory for Molecular Computing),Science,289卷,94-97页,2000年7月7日。下面将这些装置称为纳米管线纵横制存储器(NTWCM)。在这些建议下,悬置在其它电线上的各个单壁纳米管线形成了存储单元。电信号被写到一根或两个电线,使它们相互物理吸引或排斥。每一物理状态(即相吸或相斥的电线)相应于一种电学状态。相斥的电线是开放的电路结。相吸的电线是形成整流结的闭合状态。当从结上除去电源时,这些电线保持其物理状态(因而保持电状态),从而形成非易失存储单元。
NTWCN建议迄今采用直接生长或化学自装配技术来生长存储单元所需的各个纳米管。现在认为这些方法难以采用现代技术在商业规模上应用。此外,它们可能有固有的缺陷,例如用这些技术制造的纳米管的长度问题,且可能难以控制如此生长的纳米管的几何统计变异。
发明简述
本发明提供了机电式电路,如存储器单元,及其制造方法。所述电路包括由电导轨线和从基质表面延伸的支持物构成的结构,以及由支撑层悬置的穿过电导轨线的纳米管带子,其中各个带子包括一个或多个纳米管。
根据本发明的一个方面,所述机电式电路元件由具有电导轨线和支撑层的结构制成,其中的支持从基质表面延伸。在支持上有一层纳米管,并且选择性地除去纳米管层部分以形成穿过电导轨线的纳米管带子。每个带包括一个或多个纳米管。
附图简述
附图中,
图1显示依据本发明的某些实施方式,一种纳米管带子纵横制存储装置;
图2A-B显示依据本发明的某些实施方式,一种存储单元的两种状态;
图3显示依据本发明的某些实施方式,制造存储装置的步骤;
图4-11显示依据本发明的某些实施方式,产生用来制造存储装置的中间结构的几种形式;
图12显示用来制造本发明的某些实施方式的非织造纳米管织物或毡合的纳米管层;
图13显示与本发明的某些实施方式中毡合的纳米管层与隐藏在下面的轨线的关系;
图14显示本发明某些实施方式的寻址逻辑;
图15显示本发明实施方式的一种混合技术,其中存储核心使用了纳米管技术;
图16显示本发明实施方式的一种混合技术,其中存储核心和寻址线使用了纳米管带子技术;
详细描述
本发明的优选实施方式提供了新颖机电式存储阵列及其制造方法。具体言之,创造了按照类似于WO 01/03208中所述NTWCM装置操作的机电式存储单元,该文献全文参考结合于此。但是,和WO 01/03208中所述的NTWCM装置不同,本发明优选的实施方式将NTWCM装置中使用的悬置的纳米电线换成新的纳米管的毡合层或纳米管的非织造织物的带子。这些新的装置在这里被称为纳米管带子纵横制存储器(NTRCM)。这种新的纳米管带子结构被认为容易以所需的集成度和规模(所生产的装置数)制造,而且其几何形状也较易控制。
因为新型的纳米管带子纵横制存储器装置的运行和NTWCM相似,它们的结构描述和运行原理在此是简单的,其描述和背景可参见WO 01/03208。
图1显示依据本发明优选实施方式的原理所构建的一个典型的机电式存储阵列100。该阵列有很多非易失性存储单元103,可置于“开”或“关”的状态。这样的单元的确切数目对于理解本发明并不重要,但是,其技术可支持其信息存储容量与现代非易失性电路装置的容量相当或更大的装置。
每个存储单元103包括一根纳米管带子101,它通过一个或多个支撑层102悬置在电路轨线或导线例如104上方。
每根带子101和导线如104的交叉,形成了一个交叉结,构成了一个存储单元。在有些实施方式中,通过对电极112(该电极与带子101电路连通施加电流或电压,或通过与轨线或导线104连通的电极(未显示),各个单元可被读写。支撑层102是氮化硅(Si3N4)层108。在层108的下面是门氧化物层109,它将n-掺杂的硅轨线与下面的硅片110分隔。
试联合参见图1-2B,结106显示了在第一种物理和电学状态的单元,其中纳米管带子101和对应的轨线104分隔。结105显示了在第二种物理和电学状态的单元,其中纳米管带子101弯曲朝对应的轨线104。在第一种状态中,结是开路的,当就这样寻址时,它可在带子101或轨线104上被探测到是这种状态。在第二种状态中,结是个整流结(如Schotty或PN结),当就这样寻址时,它可在带子101或轨线104上被探测到是这种状态。
在某些实施方式中,纳米管带子101可通过摩擦固定在支撑层上,在其它的实施方式中,带子可用其它方法来固定,如使用任何其它的技术将带子钉扎在支撑层上。通过化学相互作用可使摩擦增强,包括通过例如芘或其它化学活性物质的碳化合物来进行共价结合。蒸发或旋涂的材料如金属、半导体或绝缘体,尤其是硅、钛、二氧化硅或聚酰亚胺也可加入用以提高此钉扎的强度。纳米管带子或单个的纳米管也可使用晶片结合在表面上。参见R.J.Chen等。“用于蛋白质固定化的单壁碳纳米管的非共价边壁功能化”美国化学会杂志。,123,2001,3838-39和Dai等人,《应用化学通讯》77,2000,3015-17,其中描述了用金属钉扎和涂布纳米管的典型技术。也可参见WO 01/03208中的技术。
在图2A-B显示的某些优选的实施方式中,纳米管带子101的宽度约为180nm,它钉扎在优选由氮化硅制成的支撑层102上。在带子101下面的轨线104的局部区域形成n-掺杂的硅电极,且在接近支撑层102的位置,其宽度优选不超过带子如180nm的宽度。从支撑层102的顶部到带子101连接电极206的下弯位置(见图2B)的相互间距208应为5-50nm。此间距208的大小的设置应与存储器的机电式开关性能适应。对于此实施方式,5-50nm的间距对于使用纳米管制成的带子101的某些实施方式是优选的,但对其他材料,其他间距也可能较好。这个间距大小是由下弯的纳米管的应变能和附着能的相互作用而产生的。这些特征尺寸是由现代制造技术所提出的。在其它实施方式中,根据制造设备的能力,该下弯尺寸或大或小。
某些实施方式的纳米管带子101是由一种缠绕或毡合的纳米管非织造织物形成的(下面将详述)。这种带子的开关参数与单根的纳米管相似。这样,预计的带子的开关时间和电压大约和纳米管的开关时间和电压相近。和先前依赖于单个纳米管的定向生长和化学自组装的技术不同,本发明的优选的实施方式中,使用薄膜和平版印刷的制造技术。这种制造方法能产生超大的表面,尤其是至少6英寸的晶片。(与此不同,让纳米管生长超过亚毫米级的尺寸现在还难以做到)。纳米管带子与单个纳米管相比,应有更好的缺陷容忍性,这是因为在带子中提供了许多导电通路的缘故。(如果带子中一根纳米管损坏了,其它纳米管还能提供其它导电通路,而如果使用单根纳米管,存储单元就损坏了)。还有,带子的电阻应比单根的纳米管小得多,这样就减少了阻抗,因为纳米管带子可比单个纳米管制成更大的截面积。
图3显示某些实施方式的NTRCM装置100的制造方法。先制造或提供第一中间结构层302。在所示的实施方式中,结构层302包括一个硅基片110,它具有一个绝缘层109(如二氧化硅)和一个氮化硅层108,后者形成很多支撑层102。在此例中,支撑层102是排列成图案形式的氮化硅,但是其它的排列也可能,例如很多纵列。导电轨线104在支撑层102之间延伸。在此例中,轨线104与支撑层102是基本互相接触的,但其它的排列以及另外的几何形状也有可能,例如:轨线104和支撑层102之间可以有空间,轨线104可以是导线的形状,或有非矩形的纵截面或横截面,包括三角形或梯形截面。牺牲层304位于轨线104上方,和支撑层102的上表面形成一个平表面306。此平表面,下面将要叙述,有助于形成一层毡合的纳米管层。
结构302制成或提供了后,其上表面306上施加一种催化剂308。例如,某些实施方式中,一种含铁(Fe)、钼(Mo)、钴或其它金属的金属催化剂,用旋涂或其它技术施加上去,形成一个第二中间结构层310。
然后,一个毡合的纳米管层312生长为单壁纳米管非织造织物,形成第三中间结构层314。例如,第二中间结构层可置于一加热炉中,加热至高温(如800-1200℃),同时将含有碳源物质、氢气和惰性气体如氩气或氮气的气体吹过其上表面。此气氛使得单壁碳纳米管的毡合层或膜312有可能产生或生长。312层主要是一个纳米管的厚度,不同的纳米管之间通过范德华力相互连接。偶而会有一个纳米管在另一个纳米管的上面生长,但是因为此材料的生长特性,这种生长是不常见的。在一些实施方式中(图中未显示),催化剂308可以以一定图案形式分布,生长成特定密度的纳米管,可按要求的密度大或小些。当催化剂的组成和密度、生长气氛和时间条件适当地控制后,纳米管可以均匀地分布在一给定区域,主要是单层。合适的生长要求控制的参数,包括但不限于催化剂的组成和浓度、下面表面的功能化、旋涂参数(长度和每分钟转数)、生长时间、温度和气体浓度。
一层光致抗蚀剂然后可施加在层312上,并使层312具有一定图案形式,用以形成毡合纳米管层312形式的带子。该带子的图案穿过(例如垂直)下层的轨线104。去除光致抗蚀剂后,留下非织造的纳米管织物带子101在306平面上,形成第四中间层318。
第四中间层318中有一些部分320,如图所示露出其下面的牺牲层304。结构318然后用酸如HF处理,除去牺牲层304,包括带子101下面的部分。这样就形成了悬置在轨线104上面并由支撑层102支撑的带子101的阵列322。
接下来的金属化可用来形成寻址电极,如图1所示的112。
上述技术的一个方面,是不同的生长、图案化和腐蚀操作可以使用常规技术。如平版印刷图案化。目前,它可以产生的特征尺寸(如带子101的宽度)为约180nm到小至130nm。但如制造技术容许,元件的物理性能可以做到使其特征尺寸更小。
下面将要进行解释,有很多可能的方法用来生成上述中间结构层或相似的结构层。图4,例如就显示了一种生成第一中间结构结构层302的方法。
一块硅片400带有氧化物层402。该氧化物层优选是有几个纳米厚,也可厚至1微米。一层氮化硅(Si3N4)层404沉积在氧化物层402的上面,该氮化硅层优选至少有30nm厚。
氮化硅层然后经图案化并腐蚀产生凹穴406,形成支撑结构407。使用现代技术,凹穴的宽度可以是180nm或更小。剩下的氮化硅材料则形成支撑层102(例如成横排或纵列)。
然后将n-掺杂的硅覆盖层408沉积上去,填满凹穴406。典型的覆盖层408的厚度是1微米,但可薄至30nm。
覆盖层408然后经过加工,例如该厚硅层的自平化或退火,形成平表面306,如上所讨论的,形成结构411。若是自平化,可以使用带终点探测(EPD)的反应性离子腐蚀(RIE)进行,直至达到经腐蚀的氮化硅的上表面410。
结构411然后进行氧化,以形成二氧化硅牺牲层304,它在平表面306以下10-20nm深。
未转化的余下的硅则形成轨线104。
图5显示另一种制造方法可用来形成NTRCM装置100。先提供一个如图4所示的一个支撑结构407,然后用CVD、溅射或电镀的方法加上一层n-掺杂硅层514。在某些实施方式中,所加的层514的厚度是氮化硅支撑层102厚度的一半。
层514加上以后,进行退火操作以生成一平表面306,形成如上所述的结构411。该退火操作使层514中的硅流入到凹穴406中。
如就图4所述的,结构411然后经过氧化,形成二氧化硅牺牲层304,它深入平表面306以下10-20nm。
图6显示形成另一种第一中间结构层302’的另一种方法。在此实施方式中,一个硅基片600上覆盖有一层氮化硅层602,其厚度604至少为30nm。
氮化硅层602然后经图案化并腐蚀产生凹穴606并形成支撑层102。该腐蚀操作暴露出硅基片600表面的一部分608。
暴露的硅表面608经氧化产生二氧化硅(SiO2)层610,其厚度为几个纳米。这些层610最终使轨线104绝缘,其方式与上述结构302中的绝缘层109相似。
一旦绝缘层610形成后,轨线104可用多种方法制备。图6显示了图4-5中的制造步骤,用来生成这样的轨线进行说明。
图7显示另一种形成第一中间结构层302的方法。一个硅基片700上具有一个二氧化硅层702和一个氮化硅层704,后者上面再有图案化的光致抗蚀剂层706。例如,一个光致抗蚀剂层可旋涂在层704上,再经曝光和光刻显影。
反应性离子腐蚀(RIE)等方法然后可以用来腐蚀氮化硅层704,形成凹穴708并形成支撑层102。
然后,n-掺杂的硅710可沉积进入凹穴708中,在某些实施方式中,硅的沉积高度大约与氮化硅支撑层102的高度712相同
然后除去光致抗蚀剂706和在光致抗蚀剂706上的硅710,形成如上所述的中间结构层411。
结构层411然后经氧化生成二氧化硅牺牲层304。
图8显示生成第一中间结构层302的另一种方法。在这种方法中,提供一起始结构800,它具有最低的硅层802,其上有最低的二氧化硅层804。第二硅层806置于层804上,而第二个二氧化硅层808又置于第二硅层806之上。
顶部的二氧化硅(SiO2)层808经光刻图案化,生成RIE掩模810。此掩模用来腐蚀第二硅层806的外露部分812,直到第一二氧化硅层804。该腐蚀操作生成凹穴814并形成轨线104。
凹穴814用氮化硅(Si3N4)816填满和覆盖之。
此氮化硅覆盖层经RIE背腐蚀达到高度818,和覆盖着n-掺杂硅电极104的二氧化硅层806余下部分一致(形成牺牲层304)。
图9显示形成第一中间结构层302”的另一方法。在此方法中,先提供类似407的结构(在图4中显示,图9中未显示)。在此例子中,Si3N4支撑层102的高度约为30nm。一金属薄层902沉积在Si3N4支撑层102的上面,并沉积在凹穴904底部的SiO2外露的部分上,此沉积的部分标为903。金属902和903形成暂时的电极。然后,用电镀方法沉积或生长一层n-掺杂硅层906,覆盖着电极903,直至硅层906的高度908达到支撑102层顶部,并和电极902接触。此生长过程可通过起动上下金属电极902,903之间的电流而加以控制。
外露的金属电极902可用湿化学方法或干化学方法加以去除。这就形成了中间结构层411’,和上述411结构相似。但具有一个埋入的电极903,作为硅生长过程的结果。
结构411’然后经氧化形成位于硅的外露部分的牺牲层304,如上所述。例如,牺牲层304可生长至厚度为10nm。
图10显示形成第一中间结构层302的另一方法,将一个硅基片1002用作起始材料,其上有一个二氧化硅层1004,而在层1004上有第二硅(n-掺杂的)层1006。在层1006上有经光刻图案化的掩模1008。
使用氮化技术,使n-掺杂硅层1006的外露部分1010化学转化为氮化硅支撑层102。1006层的未转化部分形成轨线104。
将掩模1008除去形成一个如上所述的结构411。
硅表面外露的部分1012经氧化形成二氧化硅牺牲层304。
图11显示生成第一中间结构层302的又一个方法。在此方法中,覆盖有Si3N4薄膜1104的硅基片1102作为起始材料,在氮化硅层1104的顶部,施加上n-掺杂硅,用RIE法光刻图案化,形成轨线104。
轨线104的表面经氧化以形成二氧化硅层1106,作为牺牲层304’的另一种形式。
在此结构的的上面再生长氮化硅层1108,背腐蚀以形成平面306,从而形成又一种第一中间结构结构层302。如本领域中有经验的人士所熟知的,在此方法中,当牺牲层304后来去除后,轨线104会和支撑层102分离。此技术的一些变体可用来生成轨线104另一种横截面形状。例如,轨线104可制成上部圆形的,或有三角形或梯形的横截面。另外,横截面还可以有其它形状,如带有渐缩两边的三角形。
如上所述,第一中间结构层例如302形成后,让一个毡合的纳米管层312生成在层302的平表面306上。在优选的实施方式中,此非织造织物层312生长在此结构上,此时使用催化剂308并通过生长环境的控制。其它实施方式可另行先提供毡合的纳米管层312,然后直接施加在结构302之上。虽然结构302,运用此方法优选地包括牺牲层来提供一个平表面,用来接受先行生长的织物,但在此方法中,牺牲层可以是非必需的。
因为此生长过程使这种纳米管的下面与中间结构层302的平表面306接触,所以显示出一种“自组装”的特点,如图12所示。具体是,一个个纳米管会在其生长的表面上附着,只要在能量上是有利的,这样它们就基本形成一个“单层”。有些纳米管会在其它纳米管上面生长,从而此单层并不是完善的。单个的纳米管并不是和其它纳米管互相编织起来,而是靠范德华氏力相互附着。图12大致显示了一种实际的纳米管非织造织物。因为纳米管的特征尺寸很小,即使现代的扫描电镜SEM也不能将真实的织物拍摄下来而不损失精度;纳米管的特征尺寸为1-2nm,小于SEM的精度。例如,在图12中,显示了织物的毡合特性;图中并不清晰的是,织物中可能有间断的小区域,其中不存在纳米管。每个纳米管的直径典型的是1-2nm(这样就确定了织物的厚度也是1-2nm),但长度是几个纳米,有些甚至是200nm。纳米管可以是弯曲的,偶而也会互相叉。纳米管之间通过范德华氏力相互附着。
在某些实施方式中,纳米管在X-轴和Y-轴方向上基本上不受限制地生长,但在Z-轴方向上(垂直于图12的纸面)生长受到限制,这是因为有自组装的特性。其它实施方式可以对上述方法进行补充,用场取向或流取向的生长技术来生长毡合物312。这样的补充可用来对生长人为设定,如阻止沿一个方向(如X-轴)的生长。这样能以可控的密度形成一层平坦单层的相互交织的纳米管层,更均匀地覆盖所需要的表面。
图13显示了毡合的纳米管层312和其下面的硅轨线104。
如上所解释的,在表面306上有了毡合的纳米管层312以后,将层312图案化和腐蚀,形成纳米管织物带子101,它跨越在支撑层102之上。然后除去牺牲层(如用酸),形成阵列322,如上面图3所示。因为纳米管毡合层312形成的非织造的织物是不连续的,所以腐蚀剂或其它化学试剂可能渗透至纳米管“织物”之间,并很容易地达到下面的部分,如牺牲层。
接着的金属化可用来形成寻址电极,如图1中所示的112。其它实施方式使用纳米管技术来实现存储单元的寻址,而不使用金属化电极112和寻址线(未显示)。
更具体的,在上述某些实施方式中,纳米管可用来形成NTRCM阵列。某些实施方式使用纳米管技术,不管是单根的导线还是带子的形式,用来执行寻址逻辑,从而选择存储单元进行读写操作。此方法还将纳米管技术整合在系统设计中,有利于更高级别的系统设计。例如,在此方法中,存储器结构不仅能以非易失性的方式存储记忆内容,还能存储过去的记忆地址。
基于纳米管的存储单元是双稳态的,其特点是“0”和“1”状态的阻比很高。这两个状态的转换是将特定电压加到纳米管导线或带子和下面的轨线上,其中至少一个存储单元是纳米管或纳米管带子。在一个方法中,加上一“读出电流”并用一个“读出放大器”测出此结上的电压。读出是非破坏性的,意思是存储单元仍保持其状态,不必象DRAM那样需要回写操作。
图14显示分支对分选择系统或解码器1400。下面还将说明,解码器1400可由纳米管或纳米管带子技术形成。还有,解码器可以建立在与作为一个纳米管存储单元阵列如NTRCM或NTWCM相同的电路元件上。
两根线1404和1406的垂直相交点1402,表示两根纳米管或纳米管带子的结。在此方面,其相互作用和CMOS和其它技术中发现的“通过晶体管”相似,其中,此交叉可以是敞开或封闭的。
如1420的那些位点,在该处一个纳米管或纳米管带子和别的纳米管或纳米管带子相交但不拟生成一个交叉结,可以用元件之间光刻图案化的绝缘体来互相绝缘。
为清晰起见,图中所示的解码器是用于一个3位的二进制地址,承载在寻址线1408上。根据编码的值,交叉(点)会进行转换,来产生仅仅一条通路,传感电流可以通过该通路来选择线1418。
使用这个技术,两进制地址的每个位的一个“双轨”表示1408均在外部形成。这样地址位1410的每一个均以真实和补充的形式表示。这样,线1406可以是地址线1408a的逻辑上真实的形式,而线1407可以是地址线1408a的逻辑补充。表示1408的电压值与上述将交叉结转换到“1”或“0”状态所必需的电压是一致的。
这样,一个地址1408可以用来对一个阵列中的位或一排位例如纳米管或纳米管带子提供传感电流I。相似地,同样的方法也能用来感受一给定的轨线,例如,结合选择一个排选择由其读取感受的特定纵列。因此这样的方法可用于X和/或Y解码,用于读或写的操作。
本发明的某些实施方式提供一种混合技术电路1500,如图15所示。用NTWCM或NTRCM构建核心存储单元阵列,该核心被半导体电路包围,形成X和Y地址解码器1504和1506;X和Y缓冲器1508和1510;逻辑控制1512和输出缓冲器1514。包围NTWCM或NTRCM核心的电路可用于常规的接口功能,包括提供读取电流和读取传感输出电压。
在其他实施方式中,X和Y地址解码器可被上述的纳米管导线或带子寻址技术所替代。在这些实施方式中,核心会包括存储单元和寻址逻辑。
在某些实施方式中,可用一个纳米管核心(只具有存储单元或具有存储单元和寻址逻辑)和用一个场可编程门阵列实现周围电路来形成混合电路1500。核心和门阵列电路如果需要,可在一个物理包装内,也可分别包装。例如,一个密闭包装的纳米管电路(具有存储器或存储器和寻址逻辑)可以与一个PLD/FPGA/ASIC组合,其中有I/O接口逻辑。所得的完整的芯片组对于产品的用户而言,可以获得纳米管存储器带来了好处,同时能最大限度地使用现有的技术,该技术可被制造厂家以基于需求的方式使用。
图16显示混合技术的一个可能的执行方式。一个含有缓冲和控制逻辑(如上所述)的FPGA芯片1602,通过在一个(也许是多层)印刷线路板(PCB)1604上的导电轨线连接到一个含有存储单元和寻址逻辑的纳米管芯片(NT)1606上。
这个具体的实施方式提出,能符合当今个人电脑通用的PCI总线标准。其它无源线路,如电容、电阻、变压器等(未示出)也需要符合PCI标准。一个为200MHz-400MHz正面总线速度已作了标示,表明这样的芯片组可以这样的外部时钟速度运行。此速度受到PCB内部连线和FPGA/PLD/ASIC的速度以及芯片包装的限制,而不是受纳米管存储单元速度的限制。
其它实施方式
除了碳纳米管以外,其它电子和机械性能适于做机电式开关的材料也是可用的。这些材料应有和纳米管相似的性能,但是有不同可能和更小的拉伸强度。材料的拉伸应变和附着能量必需在一个范围内,能使得结的二稳态性和机电式开关性能是可以接受的。
为了整合CMOS逻辑用来寻址,可以使用两种方法。在第一种方法中,纳米管阵列在在金属化以前,但在CMOS逻辑装置的离子注入和平面化之后进行整合。第二种方法是在CMOS装置制造(涉及离子注入和高温退火)之前生长纳米管阵列。一旦这些步骤完成后,纳米管带子和CMOS装置的金属化就用广泛使用的标准方法进行。
在某种金属或半导体线上放置含n-空穴硅的电极也是可以设想的。这样会在开的状态时产生整流结,以致不存在多重的电流通路。
除整流结以外,还有其它广泛接受和采用的方法,来防止在交叉阵列中电串话现象的发生(也就是多重电流通路的缘故)。在静态的,光刻制成的电极顶部的隧道垫垒能防止形成电阻性“开”的状态。在零偏电压时无漏电流发生,但是需施加一个小的偏电压,使载流子能克服这个垫垒和在交叉线之间的隧道效应。
可以设想采用离子的,共价的或其它力来提高附着能量的方法,改变与电极表面的相互作用。这些方法可用来扩展这些结二稳态性的范围。
纳米管可通过平面共轭的碳氢化合物如芘进行功能化,从而提高带子内纳米管之间的内部附着力。
上述的某些方面,如用于寻址的混合电路和纳米管技术,可用于单根的纳米管(如使用直接生长技术等)或纳米管带子。
本发明的范围并不被上述实施方式所限制,而由所附的权利要求所限定,这些权利要求可以包括对所描述的进行修正和改进。
Claims (34)
1.一种制造机电式电路元件的方法,其特征在于,所述方法包括
提供具有电导轨线和支持的结构,所述支持从基质表面开始延伸;
在支持上提供一层纳米管;
选择性除去纳米管层的某些部分以形成穿过电导轨线的纳米管带子,其中每个带子包括一个或多个纳米管。
2.如权利要求1所述的方法,其特征在于,所述提供一种结构的步骤是提供一种结构,该结构中电导轨线是掺杂的硅轨线。
3.如权利要求1所述的方法,其特征在于,所述提供一种结构的步骤是提供一种结构,该结构中电导轨线是纳米管。
4.如权利要求1所述的方法,其特征在于,所述提供一种结构的步骤是提供一种结构,该结构中电导轨线是纳米管带子。
5.如权利要求1所述的方法,其特征在于,所述提供一种结构的步骤是提供一种结构,该结构中的支持结构的形式是材料的排,且其中的电导轨线基本与排平行。
6.如权利要求5所述的方法,其特征在于,所述轨线与支持是分隔的。
7.如权利要求5所述的方法,其特征在于,所述轨线与支持接触。
8.如权利要求1所述的方法,其特征在于,所述轨线与支持是分隔的。
9.如权利要求1所述的方法,其特征在于,所述轨线与支持接触。
10.如权利要求1所述的方法,其特征在于,所述提供一种结构的步骤是是提供一种结构,该结构中的支持由氮化硅制成。
11.如权利要求1所述的方法,其特征在于,所述提供一种结构的步骤是提供一种结构,该结构中的电导轨线位于绝缘材料层上,使轨线之间相互电绝缘。
12.如权利要求1所述的方法,其特征在于,所述提供一种结构的步骤是提供一种结构,该结构中的电导轨线分别位于绝缘材料上使轨线电绝缘。
13.如权利要求1所述的方法,其特征在于,所述提供纳米管层的步骤是提供纳米管的非织造织物。
14.如权利要求13所述的方法,其特征在于,所述织物生长在结构上。
15.如权利要求13所述的方法,其特征在于,所述结构包括位于轨线上的材料的牺牲层,其中的织物生长在牺牲层上。
16.如权利要求14所述的方法,其特征在于,所述结构用一种催化剂处理,以促进织物生长。
17.如权利要求15所述的方法,其特征在于,牺牲层的上表面用催化剂处理,以促进织物生长。
18.如权利要求1所述的方法,其特征在于,所述选择性除去的步骤包括图案化并腐蚀纳米管层形成带子。
19.如权利要求13所述的方法,其特征在于,所述选择性除去的步骤包括图案化并腐蚀纳米管织物形成带子。
20.如权利要求14所述的方法,其特征在于,所述纳米管的生长在结构表面基本是不受限制的。
21.如权利要求18所述的方法,其特征在于,所述图案化和腐蚀采用能在织物中扩散的腐蚀剂。
22.如权利要求1所述的方法,其特征在于,所述纳米管层基本是单层的。
23.一种机电式电路,其特征在于,所述电路包括:
具有电导轨线和支持的结构,所述支持从基质表面开始延伸;
由穿过电导轨线的支持悬置的纳米管带子,其中各个带子包括一个或多个纳米管。
24.如权利要求23所述的电路,其特征在于,所述电导轨线是掺杂的硅轨线。
25.如权利要求23所述的电路,其特征在于,所述电导轨线是纳米管。
26.如权利要求23所述的方法,其特征在于,所述电导轨线是纳米管带子。
27.如权利要求23所述的方法,其特征在于,所述支持是材料的排,且其中的电导轨线基本与排平行。
28.如权利要求27所述的方法,其特征在于,所述轨线与支持是分隔的。
29.如权利要求27所述的方法,其特征在于,所述轨线与支持接触。
30.如权利要求23所述的方法,其特征在于,所述支持由氮化硅制成。
31.如权利要求23所述的方法,其特征在于,所述电导轨线位于绝缘材料层上,使轨线之间相互电绝缘。
32.如权利要求23所述的方法,其特征在于,所述电导轨线分别位于绝缘材料上,使轨线电绝缘。
33.如权利要求23所述的方法,其特征在于,所述层是纳米管的非织造织物。
34.如权利要求23所述的方法,其特征在于,所述层基本是纳米管单层。
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CN101484997B (zh) * | 2005-05-09 | 2011-05-18 | 南泰若股份有限公司 | 使用具有可重新编程电阻的纳米管制品的存储器阵列 |
CN102027598B (zh) * | 2008-05-16 | 2012-12-26 | 桑迪士克3D有限责任公司 | 碳纳米膜可逆电阻可切换元件及其形成方法 |
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US20100012927A1 (en) | 2010-01-21 |
CA2454834A1 (en) | 2003-03-13 |
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US20080067553A1 (en) | 2008-03-20 |
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JP4505683B2 (ja) | 2010-07-21 |
KR20040035691A (ko) | 2004-04-29 |
WO2003021613A2 (en) | 2003-03-13 |
WO2003021613A3 (en) | 2003-08-28 |
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US20040214366A1 (en) | 2004-10-28 |
JP2005502201A (ja) | 2005-01-20 |
US7719067B2 (en) | 2010-05-18 |
US6919592B2 (en) | 2005-07-19 |
EP1410429A4 (en) | 2007-06-06 |
TW200412685A (en) | 2004-07-16 |
TWI246788B (en) | 2006-01-01 |
AU2002353770A1 (en) | 2003-03-18 |
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US20090087630A1 (en) | 2009-04-02 |
KR100945403B1 (ko) | 2010-03-04 |
US7056758B2 (en) | 2006-06-06 |
EP1410429A2 (en) | 2004-04-21 |
US7511318B2 (en) | 2009-03-31 |
KR20080007682A (ko) | 2008-01-22 |
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