CN1641848A - 用来提高晶体管沟道中的应变效应的方法和设备 - Google Patents
用来提高晶体管沟道中的应变效应的方法和设备 Download PDFInfo
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- CN1641848A CN1641848A CN200510004305.0A CN200510004305A CN1641848A CN 1641848 A CN1641848 A CN 1641848A CN 200510004305 A CN200510004305 A CN 200510004305A CN 1641848 A CN1641848 A CN 1641848A
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- gate stack
- nitride film
- stress
- liner
- substrate
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 230000000694 effects Effects 0.000 title description 5
- 150000004767 nitrides Chemical class 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 239000000654 additive Substances 0.000 claims 1
- 230000000996 additive effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 238000005019 vapor deposition process Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920005591 polysilicon Polymers 0.000 description 24
- 229910021332 silicide Inorganic materials 0.000 description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 14
- 230000006835 compression Effects 0.000 description 6
- 238000007906 compression Methods 0.000 description 6
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- 150000002500 ions Chemical class 0.000 description 6
- 238000012797 qualification Methods 0.000 description 6
- 229910019001 CoSi Inorganic materials 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- JUJWROOIHBZHMG-UHFFFAOYSA-N Pyridine Chemical compound C1=CC=NC=C1 JUJWROOIHBZHMG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
Abstract
Description
Claims (24)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/707,842 | 2004-01-16 | ||
US10/707,842 US7118999B2 (en) | 2004-01-16 | 2004-01-16 | Method and apparatus to increase strain effect in a transistor channel |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1641848A true CN1641848A (zh) | 2005-07-20 |
CN100385635C CN100385635C (zh) | 2008-04-30 |
Family
ID=34749150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100043050A Active CN100385635C (zh) | 2004-01-16 | 2005-01-14 | 用来提高晶体管沟道中的应变效应的方法和设备 |
Country Status (3)
Country | Link |
---|---|
US (3) | US7118999B2 (zh) |
CN (1) | CN100385635C (zh) |
TW (1) | TWI377596B (zh) |
Families Citing this family (26)
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US7118999B2 (en) * | 2004-01-16 | 2006-10-10 | International Business Machines Corporation | Method and apparatus to increase strain effect in a transistor channel |
US7361973B2 (en) * | 2004-05-21 | 2008-04-22 | International Business Machines Corporation | Embedded stressed nitride liners for CMOS performance improvement |
EP1717864A1 (en) * | 2005-04-27 | 2006-11-02 | STMicroelectronics ( Crolles 2) SAS | Method for managing the stress configuration in the channel of a MOS transistor, and corresponding integrated circuit. |
US7262484B2 (en) * | 2005-05-09 | 2007-08-28 | International Business Machines Corporation | Structure and method for performance improvement in vertical bipolar transistors |
US20070013070A1 (en) * | 2005-06-23 | 2007-01-18 | Liang Mong S | Semiconductor devices and methods of manufacture thereof |
US7615432B2 (en) * | 2005-11-02 | 2009-11-10 | Samsung Electronics Co., Ltd. | HDP/PECVD methods of fabricating stress nitride structures for field effect transistors |
US8729635B2 (en) * | 2006-01-18 | 2014-05-20 | Macronix International Co., Ltd. | Semiconductor device having a high stress material layer |
US7410875B2 (en) * | 2006-04-06 | 2008-08-12 | United Microelectronics Corp. | Semiconductor structure and fabrication thereof |
US7361539B2 (en) * | 2006-05-16 | 2008-04-22 | International Business Machines Corporation | Dual stress liner |
US7514370B2 (en) * | 2006-05-19 | 2009-04-07 | International Business Machines Corporation | Compressive nitride film and method of manufacturing thereof |
US20070275530A1 (en) * | 2006-05-24 | 2007-11-29 | Wen-Han Hung | Semiconductor structure and fabricating method thereof |
US7768041B2 (en) * | 2006-06-21 | 2010-08-03 | International Business Machines Corporation | Multiple conduction state devices having differently stressed liners |
WO2008027471A1 (en) * | 2006-08-31 | 2008-03-06 | Advanced Micro Devices, Inc. | A field effect transistor having a stressed contact etch stop layer with reduced conformality |
DE102006040765B4 (de) * | 2006-08-31 | 2011-02-03 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines Feldeffekttransistors mit einer verspannten Kontaktätzstoppschicht mit geringerer Konformität und Feldeffekttransistor |
DE102006040762B4 (de) * | 2006-08-31 | 2009-05-07 | Advanced Micro Devices, Inc., Sunnyvale | N-Kanalfeldeffekttransistor mit einer Kontaktätzstoppschicht in Verbindung mit einer Zwischenschichtdielektrikumsteilschicht mit der gleichen Art an innerer Verspannung |
JP2008140854A (ja) * | 2006-11-30 | 2008-06-19 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US7935588B2 (en) * | 2007-03-06 | 2011-05-03 | International Business Machines Corporation | Enhanced transistor performance by non-conformal stressed layers |
KR20090008568A (ko) * | 2007-07-18 | 2009-01-22 | 주식회사 동부하이텍 | 반도체 소자의 제조방법 |
US7820518B2 (en) * | 2008-05-29 | 2010-10-26 | Infineon Technologies Ag | Transistor fabrication methods and structures thereof |
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DE102009046241B4 (de) * | 2009-10-30 | 2012-12-06 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verformungsverstärkung in Transistoren, die eine eingebettete verformungsinduzierende Halbleiterlegierung besitzen, durch Kantenverrundung an der Oberseite der Gateelektrode |
CN102299154B (zh) * | 2010-06-22 | 2013-06-12 | 中国科学院微电子研究所 | 半导体结构及其制作方法 |
KR101815527B1 (ko) * | 2010-10-07 | 2018-01-05 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
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US8937369B2 (en) * | 2012-10-01 | 2015-01-20 | United Microelectronics Corp. | Transistor with non-uniform stress layer with stress concentrated regions |
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US7205206B2 (en) | 2004-03-03 | 2007-04-17 | International Business Machines Corporation | Method of fabricating mobility enhanced CMOS devices |
US7504693B2 (en) | 2004-04-23 | 2009-03-17 | International Business Machines Corporation | Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering |
US7354806B2 (en) * | 2004-09-17 | 2008-04-08 | International Business Machines Corporation | Semiconductor device structure with active regions having different surface directions and methods |
US7518193B2 (en) | 2006-01-10 | 2009-04-14 | International Business Machines Corporation | SRAM array and analog FET with dual-strain layers comprising relaxed regions |
US7585773B2 (en) | 2006-11-03 | 2009-09-08 | International Business Machines Corporation | Non-conformal stress liner for enhanced MOSFET performance |
-
2004
- 2004-01-16 US US10/707,842 patent/US7118999B2/en not_active Expired - Lifetime
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2005
- 2005-01-03 TW TW094100066A patent/TWI377596B/zh not_active IP Right Cessation
- 2005-01-14 CN CNB2005100043050A patent/CN100385635C/zh active Active
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2006
- 2006-08-18 US US11/465,663 patent/US7790558B2/en active Active
- 2006-08-25 US US11/467,446 patent/US7462915B2/en active Active
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US20050158955A1 (en) | 2005-07-21 |
TW200534348A (en) | 2005-10-16 |
US7462915B2 (en) | 2008-12-09 |
US20060286786A1 (en) | 2006-12-21 |
US7790558B2 (en) | 2010-09-07 |
US20060281272A1 (en) | 2006-12-14 |
CN100385635C (zh) | 2008-04-30 |
TWI377596B (en) | 2012-11-21 |
US7118999B2 (en) | 2006-10-10 |
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