CN1695251A - 具有伸入较深的以沟槽为基础的源电极的以沟槽为基础的交叉栅电极的垂直mosfet及其制造方法 - Google Patents

具有伸入较深的以沟槽为基础的源电极的以沟槽为基础的交叉栅电极的垂直mosfet及其制造方法 Download PDF

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CN1695251A
CN1695251A CNA02827542XA CN02827542A CN1695251A CN 1695251 A CN1695251 A CN 1695251A CN A02827542X A CNA02827542X A CN A02827542XA CN 02827542 A CN02827542 A CN 02827542A CN 1695251 A CN1695251 A CN 1695251A
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groove
source
source electrode
base region
vertical mosfet
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B·J·巴利加
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Silicon Wireless Corp
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Abstract

垂直MOSFET包括一个半导体衬底，其中有一些半导体台面，它们被许多深条形沟槽分开。这些条形沟槽沿纵向沿第一方向平行伸过衬底。在这些深条形沟槽内形成一些埋入式绝缘源电极。还提供一些绝缘栅电极，它们平行伸过那些半导体台面并伸入在这些埋入式绝缘源电极内的浅沟槽中。在衬底上做了一个表面源电极。此表面源电极在沿每个埋入式绝缘源电极长度上的多个位置处与每个埋入式绝缘源电极电气连接，这些多处连接降低了有效的源电极电阻并增大了器件的开关速度。

Description

具有伸入较深的以沟槽为基础的源电极的 以沟槽为基础的交叉栅电极的垂直MOSFET及其制造方法
发明领域
本发明涉及半导体开关器件，更具体地说，是关于高功率应用的开关器件及其制造方法。
发明背景
硅双极晶体管已被选作高功率应用的器件，如在汽车驱动电路、电器控制、机器人和灯光整流器等应用中。这是因为双极晶体管可做到能用于40-50A/cm2范围的较大电流密度并支持500-1000V范围的较高阻断电压。
虽然双极晶体管能达到的额定功率很有吸引力，但将它们用于所有的高功率应用还存在几个基本缺陷。首先，双极晶体管是电流控制器件，需要比较大的基极电流(典型为集电极电流的1/5至1/10)以维持晶体管的工作模式。对于还要求高速关断的应用，基极电流更要大些。由于要求比较大的基极电流，用于控制通断的基极驱动电路比较复杂和昂贵。若大电流和高电压同时加在一个器件上(一般在感应式功率电路中有此要求)，双极晶体管还容易由于过早损坏。此外，比较难让双极晶体管并联运行，因为电流转向单个晶体管通常发生在高温下，故发射极必需有镇流措施。
硅功率金属氧化物半导体场效应晶体管(MOSFET)是为解决这个基极驱动问题而开发的。在功率MOSFET中，栅电极加上适当的栅偏压就可提供通断控制。例如，在N型增强模式MOSFET中，当加上正栅偏压时，在P型基极区(也叫“沟道区”)形成一个导电性N型转换层沟道，从而使其接通。此转换层沟道电连接N型源极和漏极区，使多数载流子在其间导通。
功率MOSFET的栅电极通过一个中间绝缘层(典型为二氧化硅)与基极区分开。由于栅电极与基极区隔离开，如果需要栅极电流也只需一小的值就能将MOSFET维持在导通状态或将MOSFET从接通状态转变为关断状态或者相反。在转换过程中栅极电流保持很小，因为栅和MOSFET的基极区构成一个电容器。因此在转换过程中只需要充放电(“位移”)电流。由于与绝缘栅电极相关的输入阻抗很高，加在栅极上的电流极小，同时栅极驱动电路很容易实现。此外，因为在MOSFET中的电流导通只通过多数载流子输运而发生，故不存在与过剩多数载流子的复合和贮存有关的延迟。因而，功率MOSFET的开关速度可做到比双极晶体管快几个数量级。与双极晶体管不同，功率MOSFET可设计成在较长时间内承受高的电流密度和加上高电压，而不会发生被称为“二次击穿”的破坏性失效机制。还可以容易地把功率MOSFET并联起来，因为在功率MOSFET上的正向电压降随着温度的增加而增加，从而有助于将各并联器件内的电流分布均匀化。
考虑到这些所希望的特性，已设计出许多功率MOSFET的变型。两种普通的类型为双扩散MOSFET器件(DMOSFET)和UMOSFET器件。B.J.Baliga的教科书“功率半导体器件”(ISBN0-534-94098-6，PWS出版公司，1995)对这些和其它的功率MOSFET作了描述，其内容被引用到这里作参考。此教科书的第七章在335-425页描述了功率MOSFET。硅功率MOSFET的例子(包括具有延伸至N+漏极区的沟道栅电极的累计，转换和延伸沟道FET)在T.Syau，P.Venkatraman和B.J.Baliga的文章中已有描述：“Comparison of Ultralow Specific On-ResistanceUMOSFET Structure：The ACCUFET，EXTFET，INVFET，and conventionalUMOSFETs“，IEEE Transactions on Electron Devices，Vol.41，No.5，May(1994)。如Syau等人所述，实验已证明比电阻在100-250μΩcm2范围内的器件能支持最大25V的电压。不过这些器件的性能受到下面事实的限制：正向阻断电压必须由在沟道底部的栅极氧化物来承受。
图1取自上述Syau等人文章中的图1(d)，表示一个普通UMOSFET结构。在阻断工作模式中，这个UMOSFET承受N型漂移层上大部分正向阻断电压，此漂移层必须是掺杂水平较低的以获得最大的阻断电压能力。但低掺杂水平一般会增大接通状态的串联电阻。基于这些高阻断电压和低接通态电阻的竞争性设计要求，已推导出一种功率器件的基本优化数字，它把比电阻(Ron，sp)与最大阻断电压(BV)联系起来。如上述Baliga的教科书373页所述，N型硅漂移区的理想比电阻由下式给定：
     Ron.sp＝5.93×10-9(BV)2.5…………………(1)
因此，一个具有60V最大阻断电压的器件，其理想比电阻为170μΩcm2。然而，由于基极区(如N沟槽型MOSFET中的P型基极区)对电阻的额外贡献，已发表的UMOSFET的比电阻一般要高得多。例如，H.Chang在一篇文章中已发布了一种具有730μΩcm2比电阻的UMOSFET，该文的题目是“Numerical and Experimental Comparison of60V Vertical Double-Diffused MOSFETs and MOSFETs with ATrench-Gate Structure”，发表于Solid-State Electronics，Vol.32，No.3，pp.247-251(1989)。但是在这个器件中，要求在漂移区用比理想值低的均匀掺杂浓度，以补偿在阻断高的正向电压时沟槽底角落附近高度集中的场线。美国专利5.637.989，5.742.076和5.912.497也发布了具有垂直电流携带能力的普通功率半导体器件，这几个专利都被引用到这里作为参考。
其中颁发给Baliga的美国专利5.637.989发布了一种优选的硅场效应晶体管，一般把它称为分级式掺杂(GD)UMOSFET。如图2所示(该图是从.898号专利的图3复制的)，一个集成式功率半导体器件场效应晶体管(FET)的单元100可能有1μm的宽度“WC”，并包含第一导电型(如N+)衬底的一个高度掺杂漏极层114，第一导电型的一个漂移层112(其中有线性分级式掺杂浓度)，一个第二导电型(如P-型)的比较薄的基极层116，和一个第一导电型(如N+)高度掺杂源极层118。此漂移层112可通过在N型漏极层114(厚度为100μm，掺杂浓度大于1×1018cm-3(如1×1019cm-3))上外延生长一个N型原地掺杂单晶硅层(厚度为4μm)而形成。漂移区112也具有一个线性分级式掺杂浓度，在带漏极层114的N+/N结处的最大浓度为3×1017cm-3，且在离N+/N结3μm(即在1μm的深度处)开始的最大浓度为1×1016cm-3，并延续至上表面保持均匀水平，基极层116可将一种P型掺杂物(如硼)注入漂移层112而形成，注入能量100keV，剂量为1×1014cm-2。然后P型掺杂物可能扩散0.5μm的深度进入漂移层112。也可以用50keV能量和1×1015cm-2剂量将砷等N型掺杂物注入。然后N型和P型掺杂物同时分别扩散0.5μm和1.0μm的深度，以形成一个包含漏极层、漂移层、基极层和源极层的复合半导体衬底。
然后在衬底内形成一个条形沟槽，它具有一对沿第三方向(未示)伸展的相对壁120a和一个底部120b。对于一个宽度为1μm的单元100，最好做成在加工末了具有宽度“Wt”为0.5μm。接着在沟槽内形成一个绝缘栅电极，它包含一个栅绝缘区124和一个导电栅极126(例如，多晶硅)。伸到沟槽底120b和漂移层112附近的那部分栅极绝缘区可能有2000左右的厚度“T1”，以防止在沟槽底部出现高电场，并沿沟槽侧壁120a提供基本均匀的电位梯度。伸到基极层116和源极层118对面的那部分栅极绝缘区124可能有500左右的厚度“T2”，以维持器件的阈值电压在2-3V左右。对一个栅偏压15V的单元100的模拟计算证实，可以实现一种垂直硅场效应晶体管，其最大阻断电压能力为60V，比电阻(Rsp.on)为40μΩcm2，后者是一个60V功率MOSFET的理想比电阻(170μΩcm2)的1/4。尽管这些特性极其优秀，图2的晶体管在栅极-漏极总电容(CGD)过大时的高频优质数字(HFOM)却比较低。MOSFET的边缘终止得不适当也可能达不到最大的阻断电压。
1988年12月12日Sony公司发布的日本专利JP63-296282中也披露了另一些以前的MOSFET。其中特别介绍了一种MOSFET，它在沟槽中建立了第一和第二栅电极，并在其间有一个栅极绝缘膜。颁发给Baba等人的美国专利5578508介绍了一种垂直功率MOSFET，它利用一个埋在沟槽内的多晶硅层作为离子注入掩模层，以防止沟道离子注入时离子被注入沟槽中。颁发给Tsang等人的美国专利介绍了一种具有凹陷栅电极的垂直MOSFET。颁发给Temple的美国专利4,941,026介绍了一种垂直沟道半导体器件，它包含一个绝缘栅电极，处在电压承受区的主要部分附近。加上适当的偏压时，控制电极即与电压承受区内的电荷发出的电场相耦合，将与这些电荷相关的电场拉向栅电极并横切流过该器件电流的方向。
颁发给Baliga的美国专利5,998,833和6,388,286介绍了另一些垂直MOSFET，带有以沟槽为基础的栅极和源电极。例如，图3(取自美国专利5,998,833的图3)表示集成式功率半导体器件的一个单元200。此器件包含一个高度掺杂的第一导电型(如N+)漏极层114，一个具有线性分级式掺杂浓度的第一导电型漂移层112，一个比较薄的第二导电型(如P型)基极层116，和一个高度掺杂的第一导电型(如N+)源极层118。在第一和第二面还提供一个源电极128b和一个漏电极130。漂移层112中的掺杂浓度可以是线性分级式。在衬底内提供一个条形沟槽，它有一对相对的侧壁120a和一个底部120b。在沟槽内还形成一个栅极/源极绝缘区125，一个栅电极127(如多晶硅)，和一个以沟槽为基础的源电极128a(如多晶硅)。
虽然已有这些研发功率半导体器件的尝试，使它们能在高速下开关，并具有很高的最大阻断电压能力和低比电阻，但仍有需要开发具有改进电特性的功率器件。
发明概要
按本发明一些实施例的垂直MOSFET包含一个半导体衬底，它具有一个第一导电型漂移区，及第一和第二沟槽，这些沟槽沿纵向沿第一方向伸至衬底内。在第一和第二沟槽之间有一个半导体台面，漂移区就伸至台面内。第一和第二埋入式绝缘源极分别伸至第一和第二沟槽的底部附近。还提供了第一和第二个空间隔开的绝缘栅电极。这些栅电极不沿纵向方向伸至各自的沟槽中，而是沿纵向方向按照一个第二方向延伸并与台面重叠。每个栅电极还伸至第一埋入式绝缘源极的一个相应的浅沟槽内和第二埋入式绝缘源极的一个相应的浅沟槽内。第一和第二方向可能是相互垂直的。
形成这些优选垂直MOSFET的方法可能包括在半导体衬底内形成一个第二导电型基极区，此衬底内有一个第一导电型漂移区，后者与基极区构成一个P-N结。在基极区内也形成一个第一导电型源极区。还有一个步骤是在半导体衬底内作出一个深沟槽，它有一个第一侧壁伸至基极区附近。然后将沿深沟槽以第一电绝缘层行程分界。接着用一个以沟槽为基础的源极填充有分界的深沟槽。再对以沟槽为基础的源极进行选择性蚀刻，以在其中形成一些浅沟槽，它们沿着以沟槽为基础的源极长度在空间上是隔开的。在这些浅沟槽的每一个中，让伸至深沟槽第一侧壁上的第一绝缘层的相关第一部分暴露。然后进行另一次蚀刻，除掉已暴露的第一电绝缘层的第一部分，并沿以沟槽为基础的源极的长度方向在多个位置让基极区暴露。然后在已暴露的浅沟槽内的那部分基极区上进行热氧化处理。此热氧化步骤导致在已暴露的基极区部分上形成栅极氧化层。然后在衬底表面上形成一些绝缘的栅电极。每个绝缘栅电极伸过台面进入每个以沟槽为基础的源电极内的相应浅沟槽内。还提供了一个表面源电极，它把以沟槽为基础的源极、源极区和基极区电气上连在一起。
附图简介
图1是一个现有技术的功率器件的剖视图。
图2是另一个现有技术的功率半导体器件和其中的掺杂截面剖视图。
图3是按现有技术的一个集成式功率半导体器件及其中的掺杂截面的剖视图。
图4是按本发明一个实施例的垂直MOSFET的透视图。
图5A-5H是各种中间结构的透视图，它说明按本发明其它一些实施例的形成垂直MOSFET的方法。
优选实施例的描述
现在将参照各附图(其中显示本发明的一些优选实施例)对本发明作较详细的描述。但是，本发明可以用不同的形式实现，故不应认为只限于这里所列举的那些实施例。相反，所提供的实施例是为了使本发明更详尽和完整，并把本发明的范围全部传达给本领域技术人员。为清楚起见各图中各层和区域的厚度都被放大了。还应指出，当说到一层是在另一层或衬底之上时，该层可以是直接处在另一层或衬底上面，或者也可以存在一个中间层。另外，“第一导电型”和“第二导电型”两个术语表示相反的导电类型，如N或P型，但这里所描述和展示的每一个实施例也包括它的辅助实施例。各图中相似的数字表示类似的元件。
现在来看图4和5A-5H，按本发明另一个实施例的一个优选垂直MOSFET包括一个半导体衬底，其中具有一些半导体台面504a，它们被一些沿纵向沿第一方向平行伸过衬底的深条形沟槽所隔开。在那些条形沟槽内提供了一些埋入式绝缘源电极516。还提供了一些绝缘的栅电极520。栅电极520平行伸过那些半导体台面504a并进入处于那些埋入式绝缘源电极516内的浅沟槽中。还提供了一些表面源电极524。此表面源电极524伸到半导体台面504a上并与埋入式绝缘源电极516电气上相连。绝缘栅电极520最好是条形电极，它们沿纵向沿与第一方向正交的第二方向伸过台面504a。
形成图4的垂直MOSFET500的优选方法示于图5A-5H。特别在图5A-5H中的每一个图给出了按本发明各实施例的一个垂直MOSFET的半个单元在各中间加工阶段的右侧透视图和左侧透视图。如图5A所示，所提供的半导体衬底502中有一个第一导电型(图中所示为N型)漂移区504。此漂移区504内可能有均匀的或不均匀的掺杂浓度分布。也可以采用其它的掺杂浓度分布。半导体衬底502可以有上、下相对的表面，且在衬底502下表面附近可提供一个高度掺杂的漏极区506(图示为N+)。本专业技术人员知道，半导体衬底502可通过在高度掺杂的半导体晶片(用作漏极区506)的上表面上外延生长一个原地掺杂漂移区504而形成。
现在来看图5B，在衬底502的上表面上可形成一个第一掩模(未示)。此第一掩模最好作成图形使其中有一个第一开口，由它限定衬底502的工作区。然后将第二导电型基极区掺杂物通过第一开口注入衬底502内。在基极区掺杂物被注入后，可进行较短时间的退火处理，以将已注入基极区的掺杂物部分推入。换一种方式，可以对第一掩模作图形以限定衬底502的非工作部分，然后进行衬底502非工作部分的热氧化处理，在它上面限定一个场氧化物隔离区。接着将第一掩模移开使衬底502的工作部分暴露。然后利用场氧化物隔离区作为基极区注入掩模。
然后可将一个第二掩模(未示)淀积在衬底502的工作部分上。在第二掩模内做一些开口，每个开口使衬底502工作部分上的一个相关区外露，通过此区把第一导电型源极区掺杂物注入。这些开口可以是一些矩形开口，每个开口的宽度是沿着第一方向伸过衬底502，长度是沿着与第一方向正交的第二方向伸过衬底502。在图5A-5H中，第一方向可以是自前至后横跨所示半个单元，第二方向可以是自左至右。
然后进行另一次退火处理，以同时把注入的源极区掺杂物和基极区掺杂物推进到它们在衬底502内的几乎整个也是最后的深度。在这次退火处理完成以后，一些条形源极区510可沿纵向按第二方向平行伸过一个单基极区508。为了抑制所得垂直MOSFET中的寄生双极晶体管效应，每个源极区条510在第一方向的宽度应小于10μm左右。为使沟道的宽度尽可能大，相邻源极区510间在第一方向的间隔“Wbc”可设置为大约1μm以下。
现在参看图5c，在衬底502的工作部分上形成一个第三掩模(未示)，此第三掩模的图形是带分隔的矩形开口，其长度沿第一方向伸展。然后利用第三掩模进行选择性蚀刻处理，以在衬底502内造成一些深条形沟槽513，每对相邻的深沟槽之间限定一个漂移区台面504a，漂移区504就伸到此台面之内。如图所示，深条形沟槽513和漂移区台面504a沿纵向沿第一方向伸过衬底502。然后在衬底502上共形淀积一个覆盖电绝缘层514。如图所示，该覆盖电绝缘层514伸到每个沟槽513中并沿每个沟槽的侧壁513a和底部513b形成分界。这个电绝缘层514可包括二氧化硅或其它更好的介质绝缘材料构成。接着将一个覆盖导电层(如N+多晶硅)共形淀积在衬底502上及沟槽513内。然后将此导电层平面化(例如，往回蚀刻)以造成一些以沟槽为基础的源电极516，它们的长度是沿着沟槽513的第一方向伸展。这些以沟槽为基础的源电极516通过沿沟槽513形成分界的电绝缘层514与衬底502电绝缘，并因此而构成埋入式绝缘源电极。
现在参看图5D，这时可以把第四掩模(未示)淀积和作图，以沿每个沟槽513的长度提供一些相隔一定位置的开口。然后进行另一次选择性蚀刻处理，利用第四掩模作为蚀刻掩模在每个埋入式绝缘源电极516内造成一些浅沟槽515。如图所示，作这些浅沟槽515时使电绝缘层514的上部(它们沿沟槽513的侧壁513a形成分界)暴露。接下去进行另一次选择性蚀刻处理，以除掉已暴露的电绝缘层514的上部。这个选择性蚀刻处理(它利用以沟槽为基础的源电极516作为蚀刻掩模)使得部分源极区510和基极区508(它们延伸至已暴露的上侧壁513a附近)暴露。如图5E所示，这时可进行一次热氧化处理，使已暴露的基极和源极区(在已暴露的侧壁513a上)上形成一个栅极氧化物层518a，并沿每个埋入式绝缘源电极516的浅沟槽515的底部和侧壁形成一个栅极-源极绝缘层518b。与衬底(典型为单晶硅)和以沟槽为基础的源电极516(典型为多晶硅)相关的不同材料特性可能使得栅极-源极绝缘层518b比栅极氧化物层518a要厚得多。虽然不一定需要，但还是可以这样来选择以沟槽为基础的源电极516的材料特性，使得以沟槽为基础的源电极516以比衬底较高的速度热氧化。例如，一个产生约40nm(400)厚度栅极-源极氧化层518a的热氧化处理也可以获得厚度约500nm(400)的栅极-源极氧化层518b。
现在参看图5F，这时将一个覆盖栅极导电层(如多酸)淀积并作成一些平行条状栅电极520，后者沿纵向沿第二方向(图示为垂直第一方向)伸过漂移区台面504a和深沟槽513。此作图步骤可利用第五掩模(未示)来进行。每个条形栅电极520沿第二方向伸过一些漂移区台面504a并伸进每个埋入式绝缘源电极516内的相应浅沟槽515内。栅电极520也可以按之字形或其它图形作图，且在栅电极520长度方向和以沟槽为基础的源电极516的长度方向之间的锐角可能在45°-90°左右的范围。
然后可把一个覆盖电绝缘钝化层522淀积在衬底502上，如图5G所示。接着利用第六掩模(未示)在选择性蚀刻处理过程中使源极区510、基极区508和伸展在相邻绝缘栅电极520之间的以沟槽为基础的源电极516的相应部分暴露。现在参看图5H，这里将一个金属化覆盖层共形淀积在衬底上及源极区508、基极区510和埋入式绝缘源电极516的已暴露部分上。然后利用第七掩模(未示)对此金属覆盖层作图以形成一个表面源电极524，它与每个源极区508欧姆接触，还与基极区510和埋入式绝缘源电极516沿着第一方向在多个位置欧姆接触。在每个埋入式绝缘源电极和表面源电极504之间的这些多个触点使有效源电极电阻降低并使开关速度得到改善，因为此电阻是在与跨接在每个栅电极520和相应埋入式绝缘源电极516之间的MOS电容器有关的位移电流路径上。
对图5H的垂直MOSFET进行了二维数字模拟。对每个单元，深沟槽513的深度和宽度分别为5μm和1.8μm，且沿深沟槽513的侧壁513a和底部513b形成分界的电绝缘层514的厚度为350nm(3500)。漂移区504的厚度为6μm。在每个埋入式绝缘源电极516内的浅沟槽515的深度为0.5μm，栅极氧化物518a的厚度为40nm(400)。漂移区504内的线性分级式掺杂截面的斜率为1.5×1020cm-4，漂移区台面504a的宽度为1μm。因而，与每个单元相关的晶格节距为2.8μm。源电极516和栅电极520分别为多晶硅和多酸。根据这些特性，模拟出的击穿电压为85V，通路比电阻(Rsp)低至0.25mΩcm2。比栅极电荷Qt(当Vg＝10V时)为4.93×10-7C/cm2，比米勒栅极电荷为8.6×10-8C/cm2。与这些结果相应的优质数字(FOM)为8.3×109(即RspXQt-1＝8.3×109)。与此相反，对图1的MOSFET采用同样的参数(但是没有埋入式绝缘源电极)模拟得到85V的击穿电压和高得多的通路比电阻(Rsp)1.2mΩcm2。相应的比栅极电荷Qt(当Vg＝10V)为3.0×10-7C/cm2，比米勒栅极电荷为1.0×10-8C/cm2。与这些结果相应的优化数字(FOM)为2.8×109，即为图5H器件的FOM的1/3左右。
以附图和说明介绍了本发明的典型优选实施例，虽然是针对特定的条件，但它们仅仅是用作一般的描述性质而并不表明只限于此，本发明的范围将由下面的权利要求书限定。

Claims (32)

1.一种垂直MOSFET，包括：
半导体衬底，其中有一些半导体台面由一些深条形沟槽隔开，这些沟槽沿纵向按第一方向平行伸过该衬底；
一些处在条形沟槽内的埋入式绝缘源电极；及
一些绝缘栅电极，平行伸过那些半导体台面以及形成在所述埋入式绝缘源电极内的浅沟槽。
2.如权利要求1的垂直MOSFET，其中每个半导体台面包含至少一个基极区，它支持沿着相应一对深条形沟槽相对侧壁的垂直转换层沟道。
3.如权利要求2的垂直MOSFET，还包含在该半导体衬底上延伸的表面源电极，它与上述埋入式绝缘源电极电气相连且与每个半导体台面的至少一个基极区欧姆接触。
4.如权利要求3的垂直MOSFET，其中表面源电极和基极区的欧姆接触形成于那些半导体台面的上表面上。
5.如权利要求1的垂直MOSFET，其中的绝缘栅电极为条形电极，它们沿纵向沿着与第一方向正交的第二方向伸过半导体衬底。
6.一种垂直MOSFET，包括：
半导体衬底，其中有第一导电型漂移区；
第一和第二沟槽，它们沿纵向沿第一方向在衬底内延伸，并在其间形成一个半导体台面，漂移区就伸入该台面内；
第一和第二埋入式绝缘源电极，它们沿纵向沿着第一方向分别伸向该第一和第二沟槽的相邻底部；及
第一和第二空间相隔的栅电极，其中每一个沿纵向沿第二方向伸过台面并伸到第一和第二沟槽的上面部分内。
7.如权利要求6的垂直MOSFET，其中第一和第二栅电极在第一沟槽的上面部分是彼此并排的；且其中每一埋入式绝缘源电极从第一沟槽底部附近向上伸入第一和第二栅电极之间的空间。
8.如权利要求7的垂直MOSFET，其中第一导电型的第一源极区和第二导电型的第二基极区从第一沟槽的一个侧壁至第二沟槽的一个相对侧壁横向伸过台面的一个宽度。
9.如权利要求8的垂直MOSFET，还包括一表面源电极，它与处于第一和第二栅电极之间的空间内第一和第二埋入式绝缘源电极欧姆接触。
10.如权利要求9的垂直MOSFET，其中第一源极区和第一基极区伸到处于第一和第二栅电极之间空间内的一台面表面；且其中表面源电极在台面表面处与第一源极区和第一基极区欧姆接触。
11.如权利要求6的垂直MOSFET，其中第一和第二方向彼此正交。
12.一种垂直MOSFET，包括：
半导体衬底，它具有第一导电型的漂移区；
第一和第二沟槽，它们沿纵向沿第一方向在衬底内延伸，并在其间形成一第一台面，该漂移区延伸到该台面中；
第三沟槽，它沿纵向沿第一方向伸入衬底内，并形成第二和第三沟槽之间延伸的第二半导体台面；
第一、第二和第三绝缘区，它们分别沿第一、第二和第三沟槽的底部和侧壁形成分界；
第一、第二和第三埋入式绝缘源电极，它们分别沿纵向在第一、第二和第三沟槽内延伸；及
第一绝缘栅电极，它沿纵向沿着与第一方向正交的第二方向伸过第一和第二台面并延伸进入第二沟槽。
13.如权利要求12的垂直MOSFET，还包括第二绝缘栅电极，它与第一绝缘栅电极隔开并沿纵向沿第二方向伸过第一和第二台面并伸入第二沟槽。
14.如权利要求13的垂直MOSFET，还包括第一导电型的第一和第二空间隔开的源极区，它们延伸入第二台面内并分别与第一和第二绝缘栅电极相对。
15.如权利要求14的垂直MOSFET，还包括表面源电极，它与处于第一和第二绝缘栅电极之间的空间内的第一和第二源极区欧姆接触。
16.如权利要求15的垂直MOSFET，还包括第二导电型的基极区，它沿纵向沿第一方向伸到第二台面内，并与处于第一和第二绝缘栅电极之间的空间内的表面源电极欧姆接触。
17.如权利要求16的垂直MOSFET，其中第一和第二源极区伸入基极区并与之形成相应的P-N结，结的长度小于10μm。
18.如权利要求17的垂直MOSFET，其中第一和第二源极区的相对两端彼此相隔约2μm以下的距离。
19.一种垂直MOSFET，包括：
半导体衬底，其内有一些半导体台面，这些台面被一些沿纵向沿第一方向平行伸过该半导体衬底的深条形沟槽隔开，每个半导体台面中至少有一个基极区和至少一个源极区；
一些伸入那些深条形沟槽内的埋入式绝缘源电极，其中第一埋入式绝缘源电极有一些浅沟槽，浅沟槽安排在沿第一深条形沟槽长度上的一些相隔位置上；及
一些绝缘栅电极，它们沿着与第一方向成一个非零角度的第二方向平行伸过那些半导体台面，其中每一个所述绝缘栅电极伸到槽位于第一埋入式绝缘源电极内的相应浅沟足够深，使得当垂直MOSFET加上偏压工作在正向接通模式时，在第一深条形沟槽附近延伸的第一半导体台面内的相应基极区中建立至少一个相应的垂直转换层沟道。
20.如权利要求19的垂直MOSFET，其中所述绝缘栅电极为之字形。
21.如权利要求19的垂直MOSFET，其中非零角度约为90°。
22.如权利要求19的垂直MOSFET，还包括一个表面源电极，它与那些埋入式绝缘源电极电气相连，并与第一半导体台面内的基极区欧姆接触。
23.一种垂直MOSFET，包括：
半导体衬底，其中有一些半导体台面，它们被一些沿纵向沿第一方向平行伸过该半导体衬底的深条形沟槽隔开，每个半导体台面包括一漂移区，一在漂移区上的过渡区，一在过渡区上的基极区，和一在基极区上的源极区；
一些伸入那些深条形沟槽内的埋入式绝缘源电极，其中所述第一埋入式绝缘源电极有一些浅沟槽，所述浅沟槽安排在沿第一深条形沟槽长度上的一些相隔位置上；及
一些绝缘栅电极，它们沿着与第一方向成一个非零角度的第二方向平行伸过那些半导体台面，其中每一个绝缘栅电极伸到位于第一埋入式绝缘源电极内的相应浅沟槽足够深，使得当垂直MOSFET加上偏压工作在正向接通模式时，在第一深条形沟槽附近延伸的第一半导体台面内的相应基极区中至少建立一相应的垂直转换层沟道。
24.一种形成垂直MOSFET的方法，包括以下各步骤：
在半导体衬底内形成一第二导电型基极区，此衬底中有一第一导电型漂移区，它与基极区构成P-N结；
在基极区形成一第一导电型源极区；
在半导体衬底内形成一深沟槽，它有一在基极区附近延伸的第一侧壁；
用电绝缘层沿深沟槽形成分界；
用一以沟槽为基础的源电极重新填充此有分界的深沟槽；
选择性蚀刻以沟槽为基础的源电极以在其中形成一浅沟槽，并将在深沟槽第一侧壁上延伸的第一电绝缘层的第一部分暴露；
选择性蚀刻该第一电绝缘层第一部分，以使深沟槽第一侧壁的上部暴露并让基极区显露出来；
用栅绝缘层沿浅沟槽形成分界，此栅绝缘层在深沟槽第一侧壁已暴露的上部上延伸，和浅沟槽的底部和侧壁；
形成栅电极，该栅电极在半导体衬底的表面上延伸并伸入有分界的浅沟槽内；及
形成表面源电极，它与以沟槽为基础的源电极、源极区和基极区电气上连在一起。
25.如权利要求24的方法，其中形成表面源电极的步骤之前进行以下步骤：
在半导体衬底上形成一个覆盖钝化层；
对此覆盖钝化层作图以在其中形成接触孔，使以沟槽为基础的源电极、源极区和基极区暴露。
26.如权利要求24的方法，其中以沟槽为基础的源电极由多晶硅形成；且其中沿浅沟槽形成分界的步骤包括以第一速度热氧化第一侧壁的已暴露上部，以高于第一速度的第二速度热氧化浅沟槽的底部和侧壁。
27.如权利要求26的方法，其中热氧化步骤包括热氧化以沟槽为基础的源电极的上表面，以在其上形成一表面氧化层；且其中形成表面源电极的步骤之前进行以下步骤：选择性蚀刻在栅电极附近延伸的表面氧化层的一部分，以使以沟槽为基础的源电极上表面的一部分暴露。
28.如权利要求24的方法，其中沿浅沟槽形成分界的步骤包括以第一速度热氧化第一侧壁的已暴露部分，并以至少大致等于第一速度的第二速度热氧化浅沟槽的底部和侧壁。
29.一种形成垂直MOSFET的方法，包括以下步骤：
形成半导体衬底，其中有一漂移区、在漂移区上的一过渡区、在过渡区上的一基极区和在基极区上的一个源极区；
在半导体衬底内形成一深沟槽，深沟槽有一第一侧壁在基极区、过渡区和漂移区附近延伸；
在深沟槽内形成一以沟槽为基础的源电极；
在该以沟槽为基础的源电极内形成一个浅沟槽，使沿第一侧壁伸展的基极区和源极区暴露；
在已暴露的基极区形成一栅极氧化物绝缘层；
形成一栅电极，它在半导体衬底的上表面上延伸并延伸入浅沟槽内；并
形成一表面源电极，它与以沟槽为基础的源电极、源极区和基极区电气连接在一起。
30.如权利要求28的方法，其中形成表面源电极的步骤之前进行以下步骤：
在半导体衬底上形成一覆盖钝化层；及
对此覆盖钝化层作图从而使其中形成一些接触孔，以使以沟槽为基础的源电极、源极区和基极区暴露。
31.如权利要求29的方法，其中形成栅电极的步骤包括形成多个条形栅电极，栅电极沿与深沟槽长度方向垂直的方向伸过以沟槽为基础的源电极；且其中表面源电极在跨于多个条形栅电极之间的一些位置与以沟槽为基础的源电极、源极区和基极区电气相连。
32.如权利要求29的方法，其中以沟槽为基础的源电极通过第一电绝缘层与第一侧壁分开；且其中形成浅沟槽的步骤包括利用以沟槽为基础的源电极作为蚀刻掩模，选择性蚀刻已被浅沟槽暴露的第一电绝缘层的一部分。
CNA02827542XA 2001-11-26 2002-11-19 具有伸入较深的以沟槽为基础的源电极的以沟槽为基础的交叉栅电极的垂直mosfet及其制造方法 Pending CN1695251A (zh)

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CN102184952A (zh) * 2010-02-23 2011-09-14 成都芯源系统有限公司 一种垂直电容耗尽型功率器件及制作方法
CN103904119A (zh) * 2014-03-28 2014-07-02 中国科学院微电子研究所 一种具有纵向屏蔽栅的Trench MOSFET及其加工方法
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US20020036319A1 (en) 2002-03-28
WO2003046996A1 (en) 2003-06-05
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