CN1703757A - 用于减小相邻存储器单元排的存储元件之间的耦合效应的技术 - Google Patents
用于减小相邻存储器单元排的存储元件之间的耦合效应的技术 Download PDFInfo
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Abstract
本发明揭示用于减少因各单元之间的电容耦合而引起存储于若干存储器单元排中的视在电荷电平的错误读数的技术。首先，对一第一排的所有页面进行第一遍编程，随后对一第二相邻排的所有页面进行第一遍编程，此后对该第一排进行第二遍编程，然后对一第三排的所有页面进行第一遍编程，随后返回来对该第二排进行第二遍编程，在一阵列中的各排之间以一来回方式依此类推。此会使因后续向相邻的存储器单元排写入数据而可能对存储于存储器单元排上的视在电荷造成的影响最小化。
Description
技术领域
本发明大体而言涉及数据存储器领域，更具体而言，涉及将数据存储为电子电荷电平的类型的存储器，包括(但不限于)利用导电性浮动栅极或介电材料作为电荷存储元件的闪速电可擦可编程只读存储器(闪速EEPROM)。
背景技术
在当前的市售产品中，一闪速EEPROM阵列中的每一存储元件通常以二元模式工作来存储一单个数据位，在二元模式中，是将存储元件晶体管的两个阈电平范围界定为存储电平。晶体管的阈电平等于存储在其存储元件上的电荷电平的范围。在目前的趋势中，除缩小存储器阵列的尺寸外，还通过在每一存储元件晶体管中存储多于一个数据位来进一步提高此等存储器阵列的数据存储密度。这通过针对每一存储元件晶体管界定多于两个阈电平作为存储状态来实现，目前在市售产品中是包含四个此种状态(每一存储元件2个数据位)。亦设想了更多的存储状态，例如每一存储元件16种状态(4个数据位)。每一存储元件存储器晶体管均具有一可在其中实际操作该晶体管的特定的阈电压总范围(窗口)，该范围被划分成界定用于该晶体管的数个状态，状态中间加有各状态间的裕量，以使这些状态能够明显地相互区别。
随着每一存储器单元中所存储状态数量的增加，存储元件上所编程的电荷电平的任何偏移的容差在减小。由于随着每一存储器单元存储元件上所存储状态数量的增加，为每一存储状态所指定的电荷范围必定会变窄且更近地靠在一起，因而必须以提高的精确度来进行编程，且可容许的所存储电荷电平在编程后的偏移程度，无论是实际偏移还是视在偏移，均会降低。在对一单元进行编程及读取时，及在对与该单元存在一定程度电耦合的其他单元(例如那些处于同一列或排中的单元，及那些共享一线或节点的单元)进行读取、编程及擦除时，可能会造成对存储在该单元中的电荷的实际扰动。
由于各存储元件之间存在场耦合，因而所存储电荷电平会出现视在偏移。目前，随着存储器单元存储元件之间的间距正在减小，此种耦合的程度必然正在增大，而存储器单元存储元件之间间距的减小则是集成电路制造技术提高的结果。在两群组已在不同时刻进行编程的相邻单元之间，该问题最为明显。对一群组单元进行编程，以向其存储元件增加一对应于一组数据的电荷电平。在使用一第二组数据对第二群组单元进行编程后，由于第二群组存储元件上的电荷以电容方式与第一群组相耦合的影响，自第一群组单元的存储元件读出的电荷电平常常看起来不同于所编程的电荷电平。此称作Yupin效应(Yupin effect)，其阐述于美国专利第5,867,429号中，该专利的全文以引用方式并入本文中。该专利阐述了使这两群组存储元件在实体上相互隔离，或者在读取第一群组存储元件上的电荷时将第二群组存储元件上电荷的影响考虑在内。
发明内容
根据本发明一个方面的一应用，为克服已编程的相邻存储器单元排相互之间的影响，在两个步骤中对相邻排进行编程。在一第一步骤中，使用数据将一第一排存储器单元编程至一第一组中间阈电平。在以同样方式对一相邻的第二排存储器单元进行编程后，将第一排存储器单元的阈电平升高至一第二组最终阈电平。由于对第一排的最终编程是在第二排的初始编程影响下进行的，因而自第一排读出的数据不会受到初始编程入第二排中的电平的不利影响。在将一毗邻第二排的第三排编程至第一组阈电平后，将第二排的阈电平升高至最终组。然后继续进行该过程，来对在相邻排之间存在场耦合的任何其他存储器单元排进行编程。
根据本发明的另一方面的一应用，以一方式存储一群组(例如一排)单元所编程的电平组的一标识，以随所编程的单元群组一同读出。首先，以所施加的读取电压来读取一群组存储器单元，所施加的读取电压选择成最佳地读取使用最常见的一组电平进行编程的单元。如果首先读出的标识显示这些单元先前是使用另一组电平进行编程，则使用对应于该另一组电平的所施加读取电压来再读取该群组单元。
本发明可实施于各种类型的闪速EEPROM单元阵列中。一种设计的NOR阵列是将其存储器单元连接于相邻位(列)线之间并使控制栅极连接至字(排)线。各单元分别包含一个存储元件晶体管，该存储元件晶体管带有或不带有一与其串联形成的选择晶体管，或分别包含两个由一单个选择晶体管隔开的存储元件晶体管。此等阵列及其在存储系统中的应用的实例阐述于SanDisk公司的以下美国专利及待决申请案中，该等美国专利及待决申请案的全文均以引用方式并入本文中：第5,095,344号、第5,172,338号、第5,602,987号、第5,663,901号、第5,430,859号、第5,657,332号、第5,712,180号、第5,890,192号、第6,091,633号、第6,103,573号、及第6,151,248号专利，及2000年2月17日提出申请的第09/505,555号申请案、2000年9月22日提出申请的第09/667,344号申请案、2001年8月8日提出申请的第09/925,102号申请案、及2001年8月8日提出申请的第09/925,134号申请案。
一种设计的NAND阵列具有若干存储器单元，例如8个、16个甚至32个，这些存储器单元以一串联串的形式通过两端的选择晶体管连接于一位线与一参考电位之间。字线跨越不同串联串与各单元的控制栅极相连。此等阵列及其运行的相关实例阐述于以下美国专利及专利申请案中，该等美国专利及专利申请案的全文均以引用方式并入本文中：第5,570,315号、第5,774,397号、及第6,046,935号专利，及2001年6月27日提出申请的第09/893,277号申请案。简言之，在两个步骤中将来自输入数据中不同逻辑页面的两个数据位编程为各单元的四种状态之一，首先根据一个数据位将一单元编程为一种状态，然后，如果该数据使得有必要，则根据输入数据的第二位将该单元重编程为其状态中的另一种状态。
上述专利及专利申请案阐述了使用导电性浮动栅极作为存储器单元存储元件的闪速EEPROM系统。另一选择为，以基本相同的方式来运作其中存储器单元使用电荷陷获介电材料来取代浮动栅极的闪速EEPROM系统。这样的实例包含于由Harari等人在2001年10月31日提出申请的第10/002,696号专利申请案中，该申请案的名称为“使用介电性存储元件的多状态非易失性集成电路存储系统(Multi-State Non-Volatile Integrated Circuit Memory Systems that EmployDielectric Storage Elements)”，该申请案以引用方式并入本文中。相邻存储器单元的介电性存储元件之间的场耦合亦可能会影响自此等存储系统读出的数据的精确性。
根据下文对本发明实例性实施例的详细说明，即可得知本发明的其他方面、特征及优点，下文对本发明实例性实施例的详细说明应参照附图一同来阅读。
附图说明
图1示意性地显示一可在其中实施本发明的实例性存储系统及运作；
图2以平面图形式显示图1所示系统的储存器单元阵列内存储器单元的存储元件的一实例；
图3包含所编程的存储器单元的电平分布曲线，这些曲线显示按顺序编程的相邻存储器单元群组之间场耦合的影响；
图4A-4C是显示本发明原理及根据一个实例实施本发明原理的结果的曲线；
图5显示一对一特定类型的存储器阵列的各排进行编程的实例性顺序；
图6概述用于按图5所示顺序逐排地对数据进行编程的一系列作业；
图7概述用于自一存储器中已根据图6所示方法编程的各排中读取数据的一系列作业；及
图8显示一页面的数据结构的详细实例。
具体实施方式
为解释本发明及实施方案实例，在图1中显示一大容量存储系统实例中各主要组件的相互关系的总图。该系统的一主要组件是存储器11，例如一形成于一半导体衬底上的存储器单元阵列，其中通过在这些存储器单元的各单独存储元件上存储两个或多个电荷电平之一，在各单独存储器单元中存储一或多个数据位。非易失性闪速EEPROM是一种用于此等系统的常见类型的存储器，在本实例中即使用非易失性闪速EEPROM。
图1所示存储系统的一第二主要组件是一控制器13。控制器13通过一总线15与一主计算机或其他正使用该存储系统来存储数据的系统进行通信。控制器13还控制存储器单元阵列11的作业，以写入由主机提供的数据、读取由主机请求的数据、并在正运作该存储器124时执行各种内务功能。控制器13通常包括一通用微处理器、及相关的非易失性软件存储器、各种逻辑电路、及类似件。可包含一或多个状态机及其他控制电路作为该阵列的一部分来控制特定例程的性能，在此种情况下，系统控制器的角色会削弱。
存储器单元阵列11由控制器13通过地址解码器17来寻址。为将数据编程至、读取数据自、或擦除一群组正由控制器13寻址的存储器单元，解码器17会向阵列11的栅极及位线施加正确的电压。附加电路19包括用于控制施加至该阵列中各元件的电压的编程驱动器，这些电压取决于正编程入所寻址的一群组单元的数据。电路19还包括为自所寻址的一群组存储器单元读取数据所需的读出放大器及其他电路。电路17及19的各种具体形式阐述于在上文背景技术部分中所标出的专利及专利申请案中。欲编程入该阵列的数据、或新近自该阵列读出的数据通常存储于控制器13内的一缓冲存储器21中。控制器13还通常含有各种用于临时存储命令及状态数据以及类似数据的寄存器。
阵列11划分成大量存储器单元块BLOCK0-N。通常对于闪速EEPROM系统来说，块即为擦除单位。换言之，每个块均包含可一同擦除的最小数量的存储器单元。亦如图1所示，每个块通常划分成若干页面。页面是编程单位，但各页面可分别划分成若干区段。一区段可含有可作为一基本编程作业一次写入的最少数量的单元，其存储有少达一个字节的数据。在一排存储器单元中通常存储一或多个数据页面。在每一页面内通常存储一个数据扇区，当然亦可包含多个扇区。如图1所示，一扇区包含用户数据及开销数据。开销数据通常包括一根据该扇区的用户数据计算出的ECC。控制器13的一部分23在数据正编程至阵列11内时计算ECC，且亦在正从阵列11读取数据时校验ECC。或者，将ECC及/或其他开销数据存储在与其所从属的用户数据不同的页面甚至不同的块中。开销数据包含一或多个TB位(跟踪位)来指明该数据页在编程时使用的阈值验证电平。TB字段的使用将在下文中予以说明。
一用户数据扇区通常为512字节，此等于磁盘驱动器内一扇区的大小。开销数据通常为一附加的16-20字节。最常见地，在每一页面中包含一个数据扇区，但两个或更多个扇区也可构成一页面。大量页面即构成一个块，例如自8个页面(举例而言)至多达32个、64个或更多个页面不等。块的数量的选择旨在为存储系统提供一所需的数据存储容量。阵列11通常划分成数个子阵列(未图示)，其中每一子阵列均包含这些块的一部分，这些子阵列在一定程度上彼此独立运行以提高在执行各种存储作业时的平行度。美国专利第5,890,192号中阐述了一使用多个子阵列的实例，该专利的全文以引用的方式并入本文中。
图2显示一存储器单元阵列中存储元件(方格)的布置，以便图解说明各排存储器单元之间的电容耦合(虚线)。举例而言，考虑排35中的一存储元件25，其场耦合至每一相邻排37及39中的存储元件。存储元件25与存储元件27及31耦合最紧密，这是因为其相互接近，但存储元件25还与更远的存储元件26、28、32及30存在程度变低的耦合。两个存储元件之间的耦合度取决于其间的距离、其间绝缘材料的介电常数、其间是否存在导电性表面，等等。
尽管图2仅显示各排存储元件之间的场耦合，但在各列存储元件之间也存在此种耦合。在本文所述的实例中未对此加以考虑，因为在这些实例中，数据是以单独的排为单元编程入存储器单元中，人们已发现，各排之间的耦合是造成所编程电平出现视在偏移的原因。例如，如果将数据编程为排35中各存储元件上的不同电荷电平，则相邻排37及39之一或二者上电荷电平的此后的变化将导致此后自排35中各存储元件读出的视在电荷电平出现偏移。自排35中一特定存储元件读出的视在电荷电平的此一偏移的量取决于与其他电荷电平此后出现变化的存储元件耦合的程度及变化的量。当因在相邻排中编程入数据而造成此后的变化时，所产生的偏移量是未知的，除非监测编程入每一排中的数据的样式并作为每一次读取作业的一部分来计算其影响。
图3显示一第一群组存储器单元(例如一排单元)因在此后一第二群组存储器单元(例如相邻单元排)的编程而受到的影响的实例。在本实例中，为每一存储元件界定四个不同的电荷电平，从而在每一存储元件上存储两位数据。由于存储在一存储元件上的电荷的电平会改变其存储器单元晶体管的阈电压(VT)，因而在图3所示曲线的水平轴上显示阈电压。实线显示在一页面刚刚编程后、在对相邻页面作任何改变之前，该页面中所有单元的阈电压数量的分布。竖轴是处于每一阈电平的单元的数量，这些曲线基本具有一高斯分布。曲线45是处于已擦除状态的单元的分布，在本实例中，亦将已擦除状态标记为这些位的已编程状态11。当擦除一单元块时，这些单元会复位至该11状态。
一页面中编程至其他已编程状态47、49或51之一的每一单元均有电子注入其存储元件上，直至其阈值达到分别对应于正编程入该单元中的数据01、00或10的状态。在上文在背景技术中所标出的其他专利中阐述了适当的编程技术。简言之，平行地对一页面中正受到编程的各单元进行编程。那些正编程为10状态的单元被轮流地施以编程电压，然后使用一验证阈电平V10来加以验证。当确定出已将一单元编程至一高于V10的阈电平时，停止对该单元编程，但继续对其他尚未达到各自验证电平的单元进行编程。如果正编程至00，则使用一验证电平V00。而若正编程至01，则使用一验证电平V01。分配给每一分布45、47、49及51的特定数据位对可不同于图3所示，且甚至可在存储系统作业期间循环移位，以便使阵列的磨损均匀。
人们期望使各状态45、47、49及51之间保持一充分的裕量，以便可清楚地读出每一单元的状态。当欲读取如上文所述进行编程的一页面的单元时，将其状态分别与位于这些状态之间的裕量内的参考阈电平相比较。这些参考阈电平在图3所示实例中显示为R10(VT＝0)、R00及R01。当然，为能够充分利用一可用阈值窗口，会包含尽可能多的不同状态，在图中是显示四种状态。另一实例是十六种状态。通过在连续脉冲中使用变小的电压增量来缩窄各分布的宽度，即可得到大量的状态，但此会耗用更多的时间来实施编程。因此，人们期望，单独地或与缩窄所编程单元分布一起，采取措施来降低对各状态之间此等大裕量的需求。相反，为容许所编程的单元分布在其编程之后因重复性的作业循环而出现偏移或扩展(经验已表明如此)，通常会保持大的裕量。为能够减小各状态之间裕量的宽度值，人们非常期望减小此种偏移及扩展。
因对一相邻单元排进行后续编程而引起的分布扩展以虚线形式显示于图3中。甚至当在对一单元排进行初始编程期间保持明显的裕量时，在因后续对一相邻单元排编程而使这些分布扩展时，这些裕量亦可能会明显缩窄。即使仅有几个单元自低于其中一个读取阈值R10、R00及/或R01扩展至高于该读取阈值，亦可能会有足够的错误读数使ECC彻底失效。在此一情况下，不能使用彼等阈值来读取数据，因而通常标记为无效，除非采取某些措施。过去所用的一种用于恢复数据的技术包括：通过简单地在裕量以内移动这些读取阈电平R10、R00及/或R01以避免扩展影响，来再次读取该页面。然而，由于此种扩展可能会来自每一裕量的两侧，因而为防止相邻状态的分布重叠，此需要使裕量保持宽于通常所需的裕量。因此，较佳地采取某些其他措施使所编程状态之间保持宽的裕量。
当后续编程入相邻页面内的数据为随机数据时，换言之，当每一存储元件中所存储的状态可为这四种可能状态中的任一种状态时，所编程的分布看起来以图3所示方式扩展。对于一编程至一位于分布47的下边缘处的电平的存储元件，如果在后续编程期间相邻存储元件上的电荷电平不发生变化，则将读取出该存储元件具有与分布47′中相同的电平。相反，对于一初始编程至一位于分布47的上边缘处的电平的存储元件，如果将相邻存储元件自一已擦除状态11后续编程至一最高状态01，则将读取出该存储元件的电平增大一值Δ。相邻存储元件上的更高电荷电平与其电平正得到读取的先前所编程的存储元件相耦合。对分布47的相邻单元的初始及后续编程的其他组合均落在这两种极端情况之间，从而造成视在分布47′。视在分布47′的下端仍保持相同电平，但其扩展会增大Δ。
在图4A、4B及4C中给出一种用于对图2及3所示阵列的存储器单元进行编程的两遍式技术的一实例。在图4A中，显示出因对一群组(例如一排)单元进行第一遍编程而引起的四种状态阈值分布61、62、63及64。分布61对应于已擦除状态，其亦为已编程状态11。曲线62显示在编程期间使用一验证阈电平VL10编程至10状态的单元的分布。同样地，曲线63表示使用一VL00验证电平编程至00状态的单元的分布，曲线64表示使用一VL01验证电平编程至01状态的单元的分布。此种编程是以上文所提及的专利及专利申请案中所述的通常方式来实现，即对大量正平行编程的单元交替地施加脉冲，然后分别读取(验证)其状态，在确定出超过各单元正编程到的状态的验证阈电平时，终止对该单元进行编程。分布61、62、63及64分别具有一宽度，该宽度取决于每一编程脉冲的电平自最后电平的增大值。分布61、62、63及64可与图3中的分布45、47、49及51相同，只是图4A所示的单元尚未完全编程，而图3所述的彼等单元已完全编程。
图4B显示在使用相同的分布对另一群组(例如一排)在实体上相邻的单元进行后续编程时，出现于已编程单元中的图4A的加宽的分布。在对相邻单元群组(其存储元件与那些其阈值显示于图4A及4B中的存储元件进行场耦合)进行编程时，图4A所示分布61、62、63及64扩展成相应的分布71、72、73及74。如上文在图3中针对相应的分布45′、47′、49′及51′所述，扩展量为Δ。
在对相邻单元群组进行编程、从而产生图4B所示扩展后，使用与先前相同的数据、但使用更高的验证电平再次对已经过初始编程的单元群组进行编程。图4A中所示的初始编程所用验证电平VL--低于图4C中所示的对同一群组单元进行最终再编程所用的验证电平VH--。在一具体实施方案中，其差值可为增量阈值Δ，此即图4C中所显示的增量。由于对一群组单元进行的该第二次、最终编程是在将相邻单元群组编程至第一电平(VL--)后进行，因而在图4C所示的第二编程步骤期间将相邻单元通过电场耦合对第一群组的影响自动地考虑在内。在第二遍中，是在存在后续受到编程的相邻单元的场影响的情况下对单元进行编程。由于在第二步骤中，阈值仅增加一较小的量，因而对相邻单元群组进行的后续第二编程步骤对第一单元群组的分布的影响极小。亦应注意，假定在对一单元群组的第一遍及第二遍编程中均使用相同的编程脉冲变化增量，则在第二编程步骤后图4C所示分布缩窄至图4A所示第一编程步骤的分布。
尽管亦可通过其他技术实现，但较佳地通过使用相同数据但使用更高的验证阈电平进行再编程，在第二遍编程期间增大第一群组单元上的电荷电平。在第一遍编程后、直到第二遍编程前，该数据可保持处于一缓冲存储器中。但由于此需要一大于通常情况的缓冲存储器，因而此通常并非人们所期望。较佳地，在对相邻群组的单元进行初始编程后，将使用更低阈电平VL--编程入一群组单元中的数据自该群组中读出。然后，将所读取数据再编程入相同的单元中但使用更高的阈电平VH--。
在图4A中还包含仅经过第一遍编程的单元的实例性读取阈电平，在图4C中包含已接受过两遍编程的单元的实例性读取阈电平。在这两种情形中，读取阈值均大约位于各相邻分布之间裕量的中点处。对于编程至第一电平的单元(图4A)而言，读取阈值是大约位于各相邻分布之间的中点处的RL10、RL00及RL01。在第二遍编程后(图4C)，使用读取阈值RH10、RH00及RH01，这些读取阈值对应于图4A中的读取阈值，但为保持大约处于再定位后的分布之间的中点处，这些阈值升高一定的阈值量，在本实例中是升高Δ。
所述编程及读取技术可有利地应用于其页面成排布置的存储系统，例如闪速EEPROM。换言之，这些技术用于一其中编程单位包含一或多排存储器单元的存储器单元阵列中。举例而言，可参照图2来解释该过程。对排35中的各存储元件进行第一遍编程，随后，如果排37中的各存储元件已在先前进行过第一遍编程，则对排37中的各存储元件进行第二遍编程。然后，对排39进行第一遍编程，随后对排35进行第二遍编程。在一阵列中以此种来回的方式对相邻排的存储器单元存储元件进行编程，直至正在编程的数据单位已全部得到编程。此亦是图5的目的所在，图5显示对排0-7进行编程的进程。留下拟编程的最末排经过第一遍编程，其第二遍编程延至对下一排相邻的已擦除存储器单元开始后续编程作业时。一例外情况是在最末编程的排亦是块中的最末排时。可在更高的阈电平VH--下对一块中的最末排进行一遍编程。由于各单元块通常相互隔离，因而将不存在其他与该最末排的场耦合足以影响自该块中最末排读取的值的后续编程的排。
由于存储器单元排的最佳读取电压取决于该排是仅经过一遍编程(图4A)还是经过两遍编程(图4C)，因而在编程期间将存储器单元排的已编程状态存储为跟踪位(TB)。该位较佳是作为用户数据的所编程页面的开销数据的一部分来存储。图1中显示将这些跟踪位作为页面开销数据的一部分与用户数据存储于同一排中。作为第一遍编程的一部分，将TB设定为LOW(低)来指示已使用较低的验证阈值设定值进行了编程。作为第二遍编程的一部分，将TB重写至HIGH(高)。在所述的四状态实例中，TB最方便地使用两个位：对于第一遍编程，TB＝11(LOW)，即一个单元的已擦除状态，而在第二遍编程后，TB＝10(HIGH)，即该单元的一更高编程状态。这使得能够通过对一页面的TB进行额外编程，作为第二遍编程的一部分轻松地对该页面的TB进行更新。
由于绝大多数排均进行两遍编程，因而通常使用较高的读取电压进行读取(图4C)。但作为该初始读取作业的一部分，亦读取TB。其值是在页面读取过程的早期进行确定。若TB＝LOW，则使用较低的读取电压设定值进行再读取(图4A)。尽管某些排需要读取两次，但由于在一存储器阵列中在任一时刻保持以较低电平编程的排的比例通常极小，因而存储器性能不会受到明显影响。即使正使用较高读取电平来读取一使用较低验证电平进行编程的排，当使用已擦除状态11来指示TB＝LOW时，在读取其跟踪位时亦不应存在错误。
图6所示流程图显示通过使用上述技术按顺序对若干相邻排(例如图5所示)进行编程的步骤顺序。下文将假定，对于本实例而言，排0，1及2的所有页面均已进行过编程，其中排0及1进行过两遍编程，但排2仅进行过一遍编程。在使用数据对后续各排3+进行编程时的第一步骤是对排3进行寻址，如图6中91所示。然后，在TB＝LOW的情况下对排3的所有页面进行一第一遍编程(图4A)，如93所示。然后，对紧位于前面的排2进行寻址，如95所示。然后，使用低读取电平(图4A)自前面的排2读取数据，如97所示，包括其TB，如99所示。如果TB＝LOW(在本实例中即为如此)，则在101处将所读取TB更新为TB＝HIGH。然后，将所读取数据连同其TB＝HIGH再编程入前面的排2中，如103所示。由此即完成一个数据编程循环。但由于绝大多数数据编程作业涉及到对较一排中所含页面更多的页面进行编程，因而在105处确定是否有其他排要编程。若有，则通过对下面的已擦除的排4进行第一遍编程、随后通过对排5的数据进行再编程以增大排5的电荷电平，来重复该过程。沿图5中的各排(其中相邻排的存储器单元存储元件在一很大程度上以电容方式相互耦合)继续进行该循环。
图7显示一自以图6所示方式进行编程的排读取数据的过程。首先，对一欲读取的第一排进行寻址，如107所示。然后，使用较高的读取电压(图4C)对该排进行读取，如109所示。由于该读取亦包括读取跟踪位，因而在111处确定TB＝LOW或TB＝HIGH。若TB＝LOW，则使用较低的读取电平(图4A)对该排进行再读取，如113所示，随后临时存储所读取数据，如115处所示。由此即完成对一个排的读取。但由于大多数读取作业是按顺序读取多个排，因而通过一询问117来确定是否要读取更多的排。若是，则按顺序读取下一排，如119所示，然后该过程返回109。
下文将参照图8来阐述一存储器单元页面的数据结构的一个实例。用户数据131及与用户数据相关的开销数据133以一使用户可自主机装置通过存储器控制器进行存取的方式来存储。开销数据133包括一根据用户数据计算出的ECC、各种旗标及类似数据。其他开销数据135，例如图8所示页面已得到擦除及再编程的次数的计数值、在编程、读取及擦除时欲使用的电压、及类似数据，则隐藏而不能由主机进行存取，而是由存储器控制器用于运作该存储系统。在隐藏区中亦存储有TB位，且通常含有冗余单元137以供替代用户数据区131中任何失效的位。因此，用户无法自主机装置存取TB位，相反，TB位是由存储系统控制器来写入及读取。
尽管上文是根据实例性实施例来阐述本发明，然而应了解，本发明有权在随附权利要求书的整个范畴内受到保护。
Claims (19)
1、一种用于运作一非易失性存储器单元阵列的方法，所述非易失性存储器单元将数据作为不同的电荷电平存储于其电荷存储元件中，其中所述电荷存储元件的相邻群组之间具有场耦合，该方法包括：
使用一第一组存储电平，将数据连同一已使用所述第一组存储电平的指示一起编程入所述电荷存储元件群组中的一第一群组内，
此后使用所述第一组存储电平，将数据连同一已使用所述第一组存储电平的指示一起编程入所述电荷存储元件群组中的一第二群组内，及
此后将所述电荷存储元件群组中第一群组的所述电荷电平自所述第一组存储电平升高至一第二组存储电平，并存储一已使用所述第二组存储电平的指示。
2、如权利要求1所述的方法，其中所述相邻的电荷存储元件群组位于相邻的存储器单元排中。
3、如权利要求1所述的方法，其中所述电荷存储元件为导电性浮动栅极。
4、如权利要求1所述的方法，其中所述第一及第二组存储电平分别包括多于两个存储电平，以便在所述各单独存储元件中存储多于一位数据。
5、一种用于运作一具有至少第一及第二群组存储器单元的存储器单元阵列的方法，其中所述第一及第二群组之间具有电场耦合，该方法包括：
使用一第一组阈值验证电平将数据编程入所述第一群组存储器单元内，包括存储一已利用所述第一组阈电平的指示，
此后，使用所述第一组阈值验证电平将数据编程入所述第二群组存储器单元内，包括存储一已利用所述第一组阈电平的指示，
此后，使用一第一组读取电平来读取所述已编程入所述第一群组存储器单元内的数据及所述指示，及
此后，使用一第二组阈值验证电平将所述所读取数据再编程入所述第一群组内，包括存储一已使用所述第二组阈电平的指示，所述第二组阈值验证电平高于所述第一组阈值验证电平，
其中可使用一高于所述第一组读取电平的第二组读取电平自所述第一群组读取数据。
6、如权利要求5所述的方法，其另外包括：
使用所述第二组读取电平来读取存储于所述第二群组存储器单元中的数据，包括在编程期间已利用所述第一组阈电平的所述指示，及
响应于读取到在编程期间已利用所述第一组阈电平，使用所述第一组读取电平再读取存储于所述第二群组存储器单元中的数据。
7、如权利要求6所述的方法，其中所述相邻的存储器单元群组位于相邻的存储器单元排中。
8、如权利要求6所述的方法，其中所述存储器单元分别包括至少一个编程带有所述数据的电荷存储元件。
9、如权利要求8所述的方法，其中所述电荷存储元件为导电性浮动栅极。
10、如权利要求6所述的方法，其中所述第一及第二组阈值验证电平分别包括多于两个电平，以便在所述各单独的存储器单元中存储多于一位数据。
11、一种用于对一种将数据作为不同的电荷电平存储于其电荷存储元件中的类型的非易失性存储器单元进行编程的方法，其中在一单元阵列所述电荷存储元件按顺序排列成至少第一、第二及第三排，其中在至少彼等相互紧邻的排中的所述存储元件之间具有场耦合，该方法按下述顺序包括：
将所述第二排的电荷存储元件编程至第一电平，所述第一电平小于所述数据存储电平，
将所述第一排的电荷存储元件上的电荷电平自小于所述数据存储电平升高至所述数据存储电平，
将所述第三排的电荷存储元件编程至第一电平，所述第一电平小于所述数据存储电平，及
将所述第二排的电荷存储元件上的电荷电平自小于所述数据存储电平升高至所述数据存储电平。
12、如权利要求11所述的方法，其中升高所述第一及第二排的电荷存储元件上的电荷电平分别包括：
读取存储于所述第一或第二排中的所述数据，及
使用自所述第一或第二排的存储器单元读取的所述数据将所述第一或第二排的存储器单元编程至所述数据存储电荷电平。
13、如权利要求12所述的方法，其中升高所述第一及第二排的电荷存储元件上的电荷电平均是在未擦除存储于所述第一或第二排中的数据的情况下实现。
14、一种用于运作一非易失性存储器单元阵列的方法，所述非易失性存储器单元将数据作为不同的电荷电平存储于其电荷存储元件中，其中相邻群组的电荷存储元件以电容方式相互耦合，该方法包括：
使用一第一组存储电平，连同一已使用所述第一组存储电平的指示一起将数据初始编程入所述各单独群组的电荷存储元件内，
此后，将所述各单独群组的电荷存储元件的电荷电平自所述第一组存储电平升高至一第二组存储电平，并存储一已使用所述第二组存储电平的指示，
使用与使用所述第二组存储电平相对应的读取电平来初始读取包含所述指示的所述各单独群组的电荷存储元件，及
如果初始读取出所述已使用所述第一组存储电平的指示，则使用与使用所述第一组存储电平相对应的读取电平再读取所述各单独群组的电荷存储元件。
15、如权利要求14所述的方法，其中升高所述各单独群组的电荷存储元件上的电荷电平包括：
读取存储于所述各单独群组的电荷存储元件中的所述数据，及
对所述数据已被读出的所述各单独群组的存储器单元进行编程。
16、如权利要求14所述的方法，其中升高所述各单独群组的电荷存储元件上的电荷电平包括在不擦除存储于所述第一或第二排中的所述数据的情况下升高。
17、如权利要求14所述的方法，其中所述相邻群组的电荷存储元件包括相邻排的存储器单元。
18、如权利要求14所述的方法，其中所述电荷存储元件为导电性浮动栅极。
19、如权利要求14所述的方法，其中所述第一及第二组存储电分别包括多于两个存储电平，以便在所述各单独存储元件中存储多于一位数据。
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| CN101009137B (zh) * | 2006-01-24 | 2012-01-25 | 三星电子株式会社 | 补偿存储单元编程状态之间的读余量减少的闪存系统 |
| CN101009139B (zh) * | 2006-01-24 | 2012-03-21 | 三星电子株式会社 | 能补偿由于高温应力状态间读出边界减小的闪存编程方法 |
| CN101461012B (zh) * | 2006-06-06 | 2013-10-30 | 美光科技公司 | 编程非易失性存储器装置 |
| CN101188142B (zh) * | 2006-09-01 | 2012-08-29 | 三星电子株式会社 | 使用编程数据高速缓存的闪存设备及其编程方法 |
| CN101345086A (zh) * | 2007-06-28 | 2009-01-14 | 三星电子株式会社 | 包括多电平单元的非易失性存储器设备和系统及方法 |
| CN101345086B (zh) * | 2007-06-28 | 2015-03-25 | 三星电子株式会社 | 包括多电平单元的非易失性存储器设备和系统及方法 |
| TWI401686B (zh) * | 2007-10-31 | 2013-07-11 | Micron Technology Inc | 記憶體單元程式化 |
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| CN102132348B (zh) * | 2008-07-01 | 2015-06-17 | Lsi公司 | 用于闪存存储器中写入端单元间干扰减轻的方法和装置 |
| CN107958687A (zh) * | 2016-10-18 | 2018-04-24 | 群联电子股份有限公司 | 存储器编程方法、存储器控制电路单元及其存储装置 |
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| DE60304220T2 (de) | 2007-03-29 |
| EP1535285A1 (en) | 2005-06-01 |
| KR100986680B1 (ko) | 2010-10-08 |
| US6870768B2 (en) | 2005-03-22 |
| DE60304220D1 (de) | 2006-05-11 |
| US20050146931A1 (en) | 2005-07-07 |
| US7046548B2 (en) | 2006-05-16 |
| ATE321339T1 (de) | 2006-04-15 |
| US6781877B2 (en) | 2004-08-24 |
| WO2004023489A1 (en) | 2004-03-18 |
| JP4391941B2 (ja) | 2009-12-24 |
| EP1535285B1 (en) | 2006-03-22 |
| AU2003262675A1 (en) | 2004-03-29 |
| KR20050083680A (ko) | 2005-08-26 |
| ES2262014T3 (es) | 2006-11-16 |
| CN100578667C (zh) | 2010-01-06 |
| US20040047182A1 (en) | 2004-03-11 |
| US20050018482A1 (en) | 2005-01-27 |
| JP2005538485A (ja) | 2005-12-15 |
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