CN1761063A - Structure of dynamic RAM - Google Patents
Structure of dynamic RAM Download PDFInfo
- Publication number
- CN1761063A CN1761063A CN 200410088174 CN200410088174A CN1761063A CN 1761063 A CN1761063 A CN 1761063A CN 200410088174 CN200410088174 CN 200410088174 CN 200410088174 A CN200410088174 A CN 200410088174A CN 1761063 A CN1761063 A CN 1761063A
- Authority
- CN
- China
- Prior art keywords
- those
- bit line
- deep trench
- line contact
- ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The DRAM structure arranges active region of each storage crystal cell on substrate solely; and designs pattern of deep groove as checkerboard type arrangement a fixed pitch is maintained between each adjacent pattern of deep groove. Active regions of diagonal adjacent each two storage units are connected electrically by using long type bit line contact plug. A contact window is setup at each long type bit line contact plug in order to connect bit line. Thus, same bit line can control diagonal adjacent storage units.
Description
Technical field
The present invention relates to a kind of structure of dynamic random access memory, particularly relate to a kind of checkerboard type deep trench pattern that has, with the structure of the dynamic random access memory that improves the element integrated level.
Background technology
Dynamic random access memory (dynamic random access memory; DRAM) device is widely used in the integrated circuit of electronic industry, to carry out the access of binary data.Yet, along with the integrated level of semiconductor circuit improves constantly, the semiconductor element size also must be dwindled thereupon, therefore, the making of dynamic random access memory structure cell in recent years develops the design of capacitor towards three dimensions, with in response to the strict demand of small-sized component to the element leakage current, even also have the dynamic random access memory structure cell, be designed to simultaneously by being positioned at deep trench (deep trench; DT) vertical transistor and deep-trench capacitor constitute, with the integrated level of more effective lift elements.
Though, vertical type bipolar transistor and deep trench capacitor structure can make the structure cell integrated level of dynamic random access memory increase, but for more saving the space of circuit layout (layout), generally again deep trench pattern (DT pattern) is designed to have the symmetrical structure of mirror type at present, as shown in Figure 1.
What Fig. 1 illustrated is an existing substrate surface part vertical view with dynamic random access memory of mirror image symmetrical expression deep trench pattern, wherein, show active region (activeregion) 102, deep trench pattern 104 and bit line (bit line) contact window 106 on the base material 100, and deep trench pattern 104 vertically be arranged as word line (word line) direction, and the transversely arranged bit line direction that is.In addition, between the active region 102, then with the usefulness of shallow plough groove isolation area 108 as electrical isolation.The characteristic of this existing structure, be a storage unit cell unit (unit cell) 111 and another adjacent storage unit cell unit 112, has the relative deep trench pattern 104 of mirror type, presenting the element symmetrical structure of mirror type, and make storage unit cell unit 111 share contact windows 106 with storage unit cell unit 112.
Therefore, existing dynamic random access memory with mirror image symmetry deep trench pattern utilizes two adjacent memory cell can share the characteristic of a contact window 106, and has the advantage that can effectively save arrangement space.But, but can be too close because of part deep trench pattern 104 positions, and it is as easy as rolling off a log in technology, produce the circuit defect 110 that deep trench pattern 104 links to each other, and then influence the quality rate of finished products that element is made, especially when the depth-to-width ratio (aspect ratio) of deep trench pattern 104 when improving day by day, the phenomenon of this kind deep trench circuit defect 110 is with even more serious.
So, how share under the layout advantage of contact window possessing memory cell, and can avoid the generation of deep trench circuit defect, make for the dynamic random access memory that circuit level increases gradually, have a urgent demand really.
Summary of the invention
The deep trench pattern of one of purpose of the present invention for providing a kind of tool checkerboard type to arrange, use for dynamic random access memory, to increase the process margin that component structure is made, and utilize the design of bit line contact plug, make and connect the diagonal angle adjacent memory unit, and have the layout advantage that two memory cell are shared a bit line contact plug, so, will help the making trend that size is dwindled day by day and the integrated benefit of subsisting of element increases of memory product.
According to above-mentioned purpose of the present invention, a kind of structure of dynamic random access memory is proposed, according to one embodiment of the present invention, a dynamic random access memory comprises a plurality of active areas, a plurality of deep trench, a plurality of elongated bit line contact plug, many word lines and multiple bit lines at least.Each active area structure independently is arranged in a base material, and is arranged in a plurality of horizontal arrays, in addition, each deep trench then the position on each active area, with common formation one memory cell region.Wherein, deep trench constitutes a checkerboard type arranges, and keeps a constant spacing between the adjacent deep trench of each same column.Especially, adjacent memory unit regions territory in diagonal angle has the structure of mirror image each other.
Simultaneously, the present invention is the elongated bit line contact plug of design, is positioned at the top of active area, and contacts with active area, and wherein, each elongated bit line contact plug connects two adjacent active areas of diagonal angle, so that connect adjacent memory unit regions territory, diagonal angle.
As for, each word line then for being positioned at the vertical array above the active area, and per two word lines and each active area juxtaposition.Bit line then passes through the top of elongated bit line contact plug, and contacts with the elongated bit line contact plug, and wherein, bit line and word line form a crossed array.
In addition, on the elongated bit line contact plug, also can comprise an insulating barrier, then among insulating barrier, the design contact window, expose each elongated bit line contact plug, and the size of contact window is less than the elongated bit line contact plug, and can not form location overlap with active area.Wherein, contact window with so that the elongated bit line contact plug with contact by the bit line above it, being electrically connected to active region, and insulating barrier is short-circuited in order to another elongated bit line contact plug that blocks an elongated bit line contact plug and adjacent bit lines and pass through.
According to another preferred embodiment of the present invention, a dynamic random access memory comprises multiple row strip formula active area, a plurality of deep trench, a plurality of ring-type oxide layer, a plurality of elongated bit line contact plug, many word lines and multiple bit lines at least.Strip formula active area is arranged in a base material, and has a plurality of memory cell region that structure links to each other on each row strip formula active area, and in addition, each deep trench is then in the base material of position in each memory cell region.Wherein, deep trench is a unit with a strip formula active area, presents symmetry at interval, deep trench on one odd column, with deep trench on another odd column symmetry each other, and constitute a checkerboard type and arrange jointly on base material, and keep a constant spacing between the adjacent deep trench of each same column.
In this embodiment, the ring-type oxide layer is positioned at first inner edge of each deep trench, and each ring-type oxide layer is designed to have first annulus, and second annulus, wherein, the height of first annulus is greater than the height of second annulus, with the memory cell region of utilizing first ring-type that electrical isolation structure is linked to each other.
And the formation of first annulus and second annulus; for example can use a photoresist mask pattern; so that the ring-type oxide layer is carried out etch process; to remove part to a degree of depth of each ring-type oxide layer; so; remove to the ring-type oxide layer of a degree of depth and constitute second annulus, and be subjected to photoresist mask protection, the ring-type oxide layer that is not removed promptly constitutes first annulus.
Similarly, this embodiment also designs the elongated bit line contact plug, and to connect two adjacent memory cell region of diagonal angle, therefore, each elongated bit line contact plug is across the top of adjacent two row strip formula active areas, and contacts with strip formula active area.
In addition, each word line is then for being positioned at the vertical array above the strip formula active area, and per two word lines and each memory cell region juxtaposition.Bit line then passes through the top of elongated bit line contact plug, and contacts with the elongated bit line contact plug, and wherein, bit line and word line form a crossed array.
The design of cumulated volume inventive embodiment, structure in conjunction with arrangement of checkerboard type deep trench and elongated bit line contact plug, to have the layout advantage of memory cell share bit lines contact plunger simultaneously, and by a constant spacing of being kept between each deep trench, and can effectively avoid the deep trench pattern to come in contact short circuit each other.
In addition, the present invention also utilizes a photoresist mask pattern, make the ring-type oxide layer that is arranged in identical deep trench form differing heights, and by highly higher annulus, contact with adjacent active area with the flush type tape conductor layer that blocks follow-up formation, and then reach the effect of the active area unit under each memory cell of electrical isolation.So, will be more can help improving that the benefit of subsisting increases when element is integrated, and process margin is when requiring to improve thereupon, the not good problem of issuable each active area definition of institute, with so significantly promote the finished product rate and the reliability of memory component making.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, cooperate appended graphicly, be illustrated as follows:
Fig. 1 is an existing substrate surface part vertical view with dynamic random access memory of mirror image symmetrical expression deep trench pattern;
With Fig. 2 A be substrate surface part vertical view according to a kind of dynamic random access memory of first preferred embodiment of the invention;
Fig. 2 B is the topology layout part vertical view according to a kind of dynamic random access memory of first preferred embodiment of the invention;
Fig. 3 is the substrate surface part vertical view according to a kind of dynamic random access memory of second preferred embodiment of the invention; And
Fig. 4 A～4B makes the flow process generalized section according to the ring-type oxide layer of the deep groove structure of a kind of dynamic random access memory of second preferred embodiment of the invention; And
Be shown in Fig. 5 A～5C according to the ring-type oxide layer of the deep groove structure of the another kind of dynamic random access memory of second preferred embodiment of the invention and make the flow process generalized section.
The simple symbol explanation
100,200,300,400,500: base material
102,202,302,402,502: active region
104,204:304: deep trench pattern
106,209: contact window
108,205,208: the zone
111,112,211,212: the structure cell unit
207,207a, 207b, 307: contact plunger
220: word line
230: bit line
311,312,315: structure cell
340,440,550: photoresist mask
350,450,450a, 450b: ring-type oxide layer
401,501: upper electrode layer
403,503: dielectric layer
404,504: deep trench
417,517: the degree of depth
505: conductor layer
550,550a, 550b: ring-type oxide layer
Embodiment
Structure of a kind of dynamic random access memory and preparation method thereof is utilized the deep trench pattern layout design of checkerboard type, makes each deep trench all keep fixing distance to each other, and effectively avoids the adjacent deep trench defective that is short-circuited.Simultaneously, cooperate the design of elongated bit line contact plug (contact plug),, make two memory cell can share a bit line contact plug in order to connect two memory cell.Below will be described in detail method of the present invention with embodiment.
Embodiment 1
The present invention has disclosed a kind of structure of dynamic random access memory, and shown in Fig. 2 A, Fig. 2 A illustrate is the substrate surface part vertical view according to a kind of dynamic random access memory of first preferred embodiment of the invention.
At first, the active region that the present invention will have the continuous design of mirror image of memory cell now separates, and forms dislocation, shown in Fig. 2 A, has separately independently active region 202 on the base material 200, deep trench pattern 204 then shows arrangement mode with chessboard, is positioned on each active region 202, wherein, active region 202 for example is a P type silicon substrate, with as a bottom electrode,, then be a capacitance structure as for the inside of deep trench pattern 204.Simultaneously, the present invention is designed to share a contact plunger also with the diagonal angle adjacent memory unit, to be electrically connected to same bit line, for example in the present embodiment, utilize an elongated bit line contact plug 207, so that the storage unit cell unit 211 adjacent with its upper right diagonal angle, a storage unit cell unit 212 is connected.
Wherein, adjacent structure cell unit, diagonal angle 211 and structure cell unit 212 be each other mirror-image structure each other, then, by the design of elongated bit line contact plug 207, with so that connect structure cell unit 211 and structure cell unit 212.In addition, between the active region 202, with the usefulness of shallow plough groove isolation area 208 as electrical isolation.
Arrangement by above-mentioned checkerboard type deep trench pattern 204, it is one fixing apart from d that deep trench pattern 204 is all kept to each other, so, can effectively reduce adjacent deep trench because of hypotelorism, and result in the manufacture process of deep trench definition, the short circuit phenomenon that deep trench links to each other takes place easily.Simultaneously, present embodiment is also by the design of elongated bit line contact plug 207, and structure cell unit 211 and structure cell unit 212 that active region 202 is linked to each other constitute the state that links to each other.
Then, with reference to Fig. 2 B, Fig. 2 B is the topology layout part vertical view according to a kind of dynamic random access memory of first preferred embodiment of the invention, and that is wherein described is the A in conjunction with Fig. 2, and the complete component placement schematic diagram that completes of follow-up word line and bit line.
In Fig. 2 B, the vertical array of each word line 220 by being made of deep trench pattern 204, and each bit line 230 then are same as the transversely arranged direction of deep trench pattern 204, and through elongated bit line contact plug 207, to be electrically connected with elongated bit line contact plug 207.
Observe Fig. 2 B, can find the setting of each bit line 230, the elongated bit line contact plug 207 that is adjacent horizontal row is very approaching, thereby makes the elongated bit line contact plugs 207 that are positioned at different horizontal row originally easily, and the short circuit phenomenon that is electrically connected takes place by bit line 230.For example, one elongated bit line contact plug 207a, elongated bit line contact plug 207b with another adjacent transverse row, the former each other independently state that should be electrically, but it is,, very approaching with elongated bit line contact plug 207b because pass through the bit line 230 of elongated bit line contact plug 207a, partly overlapping each other contact situation occurs so be subject to process conditions easily, and then cause elongated bit line contact plug 207a and elongated bit line contact plug 207b to produce short circuit.
Take place for fear of short circuit problem as above-mentioned elongated bit line contact plug 207, so in the present embodiment, on elongated bit line contact plug 207, cover an insulating barrier earlier, silicon nitride layer for example, and then design the contact window 209 of a size less than elongated bit line contact plug 207.Wherein, elongated bit line contact plug 207 usefulness so that the active region 202 of the memory cell that desire links to each other be connected, contact window 209 is then in order to connect bit line 230 and elongated bit line contact plug 207, so that bit line 230 can be by contact window 209, and reach the purpose that connects the diagonal angle adjacent memory unit.As for, on elongated bit line contact plug 207, and be positioned at contact window 209 zone 205 in addition, then by there being insulating barrier to be covered.
Because the size design of contact window 209 is significantly less than elongated bit line contact plug 207, so the layout figure of bit line 230 is difficult to overlapping to contact window 209, and only may contact to zone 205, even so bit line 230 in the layout, when the figure of the elongated bit line contact plug 207 that lists with adjacent transverse is overlapping to some extent, also can contact with the elongated bit line contact plug 207 of adjacent transverse row and effectively isolate bit line 230, to avoid the generation of short circuit phenomenon because of the insulating barrier setting at regional 205 places.
Embodiment 2
The present invention has disclosed the structure of another kind of dynamic random access memory again, and with reference to Fig. 3, Fig. 3 illustrate is the substrate surface part vertical view according to a kind of dynamic random access memory of second preferred embodiment of the invention.
In Fig. 3, on the base material 300 except the deep trench pattern 304 that checkerboard type arranges is arranged, the graphic designs that also has strip formula active region 302, wherein, present embodiment directly will not be positioned at each the storage unit cell unit on the same strip formula active region 302, define self-existent active area (shown in the active region among Fig. 2 A 202), but utilize a ring-type oxide layer photoresist mask 340, enable in deep trench pattern 304, formation has the ring-type oxide layer 350 of differing heights, to separate the active area of each storage unit cell unit.
Cooperation is with reference to Fig. 4 A～4B, Fig. 4 A～4B is depicted as according to the ring-type oxide layer of the deep groove structure of a kind of dynamic random access memory of second preferred embodiment of the invention and makes the flow process generalized section, and its position of describing is for cutting the cross-section structure of process along the I-I line among Fig. 3.
In Fig. 4 A, have deep trench 404 and active region 402 in the base material 400, and among deep trench 404, be provided with a upper electrode layer 401, and between the sidewall and upper electrode layer 401 of deep trench 404, also be provided with a dielectric layer 403, and one has the ring-type oxide layer 450 of isolation capacitance effect.When ring-type oxide layer 450 is formed in the deep trench 404 originally, has identical height, but present embodiment is after ring-type oxide layer 450 forms, utilize a ring-type oxide layer photomask pattern, to form ring-type oxide layer photoresist mask 440 (being the photoresist mask 340 among Fig. 3), make half of covering ring-type oxide layer 450.Then, carry out the etching step of general follow-up ring-type oxide layer 450 again.
So, when ring-type oxide layer 450 is carried out etching step, the ring-type oxide layer 450 that not covered by photoresist mask 440 is only arranged then, can be removed to a degree of depth 417, and the ring-type oxide layer 450 that covered by photoresist mask 440 is retained with complete.Thereby, can form the structure shown in Fig. 4 B, in Fig. 4 B, ring-type oxide layer 450 has different height on the left and right sides in deep trench 404, and wherein the height of ring-type oxide layer 450a is higher than the height of ring-type oxide layer 450b.
So, when subsequent technique forms flush type tape conductor layer (buried strap) among deep trench 404 time again, higher ring-type oxide layer 450a can completely cut off flush type tape conductor layer and contact with adjacent active region 402, and reaches the effect of isolating the active area under each memory cell.
Recall with reference to Fig. 3, another memory cell 312 that a memory cell 311 is adjacent with the diagonal angle utilizes elongated bit line contact plug 307 to be linked to each other.But with memory cell 311 or the laterally neighbour memory cell of memory cell 312, then must separate to some extent, so present embodiment is promptly by ring-type oxide layer photoresist mask 340, make the part ring-type oxide layer 350 that keeps in the deep trench pattern 304 in certain altitude (shown in the ring-type oxide skin(coating) 450a among Fig. 4 B), active area with each memory cell of energy electrical isolation, and reach the purpose that separates memory cell, for example separate memory cell 311 and memory cell 315.
In addition, except above-mentioned manufacturing process, also can be with reference to the another kind of manufacture method of Fig. 5 A～5C, be shown in Fig. 5 A～5C according to the ring-type oxide layer of the deep groove structure of the another kind of dynamic random access memory of second preferred embodiment of the invention and make the flow process generalized section.
In Fig. 5 A, have deep trench 504, active region 502, upper electrode layer 501, dielectric layer 503 and ring-type oxide layer 550 in the base material 500 equally.Yet different with Fig. 4 A is, ring-type oxide layer 550 is being carried out before part removes, form earlier tape conductor layer 505, be covered on active region 502 and the deep trench 504, the polysilicon that for example can dopant deposition arsenic and the mode of fiting chemical mechanical lapping are formed.Then, utilize a photoresist mask 540 (graphical definition is rendered as the mirror position of the photoresist mask 340 among Fig. 3), make half of shaded portions active region 502 and deep trench 504.Then, in regular turn tape conductor layer 505 and lower electrode layer 501 are carried out etching step respectively.
So, the structure of formation shown in Fig. 5 B via the two-stage etching process, makes the tape conductor layer 505 among half deep trench 504 remove earlier, the part lower electrode layer 501 of below is removed, with ring-type oxide layer 550 to one degree of depth 517 that expose half.In addition, also, carry out groove etching, so that its formation is lower than the kenel of the height of active region 502 to being covered in the tape conductor layer 505 of second half ring-type oxide layer 550 tops.
At last, can directly carry out etching step, form the structure shown in Fig. 5 C a semicircular oxide layer 550 that exposes.In Fig. 5 C, the ring-type oxide layer 550b that exposes will be removed to a degree of depth, and be subjected to the ring-type oxide layer 550a that tape conductor layer 505 covers, then complete being retained.Wherein, use the formed ring-type oxide layer of above-mentioned making flow process 550b, promptly in order to isolate the active area under each memory cell.
So,, just need not go out each active area by predefined, and can directly adopt the structure graph of strip formula active region if use the design of second embodiment of the invention according to above-mentioned, utilize the structural improvement of ring-type oxide layer again, make to reach the effect that active area unit is isolated.In addition, subsist benefit when increasing when element is integrated, even it is as easy as rolling off a log because of process margin requirement raising, and it is not good each active area definition to occur, cause active area to come in contact the phenomenon of short circuit to each other, can effectively avoid because of the active area definition bad short circuit problem that produce if adopt the design of second embodiment of the invention this moment.
The design of comprehensive the above embodiment of the present invention in conjunction with the structure of checkerboard type deep trench pattern and elongated bit line contact plug, having the layout advantage of memory cell share bit lines contact plunger simultaneously, and effectively avoids the deep trench pattern to come in contact short circuit each other.In addition, the present invention also utilizes ring-type oxide layer photoresist mask, form differing heights so that be arranged in the ring-type oxide layer of identical deep trench, block the effect that flush type tape conductor layer contacts with adjacent active area and produce, and then reach the effect of the active area under each memory cell of certain isolation.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (16)
1, a kind of structure of dynamic random access memory comprises at least:
A plurality of active areas are arranged in a base material, and are arranged in many horizontal arrays, and wherein, each those active area structure each other are independent;
A plurality of deep trench, wherein, each those deep trench is arranged in this base material of each those active area, and those deep trench constitute a checkerboard type and arrange, and keeps a constant spacing between each adjacent deep trench of same column;
A plurality of elongated bit line contact plugs are positioned at the top of those active areas, and contact with those active areas, wherein, each those elongated bit line contact plug connect those adjacent active areas of diagonal angles wherein two;
Many word lines are positioned at the top of those active areas, and wherein, each those word line is a vertical array, and each those active area and per two those word line juxtapositions; And
Multiple bit lines by the top of those elongated bit line contact plugs, and contacts with those elongated bit line contact plugs, and wherein, those bit lines and those word lines form a crossed array.
2, structure as claimed in claim 1 also comprises:
One insulating barrier is positioned on those elongated bit line contact plugs; And
A plurality of contact windows, be positioned among this insulating barrier, and on each those elongated bit line contact plug, and in those contact windows, expose those elongated bit line contact plugs, so that the part of those bit lines is by those contact windows, and contact, wherein with those elongated bit line contact plugs, the size of those contact windows is less than those elongated bit line contact plugs, and not with those active area location overlaps.
3, structure as claimed in claim 1, wherein this base material is a silicon substrate.
4, structure as claimed in claim 1, wherein each those active area is a memory cell region, and this memory cell region another memory cell region adjacent with the diagonal angle has mirror-image structure.
5, structure as claimed in claim 1, wherein those horizontal arrays of those active areas formations present symmetry at interval, and those active areas on the odd column are symmetrical each other with those active areas on another odd column.
6, structure as claimed in claim 5, wherein those deep trench are unit with each those horizontal array, present symmetry at interval, arrange and form this checkerboard type.
7, structure as claimed in claim 1 wherein has capacitance structure in those deep trench.
8, structure as claimed in claim 7, wherein the capacitance structure in those deep trench comprises a upper electrode layer, a dielectric layer and a ring-type oxide layer at least.
9, a kind of structure of dynamic random access memory comprises at least:
Multiple row strip formula active area is arranged in a base material, and each those strip formula active area has a plurality of memory cell region that structure links to each other;
A plurality of deep trench, be arranged in this base material of those memory cell region, wherein, those deep trench on one odd column of those strip formula active areas, symmetrical each other with those deep trench on another odd column, those deep trench are common to be constituted a checkerboard type and arranges, and keeps a constant spacing between adjacent each deep trench of same column;
A plurality of ring-type oxide layers, and each those ring-type oxide layer is positioned at first inner edge of each those deep trench, wherein, each those ring-type oxide layer has one first annulus and one second annulus, the height of this first annulus is greater than the height of this second annulus and a upper electrode layer, and this first annulus is in order to those continuous memory cell region of electrical isolation structure;
A plurality of elongated bit line contact plugs, and each those elongated bit line contact plug, two tops that are listed as wherein across those strip formula active areas, and contact with those strip formula active areas, wherein, each those elongated bit line contact plugs connect those adjacent memory cell region of diagonal angles wherein two;
Many word lines are positioned at the top of those strip formula active areas, and wherein, each those word line is a vertical array, and each those memory cell region and per two those word line juxtapositions; And
Multiple bit lines by the top of those elongated bit line contact plugs, and contacts with those elongated bit line contact plugs, and wherein, those bit lines and those word lines form a crossed array.
10, structure as claimed in claim 9 also comprises:
One insulating barrier is positioned on those elongated bit line contact plugs; And
A plurality of contact windows, be positioned among this insulating barrier, and on each those elongated bit line contact plug, and in those contact windows, expose those elongated bit line contact plugs, so that the part of those bit lines is by those contact windows, and contact, wherein with those elongated bit line contact plugs, the size of those contact windows is less than those elongated bit line contact plugs, and not with those strip formula active area location overlaps.
11, structure as claimed in claim 9, wherein this base material is a silicon substrate.
12, structure as claimed in claim 9 wherein has capacitance structure in those deep trench.
13, structure as claimed in claim 12, wherein the capacitance structure in those deep trench comprises this upper electrode layer, a dielectric layer and this ring-type oxide layer at least.
14, structure as claimed in claim 13, wherein this upper electrode layer is a polysilicon layer.
15, structure as claimed in claim 9, wherein also comprise a flush type tape conductor layer among those deep trench, be positioned on this upper electrode layer, wherein, this first annulus of those ring-type oxide layers is between this flush type tape conductor layer of part and those strip formula active areas, and those memory cell region that electrical isolation is linked to each other.
16, structure as claimed in claim 9; wherein those ring-type oxide layers are utilized a photoresist mask pattern; so that those ring-type oxide layers are carried out etching; make part to a degree of depth that removes each those ring-type oxide layer; and form this second annulus; as for protected by this photoresist mask pattern, and those ring-type oxide layers that are not removed partly are this first annulus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100881744A CN100438040C (en) | 2004-10-14 | 2004-10-14 | Structure of dynamic RAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100881744A CN100438040C (en) | 2004-10-14 | 2004-10-14 | Structure of dynamic RAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1761063A true CN1761063A (en) | 2006-04-19 |
| CN100438040C CN100438040C (en) | 2008-11-26 |
Family
ID=36707059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100881744A Active CN100438040C (en) | 2004-10-14 | 2004-10-14 | Structure of dynamic RAM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100438040C (en) |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7989307B2 (en) | 2008-05-05 | 2011-08-02 | Micron Technology, Inc. | Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same |
| US8247302B2 (en) | 2008-12-04 | 2012-08-21 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8268543B2 (en) | 2009-03-23 | 2012-09-18 | Micron Technology, Inc. | Methods of forming patterns on substrates |
| US8273634B2 (en) | 2008-12-04 | 2012-09-25 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8455341B2 (en) | 2010-09-02 | 2013-06-04 | Micron Technology, Inc. | Methods of forming features of integrated circuitry |
| US8518788B2 (en) | 2010-08-11 | 2013-08-27 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
| US8575032B2 (en) | 2011-05-05 | 2013-11-05 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
| US8629048B1 (en) | 2012-07-06 | 2014-01-14 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
| US8796155B2 (en) | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8852851B2 (en) | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US9076680B2 (en) | 2011-10-18 | 2015-07-07 | Micron Technology, Inc. | Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array |
| US9177794B2 (en) | 2012-01-13 | 2015-11-03 | Micron Technology, Inc. | Methods of patterning substrates |
| US9224798B2 (en) | 2008-01-08 | 2015-12-29 | Micron Technology, Inc. | Capacitor forming methods |
| US9330934B2 (en) | 2009-05-18 | 2016-05-03 | Micron Technology, Inc. | Methods of forming patterns on substrates |
| CN106711145A (en) * | 2015-11-16 | 2017-05-24 | 华邦电子股份有限公司 | Semiconductor device and formation method thereof |
| CN107863122A (en) * | 2012-03-26 | 2018-03-30 | 英特尔公司 | Three-dimensional storage control circuit |
| US10151981B2 (en) | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
| CN114283861A (en) * | 2020-09-28 | 2022-04-05 | 长鑫存储技术有限公司 | Integrated circuit memory and forming method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11145414A (en) * | 1997-09-04 | 1999-05-28 | Toshiba Corp | Semiconductor device |
| JP5057616B2 (en) * | 2001-06-29 | 2012-10-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
-
2004
- 2004-10-14 CN CNB2004100881744A patent/CN100438040C/en active Active
Cited By (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8852851B2 (en) | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US11935756B2 (en) | 2006-07-10 | 2024-03-19 | Lodestar Licensing Group Llc | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US11335563B2 (en) | 2006-07-10 | 2022-05-17 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US10607844B2 (en) | 2006-07-10 | 2020-03-31 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US10096483B2 (en) | 2006-07-10 | 2018-10-09 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US9761457B2 (en) | 2006-07-10 | 2017-09-12 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US9305782B2 (en) | 2006-07-10 | 2016-04-05 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US9224798B2 (en) | 2008-01-08 | 2015-12-29 | Micron Technology, Inc. | Capacitor forming methods |
| US9171902B2 (en) | 2008-05-05 | 2015-10-27 | Micron Technology, Inc. | Semiconductor structures comprising a plurality of active areas separated by isolation regions |
| US8629527B2 (en) | 2008-05-05 | 2014-01-14 | Micron Technology, Inc. | Semiconductor structures |
| US8901700B2 (en) | 2008-05-05 | 2014-12-02 | Micron Technology, Inc. | Semiconductor structures |
| US7989307B2 (en) | 2008-05-05 | 2011-08-02 | Micron Technology, Inc. | Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same |
| US10151981B2 (en) | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
| US9653315B2 (en) | 2008-12-04 | 2017-05-16 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8703570B2 (en) | 2008-12-04 | 2014-04-22 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8796155B2 (en) | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8247302B2 (en) | 2008-12-04 | 2012-08-21 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8603884B2 (en) | 2008-12-04 | 2013-12-10 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8273634B2 (en) | 2008-12-04 | 2012-09-25 | Micron Technology, Inc. | Methods of fabricating substrates |
| US8563228B2 (en) | 2009-03-23 | 2013-10-22 | Micron Technology, Inc. | Methods of forming patterns on substrates |
| US8268543B2 (en) | 2009-03-23 | 2012-09-18 | Micron Technology, Inc. | Methods of forming patterns on substrates |
| US9330934B2 (en) | 2009-05-18 | 2016-05-03 | Micron Technology, Inc. | Methods of forming patterns on substrates |
| US8518788B2 (en) | 2010-08-11 | 2013-08-27 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
| US8455341B2 (en) | 2010-09-02 | 2013-06-04 | Micron Technology, Inc. | Methods of forming features of integrated circuitry |
| US8575032B2 (en) | 2011-05-05 | 2013-11-05 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
| US9153458B2 (en) | 2011-05-05 | 2015-10-06 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
| US9076680B2 (en) | 2011-10-18 | 2015-07-07 | Micron Technology, Inc. | Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array |
| US9177794B2 (en) | 2012-01-13 | 2015-11-03 | Micron Technology, Inc. | Methods of patterning substrates |
| CN107863122A (en) * | 2012-03-26 | 2018-03-30 | 英特尔公司 | Three-dimensional storage control circuit |
| CN107863122B (en) * | 2012-03-26 | 2021-05-11 | 英特尔公司 | Three-dimensional memory control circuit |
| US8629048B1 (en) | 2012-07-06 | 2014-01-14 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
| US8846517B2 (en) | 2012-07-06 | 2014-09-30 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
| CN106711145A (en) * | 2015-11-16 | 2017-05-24 | 华邦电子股份有限公司 | Semiconductor device and formation method thereof |
| CN106711145B (en) * | 2015-11-16 | 2019-07-26 | 华邦电子股份有限公司 | Semiconductor device and forming method thereof |
| CN114283861A (en) * | 2020-09-28 | 2022-04-05 | 长鑫存储技术有限公司 | Integrated circuit memory and forming method thereof |
| CN114283861B (en) * | 2020-09-28 | 2024-03-26 | 长鑫存储技术有限公司 | Integrated circuit memory and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100438040C (en) | 2008-11-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1761063A (en) | Structure of dynamic RAM | |
| CN1045349C (en) | Buried bit line cell and the manufacturing method thereof | |
| CN1190263A (en) | Semiconductor device and method for manufacturing thereof | |
| US20050054159A1 (en) | Semiconductor constructions, and methods of forming capacitor devices | |
| CN1930686A (en) | Semiconductor constructions having a buried bit line, and methods of forming same | |
| CN1518100A (en) | Semiconductor device and its manufacturing method | |
| CN1947252A (en) | Memory arrays, methods of forming memory arrays, and methods of forming contacts to bitlines | |
| CN1655339A (en) | Fabrication of lean-free stacked capacitors | |
| CN100336203C (en) | Embedded vertical DRAM cells and dual workfunction logic gates | |
| US8497174B2 (en) | Method of fabricating semiconductor device including vertical channel transistor | |
| US11195837B2 (en) | Semiconductor devices including support patterns | |
| CN1992284A (en) | Layouts for cmos sram cells and devices | |
| CN1507034A (en) | Method for producing semiconductor device with contact extended at bit line direction | |
| CN1870248A (en) | Manufacturing method for a trench capacitor having an isolation collar in a semiconductor memory cell | |
| CN114388508A (en) | Dynamic random access memory and forming method thereof | |
| CN1229861C (en) | Method for forming wiring layer on integrated circuit with high-low topotactic area | |
| CN1097311C (en) | Semiconductor device and method for fabricating the same | |
| CN1126178C (en) | Static randon access memory device photoelectric tube structure and method for mfg. same | |
| CN113437069B (en) | Dynamic random access memory and forming method thereof | |
| CN115117064A (en) | Semiconductor structure and forming method thereof | |
| US7091544B2 (en) | Trench capacitor dynamic random access memory featuring structurally independent symmetric active areas | |
| CN1288758C (en) | Integrated semiconductor internal memory with formed network region selective transistor | |
| CN1303694C (en) | Dynamic random access memory and fabrication thereof | |
| US8394697B2 (en) | Methods of forming capacitors for semiconductor memory devices | |
| CN1591875A (en) | Dynamic RAS with slit capacitor and its mfg. method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |