CN1771704A - Transmitter circuit, receiver circuit, clock data recovery phase locked loop circuit, data transfer method and data transfer system - Google Patents

Abstract

To realize a highly-reliable, stable digital data transmission without the need of reference clock and shake-hand operation. A digital data transmission method for alternatively and periodically transmitting first and second information during first and second intervals, respectively, wherein the information amount of the first information per unit time during the first interval is greater than that of the second information per unit time during the second interval, and the second information during the first interval is transmitted as pulse-width-modulated serial data.

Description

Transtation mission circuit, receiving circuit and clock extracting circuit and data transferring method and data communication system

Technical field

The present invention relates to parallel digital data is carried out transtation mission circuit and receiving circuit and the coding circuit of transtation mission circuit use and data transferring method and the data communication system that uses them that serialization transmits.

And, the present invention relates to parallel digital data is carried out the receiving circuit of the serial data transfer system that serialization receives, the clock that refers in detail in the receiving element of serial data transfer system restores phase locking circuit (be also referred to as the CDRPLL circuit: clock data restores phase-locked loop circuit or clock extracting circuit).

Background technology

In recent years, during the numerical data between device transmitted, high speed serialization transmitted more and more to wish to carry out more.The serial transfer of numerical data has with inferior feature: comparing can do one's utmost to reduce with the parallel convey of numerical data makes the distribution that is connected between device, not only can realize the miniaturization of distribution cable and connector, and can reduce caused cross-talk of phase mutual interference by wiring closet etc.

Generally, in the numerical data serial transmitted, the transmitting element side converted parallel supplied digital data to serial digital data and sends to receiving element.On the other hand, in the receiving element side, the serial digital data that is received is recovered to parallel digital data.

Here, with reference to Figure 65.Figure 65 is the figure that the system configuration of the serial data transfer system that serialization transmits is carried out parallel digital data in expression.In any case, the parallel data that is input to transmitting element is converted into serial data at serial convertor after encoder has carried out the regulation coding, amplify and transmit in (1) electricity/direct-current coupling, (2) electricity/AC coupled, (3) light.After the serial data that receiving element received is being exaggerated, be converted into parallel data at the CDRPLL circuit, decoded at decoder.Direct-current coupling is simple, and can comprise the transmission of the low frequency component of DC component, and AC coupled has the advantage that can make transmitter side and receiver side DC-isolation.Optical communication has can be carried out at a high speed and long advantage apart from transmission.

In any case therein, obtain separately in transmitting element side and receiving element side and to carry out restoring action synchronously, yet when having exceeded the scope of regulation synchronously, can not carry out the Exact Number data recovery.Therefore, under the situation that synchronism deviation has taken place, need readjust synchronously.Following clock ReSet Circuit has been described in patent documentation 1, this clock ReSet Circuit is under the situation that synchronism deviation has taken place, use common mode that reference clock is sent request and send to transmitter side, when when receiver side receives the reference clock of being asked, switch to the frequency comparison pattern from the phase place comparison pattern and readjust.

And in active matrix-type liquid crystal display device or plasma display, numerical data is by serial transfer (for example, with reference to patent documentation 1).Here, with reference to Figure 66 and Figure 67 this serial transfer is in the past described.

The view data that active matrix-type liquid crystal display device uses, shown in Figure 66, by RGB chromatic number separately according to Rx/Gx/Bx with comprise the synchrodata structure of DE (DATA ENABLE: data are enabled)/Hsync (horizontal synchronization data)/Vsync (vertical synchronization data).Between active period, from image data source output chromatic number certificate, at black-out intervals, from image data source output synchrodata.In addition, between active period be DE=" height " during, Hsync and Vsync are still " height " and do not change.

Figure 67 represents the summary that the digital coding of m bit image is become the method for n bit data in the numerical data serial tranmission techniques that this patent documentation 2 disclosed.In this coding method in the past, situation is divided into situation (Figure 67 (A)) that does not send synchrodata and the situation (Figure 67 (B)) that sends synchrodata, carry out the coding of m bit image data.

In this coding in the past, under the situation that does not send synchrodata (Figure 67 (A)), become the m bit image data transaction (encode) of every pixel same logical bit discontinuous more than or equal to the individual n Bits Serial view data of k, carry out time division multiplexing and send.And, under the situation that sends synchrodata (Figure 67 (B)), by carrying out time division multiplexing, and the additional specific bit string that comprises the continuous k of same logical bit forms the serial code into (n-m) position with the m bit image data of every pixel, converts serial image data to and carries out time division multiplexing and send.Here, m, n, k satisfy the condition of m＜n and k＜(n-m) separately.Like this, do not interrupt receiving and dispatching the view data and the synchrodata of the supply that walks abreast, can use a transfer path to receive and dispatch.

Patent documentation 1: United States Patent (USP) 6,069, No. 927 communiques

Patent documentation 2: the spy opens flat 9-168147 communique

Yet, in the method for patent documentation 1, have with inferior problem: owing to need common mode driver and need the common-mode voltage testing circuit, thereby become parasitic capacitance because of these adjunct circuits, noise etc. and make transfer path quality main reasons for decrease at transmitter side in the receiving element side.And, this method is being applied under the situation of optical communication, owing to need two-way communication, thereby need to use 2 optical fiber or carry out WDM (wavelength division multiplexing) transmission, all become the main cause that cost rises.

And, in above-mentioned system in the past, need between transmitting element and receiving element, utilize the interaction action of training signal and confirmation signal.And, in system in the past, the narrow frequency range that recoverable clock frequency is generally limited to stipulate in the CDR of receiving element side.This be because, the clock extracting circuit of receiving element from the clock input of built-in quartz (controlled) oscillator or external oscillator as reference clock, the clock extracting circuit can only be extracted near the clock of the frequency range this reference clock out.Therefore, the problem that has is, under the situation that the transfer rate from the serial data of transmitting element side changes, extracts out because receiver side can not carry out clock, thereby can not carry out data recovery.

And, such as described below in patent documentation 2 described coding methods, can not fully reduce the generation of the mistake in the clock recovery (extraction) when serial data is converted to parallel data.

If in the serial data of 1 code element, there are a plurality of rising edges,, may not as originally, carry out clock and restore then when when the receiving element side is carried out parallelization.Here, 1 code element is meant the serial data block to divide with the data same period of being imported or the rising edge in its integral multiple cycle or trailing edge.

Here, the recovery to clock describes.Fig. 1 represents from by data A1, A2, A3 ... constitute the serial data A (Fig. 1 (A)) of 1 code element and constitute the sequential chart of the serial data B (Fig. 1 (B)) of 1 code element by data B1 at receiving element side recovery clock.In the serial data A shown in Fig. 1 (A), in 1 code element, there are a plurality of rising edges (Rise Edge) and trailing edge (Fall Edge).On the other hand, in the serial data B shown in Fig. 1 (B), in 1 code element, only there are 1 rising edge and trailing edge respectively.

Here, even obtaining in order to restore clock from serial data A under the situation of rising edge that synchronous timing setting is data for some A1, the influence of the waveform deterioration of factor certificate or shake etc. can take place also and the clock that can not obtain at an A1 restores synchronously.That is, restore under the synchronous situation, can obtain the clock recovery as the point outside the settings such as some A2, A3 of rising edge synchronously, restore thereby can not carry out normal clock at the clock that can not obtain at an A1.This is owing to existing a plurality of rising edges to take place as serial data A in 1 code element.

Here, be described in more detail with reference to Fig. 2 (A) with (B).Fig. 2 (A) expression comprises the serial data C of numerical data C1～C6.On the other hand, Fig. 2 (B) represents the serial data D that data structure is different with serial data C, comprise numerical data D1 and D2.In addition, suppose that here the markers of two serial datas is identical.

Among the numerical data D1 and D2 among numerical data C1 in serial data C～C6 and the serial data D, when the pulsewidth of the pulsewidth of C3 and D1 is compared, compare with C3, the pulsewidth of D1 is long.Therefore, the rising edge of serial data C and trailing edge number are more than the rising edge of serial data D.

Near the transition of each numerical data C1～C6 in the serial data C shown in Fig. 2 (A) (near rising edge or the trailing edge), the influence of the waveform deterioration of factor digital data or shake etc. and probability that errors of sampling takes place increase.On the other hand, among each numerical data D1 and D2 in the serial data D shown in Fig. 2 (B), because each data length is longer, data continue longer with the time of code, thereby the probability of generation errors of sampling is very low.In other words, in order to reduce the errors of sampling of serial data, expectation be the few data structure of rising edge of numerical data.

Present inventors think: in above-mentioned known in the past serial transfer technology, when having a plurality of rising edge in 1 code element in serial data, sometimes rising edge is thought by mistake the code element division, mistake takes place synchronously, Here it is can not fully reduce the reason that clock when serial data is converted to the parallel data mistake in restoring takes place.

Restore under the situation of clock at the serial data B shown in Fig. 1 (B) from 1 code element, only there being 1 rising edge, when handle is obtained synchronous timing setting for some B1 for restoring clock, even the influence of the waveform deterioration of data or shake etc. is arranged, owing in 1 code element, only have 1 rising edge, thereby also can reduce the possibility that when clock restores, makes a mistake.

Summary of the invention

Therefore, the present invention is exactly in view of the above problems and proposes, the invention provides a kind of the receiving element side do not need reference clock and do not need interactive action, can carry out the serial data transfer system that simple and easy high-speed serial data transmits.And,, also can follow the serial data transfer system of this variation in the receiving element side even the present invention also provides a kind of serial data transfer rate of transmitting element side to change.

And, the invention provides a kind ofly, can realize that the rising edge in the serial data only is 1, when restoring clock, reduce data transferring method, its transtation mission circuit and receiving circuit and data communication system that the high numerical data of wrong reliability transmits by synchrodata is carried out pulse-width modulation.

And, the purpose of this invention is to provide a kind of because the frequency of voltage control oscillating circuit that makes receiving element in capture range, thereby does not need needed in the past reference clock nor needs clock two-way communication, that can both use in any formation of Figure 65 to restore phase locking circuit.

The present invention is a kind of digital data transmission method, this transfer approach with the 1st information and the 2nd information each during the comfortable the 1st and during the 2nd alternate cycle transmit, it is characterized in that the amount of information of the time per unit of described the 1st information during the described the 1st is more than the amount of information of the time per unit of described the 2nd information during the described the 2nd; Described the 1st information during the described the 1st doubly is that the serial data of 1 code element transmits as the n with minimum pulse width, and the serial data of described the 2nd information during the described the 2nd after as pulse-width modulation transmits.

And, the present invention is a kind of transfer system, this transfer system with the 1st information and the 2nd information each during the comfortable the 1st and during the 2nd alternate cycle carry out serial transfer, it is characterized in that, comprise: the 2nd encoder, described the 2nd information is encoded,, become the pulse-width signal of n doubling time of the minimum pulse width of the serial data when described the 1st information carried out serialization so that carry out serialization and when becoming the serial data of 1 code element in order; The 1st encoder is encoded described the 1st information, so that make the serial data of 1 code element when having carried out serialization in proper order different with described pulse-width signal; Serializer circuit, described coded described the 1st information translation is become the serial data of described 1 code element, described coded described the 2nd information translation is become serial data as the described pulse-width signal of described 1 code element, 1 code-element string line data of described the 1st information and 1 code-element string line data alternate cycle of described the 2nd information are carried out serialization; Transfer path transmits described serialized data; The clock extracting circuit is extracted the reference clock in these serial datas out the serial data of the 1st information that is transmitted or the serial data of described the 2nd information from described transfer path; The information judging circuit, described different according to the data of the serial data of described the 1st information and the serial data of described the 2nd information are differentiated the serial data of described the 1st information and the serial data of described the 2nd information; The 1st decoder is decoded into described the 1st information with the serial data of described described the 1st information of separating is corresponding with described the 1st encoder; And the 2nd decoder, be decoded into described the 2nd information with the serial data of described described the 2nd information of separating is corresponding with described the 2nd encoder; The amount of information of the time per unit of described the 1st information that is transmitted during the described the 1st is more than the amount of information of the time per unit of described the 2nd information that is transmitted during the described the 2nd.

And, the present invention is a kind of transfer system, this transfer system with the 1st information and the 2nd information each during the comfortable the 1st and during the 2nd alternate cycle carry out serial transfer, it is characterized in that, have: the 2nd encoder, described the 2nd information is encoded,, become the pulse-width signal of n doubling time of the minimum pulse width of the serial data when described the 1st information carried out serialization so that carry out serialization and when becoming the serial data of 1 code element in order; The 1st encoder is encoded described the 1st information, so that make the serial data of 1 code element when having carried out serialization in proper order different with described pulse-width signal; Serializer circuit, described coded described the 1st information translation is become the serial digital data of described 1 code element, described coded described the 2nd information translation is become serial data as the described pulse-width signal of described 1 code element, 1 code-element string line data of described the 1st information and 1 code-element string line data alternate cycle of described the 2nd information are carried out serialization; Transfer path transmits described serialized data; And the clock extracting circuit, extract the reference clock in these serial datas the serial data of the 1st information that from described transfer path, is transmitted or the serial data of described the 2nd information out; The information judging circuit, described different according to the data of the serial data of described the 1st information and the serial data of described the 2nd information are discerned the serial data of described the 1st information and the serial data of described the 2nd information; The 1st decoder is decoded into described the 1st information with the serial data of described described the 1st information of separating is corresponding with described the 1st encoder; And the 2nd decoder, be decoded into described the 2nd information with the serial data of described described the 2nd information of separating is corresponding with described the 2nd encoder; Described clock extracting circuit has: phase bit comparison loop, comprise: voltage control circuit, the phase-comparison circuit that the output phase of described serial data and voltage control oscillating circuit is compared, and the loop filter that generates the control voltage of described voltage control circuit; Sampling circuit uses and at the multi-phase clock that described voltage control oscillating circuit generated described serial data is sampled; Frequency control circuit, the frequency of oscillation of the frequency of the serial data of described 1 code element and described voltage control oscillating circuit is compared, make the frequency of oscillation of voltage control oscillating circuit consistent with the frequency of the serial data of described 1 code element, this frequency control circuit has: along the number decision circuit, judge that rising edge number in the serial signal during described 1 code element that described voltage control oscillating circuit generated is 0 or 1 or in addition; And timer, be 0 at the rising edge number, perhaps be reset time interval output timer signal according to the rules under the disabled situation of frequency control circuit; This frequency control circuit is controlled, so that be under 0 the situation, the frequency of oscillation of voltage control oscillating circuit to be descended at the rising edge number, is exporting under the situation of timer signal from timer, and the frequency of voltage control oscillating circuit is risen; Charge pump receives the output of described frequency control circuit, and current impulse is outputed to described loop filter; And mode switch circuit, import from described phase-comparison circuit under the situation of frequency ratio than the mode request signal, enable frequency control circuit, the forbidding phase-comparison circuit, be to detect continuously more than or equal to stated number under 1 the situation at rising edge number or trailing edge number, the output frequency that is judged to be described voltage control oscillating circuit is in the capture range of described phase bit comparison loop, and the forbidding frequency control circuit is enabled phase-comparison circuit.

And, the present invention is a kind of transtation mission circuit, this transtation mission circuit be used for the 1st information and the 2nd information each during the comfortable the 1st and during the 2nd alternate cycle carry out serial transfer, have: the 2nd encoder, described the 2nd information is encoded, so that carry out serialization and when becoming the serial data of 1 code element, become the pulse-width signal of n doubling time of the minimum pulse width of the serial data when described the 1st information carried out serialization in order; The 1st encoder is encoded described the 1st information, so that make the serial data of 1 code element when having carried out serialization in proper order different with described pulse-width signal; And serializer circuit, described coded described the 1st information translation is become the serial data of described 1 code element, described coded described the 2nd information translation is become serial data as the described pulse-width signal of described 1 code element.

And described the 1st encoder can be encoded, so that have the rising edge more than or equal to 2 in the serial data of described 1 code element; Described the 2nd encoder can be encoded, so that only 1 rising edge is configured in the starting point certain position of described 1 code element of distance in the serial data of described 1 code element.

And described the 1st encoder can have: combinational logic circuit has a plurality of corresponding relations of input and output; And decision circuit, estimate described the 1st information of importing at least, output is based on the decision signal of this evaluation; Described combinational logic circuit can carry out the coding of selected described corresponding relation according to described decision signal, and the bits of coded that is used to discern this selected described corresponding relation is given to described output.

And described corresponding relation can comprise the 1st corresponding relation and the 2nd corresponding relation; Described the 1st corresponding relation can be the relation that described input and output equate; Described the 2nd corresponding relation can be to make output carry out the relations that code reverses with respect to described input every 2.

And described decision circuit is that output makes described combinational logic circuit select the decision signal of described the 2nd corresponding relation under 0 the situation at the rising edge number when described the 1st information has been carried out simple serial conversion.

And, described decision circuit carries out simple serial conversion with described the 1st information, when having added different mutually start bit of code and position of rest before and after it, be that output makes described combinational logic circuit select the decision signal of described the 2nd corresponding relation under 1 the situation at the rising edge number.

And the output of described decision circuit makes described combinational logic circuit select same code consecutive numbers in the serial data of described 1 code element behind the coding in described a plurality of corresponding relation to add the decision signal of the little described corresponding relation of value after 1 than 1/2nd of the figure place of the serial data of described 1 code element.

And the output of described decision circuit makes the decision signal of the minimum described corresponding relation of the difference of cumulative number separately of the data in the data symmetric relation after described combinational logic circuit selects to make in described a plurality of corresponding relation coding.

And, be characterised in that the output of described decision circuit makes the decision signal of described corresponding relation of the cumulative number minimum of the data in the data symmetric relation after described combinational logic circuit selects to make in described a plurality of corresponding relation coding.

And, described decision circuit can to the SN of the serial digital data that comprises main information transmitted frequency, EMI amount, described 1 code element and described pulse-width signal than or error rate at least one information estimate the decision signal that output is corresponding with this evaluation.

And, can be replaced as trailing edge to described rising edge.

And described the 2nd encoder can be encoded described the 2nd information, is that starting point arrives between the same code period of trailing edge so that become with described rising edge when order has been carried out serialization.

And, the present invention is a kind of receiving circuit, this receiving circuit is used to receive the serial data with the 2nd information, promptly as the serial data of the 2nd information after the serial dataization of 1 code element of the pulse-width signal of the n doubling time of the minimum pulse width of the serial data of 1 code element of the 1st information, serial data with the 1st information, promptly be serialized into the signal that the serial data alternate cycle of the serial data that makes 1 code element 1st information different with described pulse-width signal is carried out serial transfer, have: the clock extracting circuit, from the serial data of the serial data of described the 1st information or described the 2nd information, extract the reference clock in these serial datas out; The information judging circuit, described different according to the data of the serial data of described the 1st information and the serial data of described the 2nd information are differentiated the serial data of described the 1st information and the serial data of described the 2nd information; The 1st decoder is decoded into described the 1st information with the described serial data of declaring other described the 1st information is corresponding with described the 1st encoder; And the 2nd decoder, be decoded into described the 2nd information with the serial data of described described the 2nd information of separating is corresponding with described the 2nd encoder.

And the serial data of described the 1st information comprises the bits of coded of recognition coding pattern, and described the 1st decoder carries out the decoding corresponding with described bits of coded.

And described information judging circuit is discerned the serial data of described the 1st information and the serial data of described the 2nd information according to the rising edge number in 1 code element of described serial data.

And, the present invention is a kind of numerical data transtation mission circuit, this transtation mission circuit becomes the 1st numerical data the serial digital data of 1 code element to send to receiving circuit with the 2nd digital data conversion, have: encoder, described the 2nd digital data coding is become to go up place value always more than or equal to the numerical data of following place value, in described 1 code element, only generate 1 rising edge; Switching circuit is according to selecting signal to select described the 1st numerical data or described coded described the 2nd numerical data; And serializer circuit, the output signal and the described selection signal of described switching circuit carried out serial conversion.

And, numerical data receiving circuit of the present invention has: the parallelization circuit, parallel the 1st numerical data and the selection signal of converting to of the 1st serial digital data, and parallel the 2nd numerical data and the described selection signal of converting to of the 2nd serial digital data that in 1 code element, only has 1 rising edge; Decoding circuit is decoded described the 2nd numerical data, outputs to the 2nd switching circuit; Described the 1st numerical data is selected and exported to the 1st switching circuit according to described selection signal; And the 2nd switching circuit, select and export described described the 2nd numerical data of decoding according to described selection signal.

And, the present invention is a kind of numerical data transtation mission circuit, this transtation mission circuit becomes the 1st numerical data the serial digital data of 1 code element to send to receiving circuit with the 2nd digital data conversion, have: the 1st encoder, described the 1st numerical data is carried out dc balance handle, in 1 code element, generate rising edge more than or equal to 2; The 2nd encoder becomes to go up place value to described the 2nd digital data coding always more than or equal to the numerical data of following place value, only generates 1 rising edge in 1 code element; Switching circuit is according to described the 1st numerical data or described coded described the 2nd numerical data selected after signal is selected described dc balance processing; And serializer circuit, the output signal of described switching circuit is carried out serial conversion.

And, receiving circuit of the present invention has: the parallelization circuit, having in 1 code element, and the 2nd serial digital data that only has 1 rising edge in 1 code element walked abreast convert the 2nd numerical data to more than or equal to parallel the 1st numerical data that converts to of the 1st serial digital data of 2 rising edges; The 1st decoding circuit is decoded described the 1st numerical data, outputs to the 1st switching circuit; The 2nd decoding circuit is decoded described the 2nd numerical data, outputs to the 2nd switching circuit; Decision circuit is judged the described rising edge number of described the 1st numerical data and described the 2nd numerical data, at described rising edge number be under 1 the situation with more than or equal to 2 situation under the different selection signal of output; Described described the 1st numerical data of decoding is selected and exported to the 1st switching circuit according to described selection signal; And the 2nd switching circuit, select and export described described the 2nd numerical data of decoding according to described selection signal.

And, the present invention is a kind of digital data transmission method, this transfer approach becomes the 1st numerical data of parallel input the serial digital data of 1 code element to send to the receiver side unit with the 2nd digital data conversion in the transmitter side unit, it is characterized in that, during the 1st, become described the 1st numerical data the 1st serial digital data to send to described receiver side unit with the selection conversion of signals, during the 2nd, described the 2nd digital data coding is become to go up place value always more than or equal to following place value, in 1 code element, only generate 1 rising edge, and convert the 2nd serial digital data to and send to described receiver side unit.

And, the present invention is a kind of digital data transmission method, this transfer approach becomes the 1st numerical data of parallel input the serial digital data of 1 code element to send to the receiver side unit with the 2nd digital data conversion in the transmitter side unit, it is characterized in that, during the 1st, described the 1st numerical data is carried out dc balance to be handled, become described the 1st digital data conversion after the described dc balance processing the 1st serial digital data to send to described receiver side unit, during the 2nd, described the 2nd digital data coding is become to go up place value always more than or equal to following place value, in 1 code element, only generate 1 rising edge, and convert the 2nd serial digital data to and send to described receiver side unit.

And, data communication system of the present invention is to become the 1st numerical data of parallel input the serial digital data of 1 code element to send to the digital data transmission system of receiver side unit with the 2nd digital data conversion in the transmitter side unit, has described transmitter side unit and receiver side unit; Described transmitter side unit has: encoder, described the 2nd digital data coding is become to go up place value always more than or equal to the numerical data of following place value, and in described 1 code element, only generate 1 rising edge; The 1st switching circuit is according to selecting signal to select described the 1st numerical data or described coded described the 2nd numerical data; And serializer circuit, described the 1st numerical data in the output signal of described the 1st switching circuit and described selection signal are carried out serial conversion, generate the 1st serial digital data, and described coded described the 2nd numerical data and the described selection signal in the output signal of described the 1st switching circuit carried out serial conversion, generate the 2nd serial digital data; Described receiver side unit has the numerical data receiving circuit, this numerical data receiving circuit has: the parallelization circuit, parallel described the 1st numerical data and the described selection signal of converting to of described the 1st serial digital data, and parallel described coded described the 2nd numerical data and the described selection signal of converting to of described the 2nd serial digital data; Decoding circuit is decoded described coded described the 2nd numerical data, outputs to the 3rd switching circuit; Described the 1st numerical data is selected and exported to the 2nd switching circuit according to described selection signal; Described described the 2nd numerical data of decoding is selected and exported to the 3rd switching circuit according to described selection signal.

And, the present invention is a kind of digital data transmission system, this transfer system becomes the 1st numerical data of parallel input the serial digital data of 1 code element to send to the receiver side unit with the 2nd digital data conversion in the transmitter side unit, has described transmitter side unit and receiver side unit; Described transmitter side unit has: the 1st encoder, and described the 1st numerical data is carried out dc balance handle, in 1 code element, generate rising edge more than or equal to 2; The 2nd encoder becomes to go up place value to described the 2nd digital data coding always more than or equal to the numerical data of following place value, only generates 1 rising edge in 1 code element; The 1st switching circuit is according to the 1st described the 1st numerical data or described coded described the 2nd numerical data of selecting after signal is selected described dc balance processing; And serializer circuit, described the 1st numerical data after the described dc balance processing in the output signal of described the 1st switching circuit is carried out serial conversion, generate the 1st serial digital data, and described coded described the 2nd numerical data in the output signal of described the 1st switching circuit carried out serial conversion, generate the 2nd serial digital data; Described receiver side unit has: the parallelization circuit, parallel described the 1st numerical data that converts to after described dc balance is handled of described the 1st serial digital data, and described the 2nd serial digital data walked abreast convert described coded described the 2nd numerical data to; The 1st decoding circuit is decoded described the 1st numerical data after the described dc balance processing, outputs to the 2nd switching circuit; The 2nd decoding circuit is decoded described coded described the 2nd numerical data, outputs to the 3rd switching circuit; Decision circuit is judged described the 1st numerical data after described dc balance is handled and the described rising edge number of described described the 2nd numerical data of decoding, at described rising edge number be under 1 the situation with more than or equal to 2 situation under output different the 2nd select signal; The 2nd switching circuit selects signal to select and export described described the 1st numerical data of decoding according to the described the 2nd; And the 3rd switching circuit, select signal to select and export described described the 2nd numerical data of decoding according to the described the 2nd.

And, the invention is characterized in to have: phase bit comparison loop comprises: voltage control circuit, the phase-comparison circuit that the output phase of serial data and voltage control oscillating circuit is compared, and the loop filter that generates the control voltage of described voltage control circuit; Sampling circuit uses and at the multi-phase clock that described voltage control oscillating circuit generated described serial data is sampled; Frequency control circuit, the frequency of oscillation of the frequency of described serial data and described voltage control oscillating circuit is compared, make the frequency of oscillation of voltage control oscillating circuit consistent with the frequency of serial data, this frequency control circuit has: along the number decision circuit, judge that rising edge number in the serial signal during 1 code element that described voltage control oscillating circuit generated is 0 or 1 or in addition; And timer, be 0 at the rising edge number, perhaps be reset time interval output timer signal according to the rules under the disabled situation of frequency control circuit; This frequency control circuit is controlled, so that be under 0 the situation, the frequency of oscillation of voltage control oscillating circuit to be descended at the rising edge number, is exporting under the situation of timer signal from timer, and the frequency of voltage control oscillating circuit is risen; Charge pump receives the output of described frequency control circuit, and current impulse is outputed to described loop filter; And mode switch circuit, import from described phase-comparison circuit under the situation of frequency ratio than the mode request signal, enable frequency control circuit, the forbidding phase-comparison circuit, be to detect continuously more than or equal to stated number under 1 the situation at the rising edge number, the output frequency that is judged to be described voltage control oscillating circuit is in the capture range of described phase bit comparison loop, and the forbidding frequency control circuit is enabled phase-comparison circuit.

And, described along the number decision circuit can according to the count results of the rising edge number in the described signal of sampling represent zero output and represent not exist from the result that described serial data is directly judged rising edge output " with " carry out along the judgement of number zero.

And described frequency control circuit can make the frequency of oscillation suppression ratio rising of described voltage control oscillating circuit preferentially carry out.

And described charge pump can make and receive the total charge dosage of charging under the situation of rising signals from described frequency control circuit than in that receive the total charge dosage of discharging under the situation of dropping signal from described frequency control circuit big.

And suitable is, described charge pump makes and receiving the charging pulse number that charges under the situation of rising signals from described frequency control circuit than in that receive the discharge pulse number that discharges under the situation of dropping signal from described frequency control circuit many.

And, suitable is, described charge pump makes and receiving the charge pulse currents of charging under the situation of rising signals from described frequency control circuit than in that receive the discharge pulse current that discharges under the situation of dropping signal from described frequency control circuit big.

And, the present invention is a kind of clock extracting circuit, this clock extracting circuit is extracted clock out from the signal that the serial digital data and the pulse-width signal alternate cycle of 1 code element that the 1st information is decoded have been carried out serial transfer, this pulse-width signal be the 2nd information is encoded into different with the serial digital data of described 1 code element, the pulse-width signal that has carried out pulse-width modulation according to the n doubling time of the pulsewidth of the numerical data of the serial digital data that constitutes described 1 code element, in described 1 code element, only have 1 rising edge or trailing edge, described rising edge or trailing edge are configured in the frame end certain position apart from described 1 code element, it is characterized in that, extract described clock out according to the cycle of described rising edge in described 1 code element or trailing edge.

And clock extracting circuit of the present invention has: voltage-controlled oscillator; Phase comparator, output with import serial data and from the corresponding phase signal of phase difference of the output signal of described voltage-controlled oscillator; Frequency comparator, output is with described input serial data with from the corresponding difference on the frequency signal of the output signal frequency difference of described voltage-controlled oscillator; And the mode switch circuit, select described phase signal or difference on the frequency signal; The frequency of oscillation of described voltage-controlled oscillator is according to being controlled by selected described phase signal of described mode switch circuit or described difference on the frequency signal.

And described frequency comparator has: along the number decision circuit, judge that be 0 or 1 from the input data in 1 code-element period of the output signal of described voltage-controlled oscillator along number, export corresponding to result of determination the number decision signal; Timer is 0 along number and has selected to be reset under the situation of described phase signal time interval output timer signal according to the rules described; And frequency control circuit, along number decision signal and described timer signal, control the frequency of oscillation of described voltage-controlled oscillator according to described; The described official hour of described timer is longer than transmitting the described time interval from information at interval; Described frequency control circuit described be under 0 the situation along number, the frequency of oscillation of described voltage-controlled oscillator is descended, under the situation of having exported described timer signal, the frequency of oscillation of described voltage-controlled oscillator is risen; Described mode switch circuit has obtained at number of times in accordance with regulations to be under the situation of 1 result of determination along number, to select described phase signal continuously described.

And clock extracting circuit of the present invention has: sampling circuit, the input data are sampled the output sampling data; Described have along the number decision circuit: along testing circuit, have or not the edge according to the described input serial data of described input Data Detection, output is along having or not information; Describedly have or not information to judge according to described data from the sample survey and described edge along number along the number decision circuit.

And clock extracting circuit of the present invention has the fine setting frequency comparison circuit; Described fine setting frequency comparison circuit is according to the variable quantity of every code element of the position of the rising edge in 1 code element, calculate described oscillator oscillator signal frequency and based on the frequency departure amount of the frequency in cycle of the described rising edge in described 1 frame, the control signal corresponding with described frequency departure amount outputed to described voltage-controlled oscillator.

And described fine setting frequency comparison circuit has: infer circuit, infer start bit and position of rest in described 1 code element; According to the variable quantity of per 1 code element of described start bit and described position of rest, derive described voltage-controlled oscillator described oscillator signal frequency and based on the frequency departure amount of the frequency in cycle of the described rising edge in described 1 code element; The control signal corresponding with described frequency departure amount outputed to described voltage-controlled oscillator.

According to the present invention, at black-out intervals, the rising edge number of per 1 code element of serial data is fixed to only 1, thereby can be implemented in from serial data when extracting clock out by the minimizing of the caused mistake of waveform deterioration, can realize that stable data transmits.

And,, can have the serial digital data transmission that the simple formation of using a pair of distribution (comprising optical fiber) is carried out the high speed from the transmitting element to the receiving element according to digital data transmission system of the present invention.And obtaining following excellent results is not need the interaction action of in the past being carried out between transmitting element and receiving element that utilizes training signal and confirmation signal.In addition, using under the situation of optical fiber, owing to carried out in the past that needed two-way communication is difficult when training signal and confirmation signal interactive, thereby, do not need interactive action according to the present invention, use at distribution under the situation of optical fiber, obtain remarkable result.

And digital data transmission system of the present invention can be in black-out intervals (Hsync, the Vsync usually) data (voice data etc.) that transmission frequency is low.

And, according to digital data transmission system of the present invention, obtaining following effect is, because serial digital data has been embedded in clock, thereby the clock extracting circuit of receiving element need be from the clock input of quartz (controlled) oscillator or external oscillator, even the picture size of serial digital data changes, also can follow automatically, and also can tackle plug and play.

And, according to the present invention, because receiving element does not need reference clock, and do not need to carry out reverse transmission from the receiver side to the transmitter side, thereby can provide owing to do not need common mode driver and do not need the common-mode voltage testing circuit, thereby eliminated the cost rising main cause of transfer system and the clock of transfer path quality main reasons for decrease restores phase locking circuit at transmitter side at receiver side.

Description of drawings

Fig. 1 is the figure that has the situation of a plurality of rising edges and only have the serial data of 1 rising edge in 1 code element in 1 code element.

Fig. 2 is the figure of the different numerical data of expression data length.

Fig. 3 is the figure of the notion of the expression numerical data transtation mission circuit of an embodiment of the present invention and receiving circuit and digital data transmission method and digital data transmission system.

Fig. 4 is the figure of summary of the serial data of expression an embodiment of the present invention.

Fig. 5 is the figure that the circuit of the transmitting element in expression an embodiment of the present invention constitutes.

Fig. 6 is the circuit block diagram of the 1st coding circuit 2504a in expression an embodiment of the present invention.

Fig. 7 is the figure that the circuit of the combinational logic circuit 2504a-1 in expression an embodiment of the present invention constitutes.

Fig. 8 is the circuit diagram and the action schedule of the 1st coding circuit in an embodiment of the present invention.

Fig. 9 is the flow chart of the coding method of one embodiment of the invention.

Figure 10 is the figure that the circuit of the receiving element in expression an embodiment of the present invention constitutes.

Figure 11 is the circuit diagram of the 1st decoding circuit 2524a in an embodiment of the present invention.

Figure 12 is the circuit diagram of the 2nd decoding circuit 2524b in an embodiment of the present invention.

Figure 13 is the circuit diagram of the 1/ 2nd decoder judging circuit 2524c in an embodiment of the present invention.

Figure 14 is the flow chart of the coding/decoding method in an embodiment of the present invention.

Figure 15 is the circuit diagram and the action specification figure of the DE filter in an embodiment of the present invention.

Figure 16 is the hardware block diagram of expression as the circuit formation of the clock extracting circuit of receiving circuit of the present invention.

Figure 17 is the 1 serial data structure chart of going that image shows.

Figure 18 is the graph of a relation of the period T vco of the rising edge number of serial data of black-out intervals and voltage-controlled oscillator.

Figure 19 is the graph of a relation in the cycle of the rising edge number of the serial data between active period and voltage-controlled oscillator.

Figure 20 is that the expression clock is extracted the flow chart of handling out.

Figure 21 is the hardware block that constitutes of the circuit of expression voltage control oscillating circuit and the figure that represents the timing between each clock.

Figure 22 is serial data and the sequential chart of period of the day from 11 p.m. to 1 a.m clock and the sequential chart of sampling results of the input/output signal of sampler.

Figure 23 is the hardware block diagram of expression along the circuit formation of number decision circuit.

Figure 24 is that expression is along the hardware block diagram of the circuit formation of testing circuit and the sequential chart of input/output signal.

Figure 25 is the hardware block diagram that the circuit of expression difference on the frequency testing circuit constitutes.

Figure 26 is the hardware block diagram that constitutes of the circuit of expression timer and the sequential chart of each signal.

Figure 27 is the circuit block diagram of the formation of expression charge pump.

Figure 28 is hardware block diagram, its sequential chart and the control action transition between states figure that the circuit of expression control circuit constitutes.

Figure 29 is the frequency time variation that clock is extracted the voltage-controlled oscillator in handling out.

Figure 30 is the figure that the error in data that is taken place when numerical data has been carried out serial transfer is described.

Figure 31 is the figure that the serial transfer to the numerical data that error in data does not take place describes.

Figure 32 is the flow chart of the coding method of one embodiment of the invention.

Figure 33 is the circuit diagram of the coding circuit in one embodiment of the invention.

Figure 34 is the circuit diagram of the evaluation function in one embodiment of the invention.

Figure 35 is the flow chart of the coding method of one embodiment of the invention.

Figure 36 is the hardware block diagram that the clock of expression one embodiment of the invention restores the circuit formation of phase locking circuit 2600.

Figure 37 is the circuit block diagram of the fine setting frequency comparison circuit 80 in one embodiment of the invention.

Figure 38 is the figure that the circuit along extracting circuit 80a of expression one embodiment of the invention constitutes.

Figure 39 be expression one embodiment of the invention initial/stop to infer the figure that the circuit of circuit 80b constitutes.

Figure 40 is the figure that the circuit of the frequency detection circuit 80c of expression one embodiment of the invention constitutes.

Figure 41 is the summary pie graph of the transmitting element 3000 of one embodiment of the invention.

Figure 42 is the figure that the circuit of the CRD testing circuit 3000 of expression one embodiment of the invention constitutes.

Figure 43 is the figure that the circuit of the 1st coding circuit of expression one embodiment of the invention constitutes.

Figure 44 is the figure of the serial digital data of expression one embodiment of the invention.

Figure 45 is the figure of expression one embodiment of the invention.

Figure 46 is the figure of expression one embodiment of the invention.

Figure 47 is the figure of the transmitting element in expression one embodiment of the invention.

Figure 48 is the figure of the coding circuit in expression one embodiment of the invention.

Figure 49 is the figure of the receiving element in expression one embodiment of the invention.

Figure 50 is the figure of the decoding circuit in expression one embodiment of the invention.

Figure 51 is the figure of the transmitting element in expression one embodiment of the invention.

Figure 52 is the figure of expression one embodiment of the invention.

Figure 53 is the figure of the serial digital data of expression one embodiment of the invention.

Figure 54 is the figure of the receiving element in expression one embodiment of the invention.

Figure 55 is the figure of the DE filter in expression one embodiment of the invention.

Figure 56 is the figure of the serial digital data of expression one embodiment of the invention.

Figure 57 is the figure of expression one embodiment of the invention.

Figure 58 is the figure of the dc balance coding circuit in expression one embodiment of the invention.

Figure 59 is the figure of expression one embodiment of the invention.

Figure 60 is the figure of expression one embodiment of the invention.

Figure 61 is the figure of the transmitting element in expression one embodiment of the invention.

Figure 62 is the figure of the receiving element in expression one embodiment of the invention.

Figure 63 is the figure of the serial digital data of expression one embodiment of the invention.

Figure 64 is the figure of the clock extracting circuit in expression one embodiment of the invention.

Figure 65 is the figure of the system configuration example of expression serial data transfer system.

Figure 66 is the figure of the formation of the view data used of expression active matrix-type liquid crystal display device.

Figure 67 is the figure that represents that numerical data serial in the past transmits.

Figure 68 is the figure of the serial digital data of expression one embodiment of the invention.

Figure 69 is the figure of the serial digital data of expression one embodiment of the invention.

Figure 70 is the serial data of expression in one embodiment of the invention and the sequential chart of the relation of sampling clock.

Among the figure: 401 transmitting elements, 402 serializer circuit, 403 phase locking circuits, 404 coding circuits, 405 switching circuits, 406 output bufferings, 411 input chromatic number certificates, 412 input synchrodatas, 414 input clocks, 415 serial datas, 421 receiving elements, 422 parallelization circuit, 423 clock extracting circuits, 424 decoding circuits, 425 switching circuits, 426 switching circuits, 427 input bufferings, 431 input chromatic number certificates, 432 output synchrodatas, 434 output clocks, 2501 transmitting elements, 2502 serializer circuit, 2503 phase locking circuits, 2504 coding circuits, 2505 switching circuits, 2506 output bufferings, 2511 input chromatic number certificates, 2512 input synchrodatas, 2514 input clocks, 2515 serial datas, 2521 receiving elements, 2522 parallelization data, 2523 clock extracting circuits, 2524 decoding circuits, 2525 switching circuits, 2526 switching circuits, 2527 input bufferings, 2531 output chromatic number certificates, 2532 output synchrodatas, 2534 output clocks, 10 phase-comparison circuits, 20 loop filters, 30 voltage-controlled oscillators, 40 sampling, 50 frequency comparison circuits, 51 along the number decision circuit, 52 difference on the frequency testing circuits, 53 timers, 60 charge pumps, 70 control circuits, 200 receiving circuits (clock recovery phase locking circuit), 300 serial datas, the PLLCLK:PLL clock, SUBCLK: period of the day from 11 p.m. to 1 a.m clock, DetCLK: along detecting clock, NEDG0: rising edge several 0, NEDF1: rising edge several 1, FQDEN: frequency ratio is than activation signal, FQDEN: phase bit comparison activation signal, FQDRQ: frequency ratio is than request signal, TIM: expression is more than or equal to the signal of the time of 1 line scanning, CLK: system clock.

Embodiment

Below, with reference to the accompanying drawings preferred forms of the present invention (hereinafter referred to as execution mode) is described.Fig. 3 represents the data transmit circuit and the receiving circuit of present embodiment and the data transferring method and the data communication system that use them.This transtation mission circuit can be packaged into to send uses LSI, and this receiving circuit can be packaged into reception LSI.

Transmitting element (transtation mission circuit) 2501 is (in the present embodiment, (the switching signal DEI (input select signal (the input data are enabled)) of input synchrodata (HsyncI (input level synchrodata), VsyncI (input vertical synchronization data), CTRLI (input control)) and the 1st input information and the 2nd input information has carried out serialized serial data 2515 and sent to receiving element 2521 the input chromatic number according to (RI5～RI0, GI5～GI0, BI5～BI0)) and the 2nd input information 2512 with the 1st input information 2511.This serial data 2515 is embedded in the information of input clock 2514.

Receiving element (receiving circuit) 2521 receives the serial data 2515 that is sent from transmitting element 2501, carry out parallelization, (the output chromatic number is exported according to (RO5～RO0, GO5～GO0, BO5～BO0)), the 2nd output information 2532 (HsyncO (output horizontal synchronization data), VsyncO (output vertical synchronization data), CTRLO (output control), DEO (signal (dateout is enabled) is selected in output)) and output clock 2534 to be recovered to the 1st output information 2531.

Transmitting element 2501 has: serializer circuit 2502 (Serializer), phase locking circuit 2503 (PLL circuit: Phase Locked Loop (phase-locked loop) circuit), the 1st coding circuit 2504a (Encoder1) and the 2nd coding circuit 2504b (Encoder2), switching circuit 2505 and output buffer 2506 (Output Buffer).

And, receiving element 2521 has: parallelization circuit 2522 (De-serializer), clock extracting circuit (CDRPLL circuit: Clock Data Recovery Phase Locked Loop (clock data recovery phase-locked loop) circuit) 2523, the 1st decoding circuit 2524a (Decoder1) and the 2nd decoding circuit 2524b (Decoder2), the 1st switching circuit 2525 and the 2nd switching circuit 2526 and input buffer 2527 (Input Buffer).In addition, output buffer 2506 and input buffer 2527 can be provided with as required.And, in the present embodiment, for input chromatic number certificate as the 1st input information 2511, each example of 6 naturally of expression RGB data of all kinds, yet the present invention also can be applied to 8 RGB data and 10 RGB data etc., the invention is not restricted to specific RGB data bits.And, in receiving element 2521, the 1st decoding circuit 2524a, the 2nd decoding circuit 2524b, the 1st switching circuit 2525 and the 2nd switching circuit 2526 be owing to these circuit coordinates realize function that the 1st output information 2531 and the 2nd output information 2532 are separated and generated, thereby also these circuit can be referred to as the information separated circuit.In addition, the 1st input information 2511 is corresponding with the 2nd output information 2531, and the 2nd input information 2512 is corresponding with the 2nd output information 2532.

In transmitting element 2501, the 1st input information 2511 and be imported into respectively among the 1st coding circuit 2504a and the 2nd coding circuit 2504b and encode as the 2nd input information 2512 of input synchrodata.Switching circuit 2505 is used as input select signal to DEI, under the high situation of DEI, select by the 1st coded information 2511 of the 1st coding circuit 2504a, under the low situation of DEI, selection outputs to serializer circuit 2502 by the 2nd coded information 2512 of the 2nd coding circuit 2504b.Input clock 2514 is converted into multi-phase clock at phase locking circuit 2503, and serializer circuit 2502 uses this multi-phase clock that serialization is carried out in the output of switching circuit 2505, generates serial data 2515, exports by output buffer 2506.

The 2nd coding circuit 2504b of transmitting element 2501 encodes the 2nd information (HSYNCI, VSYNCI and CTRLI).At this moment, if the 2nd coding circuit 2504b when the data order having been carried out serialization (simple serialization) in 1 code element with the time on first signal be MSB, then encoding makes the value of the value of MSB more than or equal to LSB, and output to switching circuit 2505.(in the present embodiment, during black-out intervals (DEI=" low "), the dateout of the 2nd coding circuit 2504b is selected by switching circuit 2505, carries out serialization by serializer circuit 2502 from MSB to the LSB order and exports during the 2nd information.Therefore, under the low situation of DEI since by 2502 serialized data of serializer circuit in 1 code element the time early be high level, thereby generation rising edge when code element is switched only.

And the 1st coding circuit 2504a of transmitting element 2501 uses any pattern in a plurality of patterns (making the input corresponding relation corresponding with output) to encode the 1st input information 2511, outputs to switching circuit 2505.(in the present embodiment, when (DEI=" height "), the dateout of the 1st coding circuit 2504a is selected by switching circuit 2505, carries out serialization by serializer circuit 2502 from MSB to the LSB order and exports between active period during the 1st information.About the coding method among the 1st coding circuit 2504a, describe in the back.

In receiving element 2521, at first, clock extracting circuit 2523 restores output clock (CLKO) 2534 and multi-phase clock from serial data 2515.Then, parallelization circuit 2522 uses multi-phase clock that serial data 2515 is converted to parallel signal.This parallel signal is imported into the 1st decoding circuit 2524a, the 2nd decoding circuit 2524b and the 1/ 2nd decoder judging circuit 2524c decodes.For activating, (the output chromatic number is exported output low level when DEI hangs down according to (RO5～RO0, GO5～GO0, BO5～BO0)) to the 1st switching circuit 2525 as the 1st output information 2531 the output parallel data of the 1st decoding circuit 2524a when DEI is high.And the 2nd switching circuit 2526 for activating, is exported the output parallel data of the 2nd decoding circuit 2524b when DEI is low as the 2nd output information 2532 (output synchrodata).And, preferably when DEI is high, keep output.This be because, DEI high during synchrodata do not change.

Below with reference to Fig. 4, the parallel data coding method of the digital data transmission system of present embodiment is described.Fig. 4 (A) and (B) expression as each input chromatic number of 6 of the 1st information of parallel input according to (RI5～RI0, GI5～GI0, BI5～BI0) and in transmitting element 2501, be encoded and the example of the signal waveform of the serial data 2515 that is serialized as the input synchrodata (HsyncI, VsyncI, CTRLI) of the 2nd information.

Shown in Fig. 4 (A), be black-out intervals at DEI=" low ", serial data 2515 embedding the information that HsyncI, VsyncI and CTRLI are arranged as the start bit (Start) of MSB and between by 21 1 code elements that constitute as the position of rest (Stop) of LSB.3 information of coding this HsyncI, VsyncI and CTRLI in the coding circuit 2504 make it carry out becoming after the serialization pulse-width modulation (PWM) data in order.That is, when making start bit be " height ", 3 information of HsyncI, VsyncI and CTRLI are modulated into " height " digit pulse time width.In the example shown in Fig. 4 (A), be that unit carries out the pulse-width modulation of 0 to 7 (0 to 14 bit width) with 2 bit widths.In Fig. 4 (A), expression is with the pulse-width signal of this 14 bit width the 4th example that embeds of start bit since the MSB of 1 code element, yet as long as from the position of start bit level with level, before 1 code element end, take in 14 bit widths, can from who embedding.For example, embed under the PWM data conditions in the 4th of start bit since the MSB of 1 code element, comprise position of rest at the terminal part of 1 code element, having 3 is not the position of PWM data.3 of this terminal part are all " low " level with position of rest.Like this serialized serial data 2515 shown in Fig. 4 (A), have the data structure that in 1 code element, only has 1 rising edge.More than, to start bit is that " height ", position of rest are that " low ", PWM modulating data are that the example of " height " pulsewidth is described, yet as long as can have the data structure that only has 1 rising edge in 1 code element, the level of start bit, position of rest and PWM bits of modulation just is not limited to this example.That is, even the serial data of start bit " low ", position of rest " height " and PWM bits of modulation " low " for example also can constitute the data that only have 1 rising edge in 1 code element, this serial data also can be used in system of the present invention.And in the example shown in Fig. 4 (A), the PWM data constitute by 2 units, yet the PWM data can be by the unit beyond 2, and for example 1 bit width unit constitutes.In addition, under the situation of DEI=" low ", the 2nd input information is carried out pulse-width modulation according to 21 doubling times of the pulsewidth of the numerical data that constitutes the 1st input information.

Also can embed out of Memory in 2 patterns beyond embedding has the pwm signal of information of HsyncI, VsyncI and CTRLI.For example also can in this 2 pattern, embed acoustic information.

Then, at DEI=" height " is between active period, shown in Fig. 4 (B), 1 code element of serial data 2515 by according to start bit (Start), comprise the 1st coded input information (serial digital data D＜17:0 of RI5～RI0, GI5～GI0, BI5～BI0)〉and 1 bits of coded En (being also referred to as the coding mode identifying information) and the order of position of rest (Stop) carried out serialized data structure.Under the situation of DEI=" height ", in order to form in 1 code element serial data that exists more than or equal to 2 rising edge, the 1st coding circuit 2504a shown in Fig. 4 (B), uses any pattern that activates in 1 pattern (ACTV symbol/1) and 2 patterns of activation (ACTV symbol/2) to encode and serialization the 1st input information.In the present embodiment, select any coding mode in 1 pattern that activates and 2 patterns of activation, so that the rising edge number in 1 code element, promptly the transition number is more than or equal to 2.

In the present embodiment, shown in Fig. 4 (B), in serial data 2515, has bits of coded, so that distinguish to using which kind of coding mode in 2 kinds to carry out coded data.In the present embodiment, example as bits of coded, under the situation of using 1 pattern of activation to carry out encoding, at the preceding additional data of position of rest (stop) " 1 " as bits of coded (En), and under the situation of using 2 patterns of activation to carry out encoding,, can carry out coded data and use 2 patterns of activation to carry out coded data and differentiate as bits of coded (En) at the preceding additional data of position of rest (stop) " 0 " use activating 1 pattern.

And, in the present invention, because under the situation of DEI=" low ", rising edge number in 1 code element is 1, thereby under the situation of DEI=" height ", select any coding mode in 1 pattern that activates and 2 patterns of activation, so that not being 1 ground, the rising edge number in 1 code element do not generate serial data.

As shown in Figure 4, in the present embodiment, the serial data of using 2 patterns of activation to carry out coding adopts uses 1 pattern of activation to carry out the formation of per 2 per 2 bit reversals of serial data of coding.That is, at using 1 pattern of activation to carry out the serial data D＜17:0 of coding 〉, the serial data of using 2 patterns of activation to carry out coding adopts D＜D17, D16, and counter-rotating D15, counter-rotating D14, D13, D12 ... D5, D4, the counter-rotating D3, the counter-rotating D2, D1, D0〉formation.In addition, the coding method that use to activate 1 pattern and 2 patterns of activation is not limited to this, can use rising edge in 1 code element and be the transition number more than or equal to 2 coding method.

(transmitting element)

Here, use Fig. 5 that the formation and the connecting and composing of each inscape of the transmitting element 2501 of digital data transmission system of the present invention are described.As shown in Figure 5, the output from the 1st coding circuit 2504a and the 2nd coding circuit 2504b is imported into switching circuit 2505.Switching circuit 2505 has 20 multiplexers.In addition, as shown in Figure 5, in the present embodiment, be imported into switching circuit 2505 from the 1st coding circuit 2504a 18 (ENCD1～18) output with from 7 outputs of the 2nd coding circuit 2504b.

Below with reference to Fig. 6.Fig. 6 represents the circuit block diagram of the 1st coding circuit 2504a in the present embodiment.The 1st coding circuit 2504a has combinational logic circuit 2504a-1 and decision circuit 2504a-2.The 1st input information 2511 (D＜17:0 〉) is imported into combinational logic circuit 2504a-1 and decision circuit 2504a-2.Decision circuit 2504a-2 judges and uses 1 pattern of activation and which kind of pattern in 2 patterns of activation that the 1st input information 2511 is encoded that output is based on the decision signal of this judgement according to the 1st input information 2511.In the present embodiment, the decision signal of decision circuit 2504a-2 output is " height " level signal making combinational logic circuit 2504a-1 activate under the situation of coding of 1 pattern, is " low " level signal under the situation of the coding that activates 2 patterns.This decision signal also can be used as bits of coded En.Combinational logic circuit 2504a-1 encodes the 1st input information 2511 and exports according to decision signal use activation 1 pattern or 2 patterns that activate.And, decision circuit 2504a-2 can be not only according to the 1st input information 2511, and according to the SN of the pulse-width signal of the serial digital data of 1 code element of the transmitted frequency of the 1st information, EMI amount, the 1st information and the 2nd information than or error rate at least one estimate.In the case, decision circuit 2504a-2 obtains these information except the 1st input information.By adopting this formation, the 1st coding circuit 2505a can use the serial digital data of 1 code element of transmitted frequency, EMI amount, the 1st information of the 1st information and the 2nd information pulse-width signal SN than or the good pattern of error rate encode, can comprehensively improve transmission characteristic.

In addition, in the present embodiment, any pattern in 2 kinds of patterns of the 1st coding circuit 2504a use activation 1 pattern and 2 patterns of activation is encoded data, yet the invention is not restricted to this, combinational logic circuit 2504a can have more than 2 kinds coding mode (for example, n pattern), use wherein any pattern that data are encoded.In the case, decision circuit 2504a-2 generates (log ₂N) Wei decision signal outputs to combinational logic circuit 2504a-1.Here, the difference of coding mode means the corresponding relation difference of input and output.Therefore, if coding mode difference, then the corresponding relation difference of input and output.

Below with reference to Fig. 7, the circuit of the combinational logic circuit 2504a-1 of the 1st coding circuit 2504a constituted describe.Combinational logic circuit 2504a-1 has the "or" else circuit (XOR circuit) and the switching circuit of the number corresponding with the figure place of the 1st input information 2511.Data corresponding and be imported into each switching circuit with the corresponding data of 2 patterns of activation with 1 pattern that activates.Each switching circuit is according to the decision signal from decision circuit 2504a-2, select the data corresponding with 1 pattern of activation or with the corresponding data of activation 2 patterns, output to each XOR circuit.The 1st input information 2511 and be imported into each XOR circuit from the output of each switching circuit carries out logical operation by each XOR circuit.The output of each XOR circuit is imported into the 1st switching circuit 2525.

Below, with reference to Fig. 8 (A) with (B) action of the 2nd coding circuit 2504b is described.The circuit of the 2nd coding circuit 2504b of Fig. 8 (A) expression present embodiment constitutes and 7 output (SYNC[0]～SYNC[6]).And Fig. 8 (B) expression is input to the tables of data of Hsync, the Vsync of the 2nd coding circuit 2504b of present embodiment and CTRLI and dateout thereof (SYNC[0]～SYNC[6]).

Shown in the tables of data of Fig. 8 (B), has when having imported data Hsync, Vsync and CTRLI the form that the transition number is restricted from the dateout of the 2nd coding circuit 2504b (SYNC[0]～SYNC[6]).In other words, being HsyncI with upper (MSB), being that 3 bit data of CTRLI are { when Hsync, Vsync, CTRLI} are encoded into 7 bit data { SYNC[0] (upper)～SYNC[6] (the most the next) } with the most the next (LSB), be encoded into: the every increase by 1 of this 3 bit data, just export " height " data continuously from the upper order of this 7 bit data.And in other words, be encoded into: make and go up place value in 7 bit data { SYNC[0] (upper)～SYNC[6] (the most the next) } and always be output more than or equal to the data of place value down.This way of output is commonly referred to as " Thermo-Code (hot code) ", and this coding is called as " Thermo-Code " type coding, and this encoder is called as " Thermo-Code " type encoder.

The 2nd coding circuit 2504b in data transferring method of the present invention and the data communication system takes the Thermo-Code type way of output.In addition, the circuit formation about the 2nd coding circuit 2504b is not limited to the circuit shown in Fig. 8 (A) and constitutes, so long as take the circuit of the Thermo-Code type way of output to constitute, just can adopt any circuit to constitute.Like this, in 1 code element, only generate 1 rising edge.

Here, referring again to Fig. 5.Be imported into switching circuit 2505 from the dateout (ENCD1～19) of the 1st coding circuit 2404a with from the dateout of the 2nd coding circuit 2404b (SYNC[0]～SYNC[6]) and DEI (the input data are enabled).Switching circuit 2505 is according to the DEI that is imported, when DEI=" height ", selection is from the dateout (ENCD1～19) of the 1st coding circuit 2404a, and when DEI=" low ", selection is from the dateout of the 2nd coding circuit 2404b (SYNC[0]～SYNC[6]), and (SR0～SR19) outputs to serializer circuit 2502 data.

Phase locking circuit 2503 forms the different a plurality of clocks of phase place according to input clock 2514, outputs to serializer circuit 2502.

Serializer circuit 2502 is according to the different a plurality of clocks of being imported from phase locking circuit 2503 of phase place, and (SR0～SR19) carry out serialization forms serial data 2515, outputs to receiving element 2521 by output buffer 2506 with the data imported.In the formation of this serial data 2515, in order to form the start bit of " height " in the beginning of 1 code element, form the position of rest of " low " at the end, " height " level and " low " level signal are imported into serializer circuit 2502.

Here, with reference to Fig. 9 the differentiation with input information corresponding codes pattern in the data communication system of present embodiment is elaborated.Fig. 9 represents the flow chart according to the coding mode differentiating method of present embodiment.

At first, the DEI of judgement input information (parallel data) is " height " or " low " (step S1).At step S1, under the situation of DEI=" low ", (HsyncI, VsyncI and CTRLI) encodes with the 2nd information, becomes pulse-width modulation (PWM) signal when having carried out serialization in proper order with box lunch.According to this coding, carrying out after the serialization, can obtain the data structure (step S2) that in 1 code element, only has 1 rising edge number.So far, the digital coding of the 2nd information finishes (step S3).

At step S1, under the situation of DEI=" height ", to import chromatic number according to (RI5～RI0, GI5～GI0, BI5～when BI0) encoding, use 1 pattern of activation to encode, when having added different mutually start bit of code and position of rest before and after it and carried out serialization, whether judgement rising edge number in 1 code element is 1 (step S4), the rising edge number is under 1 the situation in 1 code element, with the 1st information (RI5～RI0, GI5～GI0, BI5～BI0) use 2 patterns of activation to encode (step S5), end data coding (step S6).On the other hand, the rising edge number carries out the processing of step S7 more than or equal under 2 the situation in 1 code element.At step S7, with the 1st information (RI5～RI0, GI5～GI0, BI5～when BI0) encoding, use 2 patterns of activation to encode, when having added different mutually start bit of code and position of rest before and after it and carried out serialization, whether judgement rising edge number in 1 code element is 1 (step S7), the rising edge number is under 1 the situation in 1 code element, with the 1st information (RI5～RI0, GI5～GI0, BI5～BI0) uses 1 pattern of activation encode (step S8), end data coding (step S9), the rising edge number carries out the processing of step S10 more than or equal under 2 the situation in 1 code element.

More than, to carry out simple serial conversion as the input chromatic number certificate of the 1st information, when having added different mutually start bit of code and position of rest before and after it, whether to the rising edge number is 1 to estimate, and judge, yet can not consider start bit and position of rest, to estimating according to the serial data under the situation of having carried out simple serial conversion as the input chromatic number of the 1st information.In the case, judge whether the rising edge number is 0.

In step S10, using the evaluation function of stipulating to estimate which kind of pattern of using 1 pattern of activation or activating in 2 patterns encodes, judge according to this evaluation to be to use 1 pattern of activation to encode (step S8), also be to use 2 patterns of activation encode (step S5).By this digital coding (step S9 or step S6) of encoding and finishing the 1st information.In addition, in step S10, even carried out under the situation of coding in which kind of pattern that use to activate 1 pattern or activate in 2 patterns, can be not identical with the serial data (the rising edge number is 1) of the situation of DEI=" low " yet.

By carrying out above encoding process, the serial data by the data encoded structure under the situation of the situation of DEI=" low " and DEI=" height " can clearly be distinguished: be that rising edge number in 1 code element is 1 (situation of DEI=" low "), still the rising edge number in 1 code element is more than or equal to 2 (situations of DEI=" height ").

As described above, after the 1st information 2511 of parallel input and the 2nd information 2512 are encoded, carry out serialization, be sent to receiving element 2521 from transmitting element 2501 as serial data 2515.In the transmission of the so serialized serial data of institute, calling during the 1st during 1 code element of the serial data of transmission the 1st information 2511, calling during the 2nd during 1 code element of the serial data of transmission the 2nd information 2512.Therefore, the amount of information of the time per unit of the 1st information during the 1st is more than the amount of information of the time per unit of the 2nd information during the 2nd.

More than, in present embodiment shown in Figure 3, adopt following formation: at the prime deploy switch circuit 2505 of serializer circuit 2502, selected 1st information 2511 coded in advance according to DEI and by the 2nd coding circuit 2504b after coded the 2nd information 2512, serializer circuit 2502 is carried out serialization in proper order with these selected data at switching circuit 2505 by the 1st coding circuit 2504a.On the other hand, also can adopt following formation: the prime that serializer circuit 2502 is configured in switching circuit 2505, to carry out separately in serializer circuit 2502 after the serialization by coded the 1st information 2511 of the 1st coding circuit 2504a with by the 2nd coded information 2512 of the 2nd coding circuit 2504b, switching circuit 2505 carries out serialization with the serial data and the 2nd serial data alternate cycle of the 1st information.

(receiving element)

Figure 10 represents the formation of the receiving element 2521 of present embodiment.The serial data of being exported from transmitting element 2,501 2515 is imported into parallelization circuit 2522 and clock extracting circuit 2523 by input buffer 2527.Clock extracting circuit 2523 is extracted clock out from serial data 2515, restore the output clock 2534 a plurality of clocks different with phase place.Parallelization circuit 2522 is according to the different a plurality of clocks of phase place that restored by clock extracting circuit 2523, serial data 2515 is carried out parallelization, and (DSR0～DSR20) outputs to the 1st decoding circuit 2524a, the 2nd decoding circuit 2524b and the 1/ 2nd decoder judging circuit 2524c this dateout.The dateout (DSR1～19) corresponding with the 1st input information 2511 is imported into the 1st decoding circuit 2524a, dateout (DSR4, DSR6, DSR8, DSR10, DSR12, DSR14, DSR16 in the present embodiment) is imported into the 2nd decoding circuit 2524b.And dateout (DSR1～19) is imported into the 1/ 2nd decoder judging circuit 2524c.Each decoding circuit 2524a, 2524b decode the data of being imported, and separately the data corresponding with the 1st input information 2511 and the 2nd input information are outputed to switching circuit 2525,2526.

In addition, receiving element 2521 as shown in figure 10, can have DE filter 2540 and flip-flop circuit 2541.In the case, the dateout of the 1/ 2nd decoder judging circuit 2524c is processed at DE filter 2540, and this output is imported into the 1st switching circuit 2525 and the 2nd switching circuit 2526.In addition, the action of DE filter 2540 describes in detail in the back.

Here, with reference to Figure 11 the 1st decoding circuit 2524a of present embodiment is described.Figure 11 represents the circuit diagram according to the 1st decoding circuit 2524a of present embodiment.In DSR＜19 corresponding with bits of coded (En)〉be under the situation of " low "=0, obtain and use the corresponding specified data (mask " 001100 ") and the DSR＜1:18 of coding method of 2 patterns that activate〉" different " (XOR), D＜17:0〉output to the 1st switching circuit 2525.And, in DSR＜19〉and be under the situation of " height "=1, corresponding to DSR＜1:18 with the coding that activates 1 pattern same as before as D＜17:0 output to the 1st switching circuit 2525.

Below, use Figure 12 that the circuit formation of the 2nd decoding circuit 2524b of present embodiment is described.The 2nd decoding circuit 2524b has 12 NOR circuit, 1 NAND circuit and 2 inverter circuits.In addition, the 2nd decoding circuit 2524b can have the circuit that the synchronizing signal of institute " Thermo-code " change is decoded and constitute, and is not limited to circuit shown in Figure 12 and constitutes.

Below, with reference to Figure 13 the circuit formation of the 1/ 2nd decoder judging circuit 2524c is described.The 1/ 2nd decoder judging circuit 2524c has input 18 AND circuit (the 1st grade) of the dateout (DSR1～19) from parallelization circuit 2522 and the OR circuit (the 2nd grade) that input has these outputs is arranged.At the 1st grade, judge from DSR＜1〉to DSR＜19 each interdigit whether rising edge is arranged.At the 2nd grade, if the 1st grade output have 1 high, then be judged as DEI=" height ", output " height " (=" 1 ") DEO, if the 1st grade output do not have 1 high, then be judged to be DEI=" low ", output " low " (=" 0 ") DEO.Obtaining under the synchronous state, because DSR＜20〉and DSR＜0 respectively position of rest (Stop) and start bit (Start) naturally, thereby be defined as having 1 rising edge therebetween, so result, in the 1/ 2nd decoder judging circuit 2524c, judgement rising edge in 1 code element is 1, still more than or equal to 1.

Here, use flow chart that the coding/decoding method in the receiving element 2521 of present embodiment is described with reference to Figure 14.At first, whether judgement is 1 (step S1) by rising edge number in the data of 1 code element of 2522 parallelizations of parallelization circuit.Be under 1 the situation at the rising edge number, because the data of this 1 code element are the 2nd information (synchronizing signal (HsyncI, VsyncI, CTRLI)), thereby the 2nd decoding circuit 2524b decodes these the 2nd information (step S2), and data decode finishes (step S3).On the other hand, the rising edge number more than or equal to 2 situation under, the data of this 1 code element are that (the chromatic number number of it is believed that (RI5～RI0, GI5～GI0, BI5～BI0)), the data of further judging bits of coded (En) are " 1 " or " 0 " (step S4) to the 1st information.The 1st decoding circuit 2524a is under the situation of " 1 " in the data of bits of coded (En), the data of 1 code element of institute's parallelization are used activation 1 pattern corresponding with the coding of activation 1 pattern decode (step S5), data in bits of coded (En) are under the situation of " 0 ", use activation 2 patterns corresponding to decode (step S7) decoding end (step S6, S8) data of 1 code element of institute's parallelization with the coding of 2 patterns of activation.

Referring again to Figure 10.The 1st switching circuit 2525 is according to the different a plurality of clocks of being imported from clock extracting circuit 2523 of phase place, and selection outputs to flip-flop circuit 2542 from the data that the 1st decoding circuit 2524a is imported.And the 2nd switching circuit 2526 is according to the different a plurality of clocks of being imported from clock extracting circuit 2523 of phase place, and selection outputs to flip-flop circuit 2542 from the data that the 2nd decoding circuit 2524b is imported.Flip-flop circuit 2542 is made of 19 triggers, exports the 1st output information (RO5～RO0, GO5～GO0, BO5～BO0) and the 2nd output information (HsyncO, VsyncO, CTRLO).

Like this, parallel the 1st information the 2511, the 2nd information 2512, DEI and the input clock 2514 that is input to transmitting element 2501 is sent out after the serialization having carried out.The serial data that is received at receiving element 2521 has been carried out decoded after the parallelization, is recovered to the 1st output information the 2531, the 2nd output information 2532, DEO and output clock 2534 and is output.

Below, use Figure 15 that the action of DE filter 2540 is described.The circuit of Figure 15 (A) expression DE filter 2540 constitutes, the sequential chart of the data (DE0, DE1, DE2, DEO) in Figure 15 (B) expression DE filter 2540.The DE filter 2540 of present embodiment has by 1 OR circuit and 3 majority voter 2540a and 3 triggers that the AND circuit constitutes.

The DEI signal is not 1 a pulse width signal only, but the continuous signal of numerical digit.Therefore, if 1 pulse is only arranged in the DEI signal, then it is not a true data, but mistake.DE filter 2540 is removed this mistake.DE filter 2540 is made of the flip-flop circuit and the majority voter 2540a that are used to DEI is postponed.Majority voter 2540a in 3 inputs 1 for a long time, output 1,0 for a long time, output 0.In the waveform example shown in Figure 15 (B), the mistake shown in the thick line is by majority voter 2540 filterings.By adopting the circuit shown in Figure 15 (A) to constitute, even be input to 1 the pulsewidth mistake that comprises serial data in the DE0 of DE filter 2540, also can export removed should mistake DE0.More than, with 2 grades of connections of trigger series connection, adopt per 1 bit period to make the majority voting of 3 signals (DE0, DE1, DE2) of timing slip, yet the majority voting of signal is not limited to 3.For example, trigger can be connected 4 grades connects, and adopts per 1 bit period to make the majority voting of 5 signals of timing slip.

(clock extracting circuit)

Below with the example that is transmitted as of view data, use figure is elaborated to the embodiment of receiving circuit of the present invention.Figure 16 is the circuit formation of phase locking circuit (clock extracting circuit) is restored in expression as the clock of a receiving circuit of the present invention hardware block diagram.This clock extracting circuit is equivalent to the clock extracting circuit 2523 among Fig. 3.Figure 17 is that the transmitting element that is illustrated in transmitter side carries out the serial data structure that serial dataization sends with the parallel image data.At first, the data structure to the serial data of the input signal that restores phase locking circuit as clock shown in Figure 16 describes.The needed serial data structure of scanning 1 row during Figure 17 presentation video shows, (tLine) is made of (tActive) between black-out intervals (tSync) and active period between any 1 departure date.No matter when, be transmitted as 1 code element with initial/1/0 21 of being divided of stopping.According to this is initial/stop to carry out the needed phase bit comparison of Phase synchronization.

In the black-out intervals (tSync) of input data, 1 code element of serial data 300 constitutes by having carried out serialized data according to the order of start bit (Start), coded horizontal synchronization data (HsyncI), vertical synchronization data (VsyncI) and control data (CTRLI) and position of rest (Stop).Specifically, the serial data of the black-out intervals form of pulse-width modulation that had carrying out that certain, trailing edge of rising edge cycle changes because of Hsync, Vsync and CTRLI.

On the other hand, between active period in (tActive), 1 code element of serial data 300 constitutes according to start bit (Start), with 18 19 and orders of position of rest (Stop) of carrying out coding of look data bit (each 6 of R, G, B), has carried out serialized data with 21.In addition, at the coding that carries out R, G, B data so that the rising edge in the code element more than or equal to 2 after, carry out serialization.In the present embodiment, the chromatic number that constitutes serial data is according to each RGB data of 6 naturally, yet is not limited to this.

Below, to being restored, the clock of this serial data of being sent from the transmitting element side when the receiving element side converts parallel data to describe.Figure 18 is the figure of relation in the cycle (Tvco) of the rising edge number of the serial data in 1 code-element period (To) of serial data 300 of expression black-out intervals and voltage-controlled oscillator described later.Because data structure is taked only to have 1 rising edge in 1 code element in the serial data 300 for making, thereby Tvco than the short situation of To under, the frequency (fvco) that is voltage-controlled oscillator is than under the high situation of To frequency (fo), and the rising edge number (NEDG) in the Tvco is 1 or 0.Under the situation of fvco=fo, NEDG=1, under the situation of fvco＜fo, NEDG=1 or 2.Therefore, by estimating NEDG, can judge the magnitude relationship of fvco and fo.

Figure 19 is the figure of relation in the cycle (Tvco) of the rising edge number of the serial data in 1 code-element period (To) of the serial data 300 of expression between active period and voltage-controlled oscillator described later.Rising edge number in 1 code element in the serial data 300 is under the situation of To＞Tvco, and promptly the frequency of voltage-controlled oscillator (fvco) is than under the high situation of the frequency (fo) of To, and rising edge number (NEDG) is more than or equal to 1 or more than or equal to 0.Under the situation of fvco=fo, NEDG is more than or equal to 1, and under the situation of fvco＜fo, NEDG is more than or equal to 1 or more than or equal to 2.Therefore, between active period, only can not judge the magnitude relationship of fvco and fo according to NEDG.

According to above explanation, can be by following differentiation difference on the frequency.

(1) if NEDG=0, then fvco＞fo

(2) if NEDG=1 is continuous to a certain extent, then fvco fo (if consecutive numbers is made as N, the poor fo/N of fvco and fo then.In an embodiment, establish N=30～50)

(3) with to have passed through black-out intervals irrelevant, if (1) and (2) does not take place, fvco＜fo (this is because set than the sufficiently long tTME of tLine, so that certain process blanking during tTME described later) then

Figure 20 is expression according to carrying out the flow chart of the process of clock recovery in the magnitude relationship of the illustrated fvco of Figure 18 and Figure 19 and fo with the relation of NEDG.The serial data that received is used in the sampling pulse that voltage control oscillating circuit described later generated sample (step 100).According to sampling results, the rising edge number of the serial data in the Tvco is counted then, judged whether NEDG=0 (step 110).If NEDG is not equal to 0, whether the consecutive numbers (NNEDG1) of then judging NEDG=1 is more than or equal to regulation numerical value (NNEDG1th) (step 120).Under the situation of NNEDG1, be judged as the capture range that has entered phase bit comparison loop, beginning phase bit comparison (step 130) more than or equal to regulation numerical value.In step 110, if NEDG=0 then is judged as the fvco height, the frequency of voltage control oscillating circuit is descended, timer and NNEDG1 are resetted, continue sampling (step 140, step 170 and step 100) once more.In step 120, surpass under the situation of regulation numerical value at the consecutive numbers of NEDG=1, judge timer whether exceed schedule time (tTIM) (step 150).Under the situation that has surpassed the stipulated time, owing to mean that fvco is lower than fo, thereby fvco is risen, timer and NNEDG1 are resetted, continue sampling (step 140, step 170 and step 100) once more.In step 150, under situation about not exceeding schedule time, get back to step 100.

Getting back to Figure 16 describes the embodiment that this clock restores handling process.In the phase bit comparison loop that the phase-comparison circuit 10 that is restored phase locking circuit 200 by clock, loop filter 20 and the voltage-controlled oscillator (VCO) 30 of Figure 16 constitutes, apply control, make that the code element mark (start bit and position of rest) that will have been carried out the pll clock (PLLCLK) of frequency division and the serial data of being imported by the period of the day from 11 p.m. to 1 a.m clock that voltage-controlled oscillator 30 is generated is consistent.In order to make this phase bit comparison loop action, the frequency f vco that need make pll clock is fully near symbol frequency fo, promptly in capture range.When entering the phase place comparison pattern, in the frequency comparison loop of sampler 40, frequency comparison circuit 50, charge pump 60, loop filter 20 and voltage control oscillating circuit 30, the rising edge number of serial data is counted, obtain NEDG, control, make the fundamental clock (fvco) of voltage-controlled oscillator enter in the capture range of phase bit comparison loop.

This frequency comparison loop control model is described.For the serial data that is sent is sampled, voltage control oscillating circuit 30 generates the period of the day from 11 p.m. to 1 a.m clock of sampling usefulness.Figure 21 is that the circuit of the voltage control oscillating circuit 30 under lock-out state constitutes the sequential chart between hardware block diagram and each square frame.Voltage control oscillating circuit 30 is in order to carry out 2 times oversampling, at the period of the day from 11 p.m. to 1 a.m clock (SUBCLK) of 1 code element output, 2 * 21=42 phase.In addition, in the present embodiment, the multi-phase clock that generates 42 phases at the oscillator of voltage control oscillating circuit 30 is because the problem of circuit area etc., generates the period of the day from 11 p.m. to 1 a.m clock of 14 phases at oscillator, makes its 3 overtones bands vibration according to 1 code element.And being controlled so as to the pll clock (PLLCLK) consistent with the cycle of the code element mark (start bit and position of rest) of the serial data of being imported is in the frequency divider logical circuit, 1 sub-clock is carried out 3 frequency divisions and generates.Have or not generating by carrying out frequency division and logical process too of edge described later in the Tvco along being used in the testing circuit judge along detecting clock (DetCLK).14 phase period of the day from 11 p.m. to 1 a.m clock and watch of Figure 21 (b) expression period of the day from 11 p.m. to 1 a.m clock (0)～period of the day from 11 p.m. to 1 a.m clock (13) show at serial data in the action of phase bit comparison loop and the timing relationship under the blocked situation.For simplicity, below the cycle that 3 frequency divisions have been carried out in the output of voltage control oscillating circuit 30 is made as Tvco, its inverse is made as fvco describes.

The sampler of Figure 16 (parallelization circuit) 40 uses samples the serial data of being imported at the illustrated period of the day from 11 p.m. to 1 a.m clock of Figure 21.Figure 22 represents serial data and the figure of the timing relationship of the timing relationship of the period of the day from 11 p.m. to 1 a.m clock of sampling and sampling results.Can know that by carrying out 3 sampling by 14 per 1 code-element periods of each period of the day from 11 p.m. to 1 a.m clock that constitute mutually, realization is as the sampling of 21 2 times 42 phases.

In frequency comparison circuit 50, according to this sampling results, the relation of the frequency (fo) of 1 code-element period (To) of fundamental frequency of voltage-controlled oscillator 30 (fvco) and black-out intervals is compared, by charge pump 60 control signal is sent to loop filter 20, make fo fvco, the fvco of control voltage control oscillating circuit 30.

Frequency comparison circuit 50 comprises: along number decision circuit 51, the rising edge number of being sampled is counted, judgement is 1 or 0 or in addition; Timer 53 generates the commutator pulse that surpasses the time of (tLine) between 1 departure date; And difference on the frequency testing circuit 52, detect the poor of fvco and fo according to this judgement and timer output.

Figure 23 is the hardware block diagram of expression along the circuit formation of number decision circuit 51.Sampling results signal SMPD (0) shown in Figure 22～SMPD (42) is separately as the "AND" circuit that just is input to adjacency with reverse signal respectively.In waveform example for example shown in Figure 22, the sampling results signal of SMPD (14), (15), (16) respectively does for oneself 0,0,1.When this signal was input to "AND" circuit, because the input of the 16th "AND" circuit all is 1, thereby the output of EDG (15) was 1.Because at 1 code-element period, it is 1 that EDG (0～20) only has this 1, thereby is the OR circuit output high level of 1 decision circuit (NEDG1) by the rising edge number of Figure 23-b.

At Figure 23 (a) if in sampling results all be 0, then EDG (0～20) all is 0, by NOR circuit, output (NEDGOS) be 1.In the case, when only judging according to sampling results, under the very slow situation of the fundamental frequency of the oscillator of voltage control oscillating circuit 30, because the interval of period of the day from 11 p.m. to 1 a.m clock is longer than 1 pulsewidth Tbit of serial data shown in Figure 70, thereby occur in the sampling hourglass get rising edge, can not detect the situation of rising edge.Disconnected for fear of this erroneous judgement, use along testing circuit (EDGDET), obtain with directly judge from serial data the result (EDGDETX) that has or not rising edge " with ", carry out the judgement of rising edge 0.

Here, to describing along testing circuit (EDGDET).Figure 24 is that expression is along the hardware block diagram of the circuit formation of testing circuit (EDGDET) and the sequential chart of input/output signal.In Figure 24 (a), serial data and shown in Figure 21 being imported into along testing circuit along detecting clock (DetCLK), serial data has or not rising edge during the detection Tvco.Along detecting clock is the synchronizing signal of Tvco.Figure 24 (b) express time figure.The output EDGDET0 of trigger FF1 is " height " when detecting the rising edge of serial data.Because FF1 is reset when DetCLK " height ", thus EDGDET0 represent DetCLK " low " during have or not rising edge.For FF2, by the rising edge that uses DetCLK EDGDET0 is carried out breech lock and determine to judge.This signal counter-rotating is exported as EDGDETX.Shown in Figure 24 (b), serial data has under the situation of rising edge during DetCLK " low ", and the EDGDETX during next is " low ", is not having under the situation of rising edge, and the EDGDETX during next is " height ".

By more than, from export NEDG0 and the NEDG1 as the result of determination of rising edge number separately along number decision circuit 51, NEDG0 is imported into difference on the frequency testing circuit 52 and timer 53, NEDG1 is imported into control circuit 70.Figure 25 is the circuit block diagram that the circuit of expression difference on the frequency testing circuit 52 constitutes.Input NEDG0 means the frequency height of the fundamental clock that the oscillator of voltage control oscillating circuit 30 takes place.Therefore, difference on the frequency testing circuit 52 receives these NEDG0, obtain with the signal (FQDEN) that is in the FREQUENCY CONTROL pattern from the expression of control circuit 70 described later " with ", the frequency dropping signal that is used to make frequency decline is outputed to the charge pump 60 of Figure 16.

And, be not NEDG0, but NEDG1 is discontinuous more than or equal to stipulated number, and its state kept the time more than or equal to 1 line scanning, this means that the frequency of fundamental clock is low.Therefore, difference on the frequency testing circuit 52 obtain NEDG0 the low level reverse signal, from control circuit 70 be used to keep the FREQUENCY CONTROL pattern in case do not enter phase control mode signal (FQDEN) and from the stipulated time signal of the timer 53 that the following describes " with ", output is used to frequency rising signals that frequency is risen.The circuit of Figure 25 becomes the mediation circuit that makes dropping signal preferential.This be because, compare with rising, (because if NEDG=0, then decidable is for being fvco＞fo) for the accuracy height of descend judging.

Figure 26 is the hardware block diagram that constitutes of the circuit of expression timer and the sequential chart of each signal.In Figure 26 (a), being used to export expression has passed through more than or equal to the timer 53 of the signal of time of 1 row the clock (OSCCLK) of oscillator has been counted, generate official hour (TIM0), carry out the edge and detect, the signal (TIM) that generates that Figure 17 represents more than or equal to time of 1 horizontal-scanning interval (tLine).The signal (FQDEN) that oscillator is in the FREQUENCY CONTROL pattern to expression is as enabling signal (Enable), counter the reverse signal of FQDEN and NEDG0 " with " as reset signal (RSTn).Because the interval of TIM signal capablely looks The more the better than 1, thereby to cycle of TIM signal and do not require too high time precision.Therefore, oscillator can use the low oscillator of precision of RC oscillator or ceramic resonator etc.The sequential chart of Figure 26 (b) is represented each time relationship.

Figure 27 is the circuit block diagram that the circuit of expression charge pump 60 constitutes.The output of charge pump 60 receive frequency difference detecting circuits 52 outputs to the charging and discharging currents pulse of carrying out FREQUENCY CONTROL the loop filter 20 of Figure 16.This current impulse is to generate at pulse generating circuit according to the clock of voltage control oscillating circuit 30 (CLK).Because the rising signals that frequency is risen is lower than dropping signal frequency, thereby under the situation of having imported rising signals, carries out the charging greater than the discharge of dropping signal.For example in Figure 27, make the rising signals elongation by pulse stretching, yet also can make charging current bigger than discharging current.The rising signals of using the charging current pulse and being extended " with " generate the charging current pulse, and use and dropping signal " with " generate discharge current pulse, output to loop filter 20.Voltage control oscillating circuit 30 uses the frequency corresponding with the voltage of loop filter 20 to vibrate.Like this, under the situation of having imported rising signals,, the frequency of oscillation of voltage control oscillating circuit 30 is entered in the capture range rapidly by carrying out greater than the charging of the discharge of dropping signal and making charging current bigger than discharging current.

Figure 28 is the transition between states figure of circuit block diagram, its sequential chart and the expression control action of the formation of expression control circuit 70.In Figure 28 (a), the NEDG1 signal that control circuit 70 receives along number decision circuit 51 is counted its consecutive numbers at counter, output CNEDG1 when surpassing regulation numerical value.State machine is connected with the back level of counter, receive this CNEDG1 with when power supply drops into or can not introduce the signal of being exported from phase-comparison circuit 10 under the situation of bit comparison loop mutually (FQDRQ), signal (PHDEN) is enabled in the bit comparison of generation phase and FREQUENCY CONTROL is enabled signal (FQDEN), PHDEN is outputed to phase-comparison circuit 10, FQDEN is outputed to difference on the frequency testing circuit 52 and timer 53, phase bit comparison loop and frequency comparison circuit are switched.Figure 28 (c) is the transition between states figure of state machine.

In Figure 28 (b), according to FQDRQ, FQDEN rises, and clock is restored phase locking circuit 200 be set at the FREQUENCY CONTROL pattern.In counter, when the number of NEDG1 surpassed regulation numerical value, the signal of CNEDG1 rose, and FQDEN is resetted, and PHDEN is risen, and clock is restored phase locking circuit 200 set phase bit comparison control model for.Figure 28 (c) represents the situation of this transition between states.

Figure 29 is the figure of the frequency change of the voltage-controlled oscillator 30 of expression from start to locking.Be initially the frequency comparison pattern, the fundamental frequency of voltage-controlled oscillator 30 (fvco) is controlled by frequency comparison circuit 50, the frequency (fo) of 1 code-element period (To) of progressive black-out intervals, and it is locked to enter capture range.Under the remarkable low situation, improve frequency with respect to fo at fvco every the time interval that timer 53 is set.When surpassing fo, when detecting NEDG=0, frequency reduces.At a time,, detect, when this number surpasses regulation numerical value, be judged as and enter in the capture range, transfer to phase control mode, by phase-comparison circuit 10 lockings by control circuit 70 when the NEDG=1 consecutive hours.

As described above, according to the present invention, only from serial data, just can extract reference clock out.Do not need in the past the consistent needed reference clock of frequency, and do not need to carry out the reverse transmission from the receiver side to the transmitter side yet until capture range.Therefore, can use simple and easy formation to constitute transfer system, can carry out low cost, the transmission of high-quality data.And so far illustrated function realizes that the unit is not to be used to limit the present invention, so long as can realize the unit of this function, any circuit or device also can, also can use software to realize the part of function.

And, as described above, be transmitted in when chrominance signal and synchronizing signal clearly distinguished according to the data of present embodiment, can carry out serial transfer, can reliably carry out clock at receiver side and extract out.And obtaining following excellent results is not need the interaction action of in the past carrying out between transmitting element and receiving element that utilizes training signal and confirmation signal.

And the serial digital data that can use a pair of distribution (comprising optical fiber) to carry out from the transmitting element to the receiving element according to the digital data transmission system of the present invention of present embodiment transmits.Under the situation that the present invention is applied to the optical fiber transmission, constitute: in transmitting element 2501, configuration E/O conversion element replaces output buffer 2506, electric serial signal is converted to the light serial signal, light signal is outputed to the light transmission path footpath, in receiving element 2521, configuration O/E conversion element replaces input buffer 2527, the light serial signal is converted to electric serial signal carry out subsequent treatment.In optical fiber transmits, comprise the cost height of per 1 transfer path of receive-transmit system.Therefore, under the situation that the present invention is used for the optical fiber transmission, do not need to carry out is the two-way communication of necessary, as to be used to carry out training signal, confirmation signal interaction in optical fiber transmits in the past, thereby does not need to increase the optical fiber radical, obtains significant cost degradation effect.

And, in data communication system according to present embodiment, be described as Hsync, the Vsync of the 2nd information and the example of CTRL transmitting in during the 2nd (black-out intervals), be not limited to Hsync, Vsync and CTRL yet the 2nd information that can be used as transmits, also can transmit the few information (for example voice data, Word message etc.) of the amount of information of comparing time per unit with the 1st information as the 2nd information.

And, according to the digital data transmission system of the present invention of present embodiment since in the clock extracting circuit of receiving element not needs from the clock input of quartz (controlled) oscillator or external oscillator, thereby obtain following effect and be, even the picture size of serial digital data changes, also can follow automatically, and also can tackle plug and play.

And, in the above-described embodiment, the execution mode of the rising edge that is conceived to serial data is described, yet,, also can implements the present invention the rising edge in the above-mentioned execution mode and trailing edge double replacement mutually even be conceived to trailing edge, can obtain same effect.

Embodiment 1

In the present embodiment, other example to the 1st coding circuit 2504a of illustrated in the above-described embodiment digital data transmission system of the present invention describes.In addition, about other formation, since identical with the described formation of above-mentioned execution mode, thereby omit explanation here.

With reference to Figure 30.Figure 30 is the figure of an example of the error in data that taken place when numerical data carried out serial transfer of expression.In data communication system of the present invention, owing to use a pair of distribution or cable to transmit serial digital data at a high speed, thereby under the situation that distribution length or cable length is prolonged grow distance to transmit, perhaps under the situation of the bad characteristic of distribution or cable, the waveform rust of numerical data takes place easily by ISI (Intersymbol Interference: the bit-errors that inter symbol interference) causes.This error in data as shown in figure 30, is carrying out after high level data transmits during of short duration, carries out under the situation that low-level data transmits performance significantly.Under the situation of carrying out data transmission shown in Figure 30, in the receiving element side, data waveform can not surpass threshold value, and error in data takes place.

Present inventors have carried out result of study to the problems referred to above, notice, and are discontinuous more than or equal to a fixed number by making with code data as shown in figure 31, can suppress the data waveform rust, can prevent error in data.

Therefore, present inventors are in order to address the above problem, and have developed in numerical data transmits, and can provide about the characteristic institute that is not subjected to distribution or cable, suppress the coding method of long distance transmission of the serial digital data of wrong generation.

With reference to Figure 32.Figure 32 represents the flow chart of the coding method among the 1st coding circuit 2504a of transmitter side unit of digital data transmission system of present embodiment.At first, import the 1st information D＜17:0〉(step S1).Then, using specific evaluation function, to the 1st information D＜17:0〉the same code consecutive numbers that carried out serialized serial data behind the coding carries out prediction and evaluation.In the present embodiment, suppose whether estimating (step S2) more than or equal to 11 with the code consecutive numbers.

Here, as the decision circuit of estimating, for example can use 4 AND circuit and 1 circuit that the NOR circuit has carried out combination shown in Figure 34.Carry out prediction and evaluation according to the serial data of this decision circuit after, switch, can be set at the same code consecutive numbers of serial data smaller or equal to 10 by carrying out coding mode described later to the serialization of the 1st information.In this decision circuit, the 1st information D＜17:0〉be divided into D＜8:0, D＜10:7 and D＜17:9 3 pieces judge.If the D＜10:7 of the central authorities of 1 code element〉4 be same code entirely, then En is " height ", if at D＜8:0〉and D＜17:9 in be " 1 " separately entirely, then En is " height ".Owing to use the D＜10:7 of central authorities〉whether 4 to carry out all being judgement with code, thereby under consecutive numbers is be evaluated as more than or equal to 11 situation,, can use the D＜10:7 of central authorities as described later by making per 2 bit reversals 4 reliably generate transition.In addition, in the present embodiment, by switching the coding mode in this decision circuit and the combinational logic circuit, the same code continuity of having carried out serialized serial data behind the coding is not more than equal 11 (serial digital data length 18 (position)/2+2=11), however the combination of the coding mode of decision circuit and combinational logic circuit is not limited to this.For example,, the coding mode of evaluation function and logical circuit is made up, so that be (n/2+2) with the code consecutive numbers if serial digital data length is the m position.

Stating bright evaluation function prediction and evaluation in the use is, the same code consecutive numbers that has carried out serialized serial data behind the coding is not more than under the situation that equals 11 (smaller or equal to 10), make bits of coded (En) be " height " as decision signal, carry out D＜17:0 the coding (step S3) of output same as before, coding is finished (step S5).On the other hand,, will make parallel input D＜17:0 making bits of coded (En) under the situation of " low " as decision signal〉in D＜15,14,11,10,7,6,3,2〉counter-rotating data are as dateout (step S4), coding is finished (step S6).Afterwards, serializer circuit 2502 is with parallel data D＜17:0 〉+En carries out serialization, sends to receiving element 2521 as serial digital data.In addition, when the data of serializer circuit 2502 after will encoding are carried out serialization,, give the position of rest of " low " at the end in the start bit that " height " given in the beginning of 1 code element of serial data.

Figure 33 represents the circuit diagram of the 1st coding circuit 2504a in the present embodiment.Parallel 18 input chromatic number is according to D＜17:0〉be imported into decision circuit 2504a-2 same as before.And, the input chromatic number according to D＜17:0 in D＜17,16,13,12,9,8,5,4,1,0〉be imported into an input of each XOR circuit 1, and the input chromatic number is according to D＜17:0〉in D＜15,14,11,10,7,6,3,2〉be imported into an input of each XOR circuit 2." low " is imported into another input of each XOR circuit 1, and is imported into another input of each XOR circuit 2 as the decision signal of the output of decision circuit.Each XOR circuit 2 is under the situation of " height ", with D＜15,14,11,10,7 at the decision signal of decision circuit 2504a-2,6,3,2〉output same as before is under the situation of " low " at the decision signal of decision circuit 2504a-2, makes D＜15,14,11,10,7,6,3,2〉each self reversal is exported.This decision signal also can be used as data and enables (En).Then, with the output of each XOR circuit 1 and the output addition of each XOR circuit 2, form 18 dateout.Above circuit according to the 1st coding circuit 2504a shown in Figure 33 constitutes, and can realize the coding of flow chart shown in Figure 32.

By using the coding method of present embodiment, can form with the discontinuous serial data of code data more than or equal to a fixed number.Therefore, desirable following effect, promptly, carried out serialized serial data by using this coding method to transmit, in the judgement of receiving digital signals, can suppress the influence of the data waveform rust that the characteristic etc. by transfer path causes, the result can improve data error rate.

Embodiment 2

Embodiment 2 is other examples of the coding method of illustrated in the above-described embodiment data communication system.In addition, about other formation, since identical with the described formation of above-mentioned execution mode, thereby omit explanation here.

In the present embodiment, the feature part is that transmitting element 2501 has the dc balance circuit, encodes, so that obtain the dc balance of serial data.Accumulative total of " height " (=1) of the data after this dc balance circuit will be encoded and the accumulative total of " low " (=0) are counted, and give evaluation function the signal feedback corresponding with this count number.This feedback makes evaluation function carry out the selection of coding mode, so that accumulative total of " height " (=1) of the data behind the coding and the accumulative total of " low " (=0) converge to identical number.The function of this dc balance circuit is called dc balance to be handled.

Here, with reference to Figure 35 the coding method in the data communication system of present embodiment is elaborated.Figure 35 represents the flow chart of the coding method in the present embodiment.

At first, judge that the DEI that is imported is " height " or " low " (step S1).Under the situation of DEI=" low ", (HsyncI, VsyncI and CTRLI) carries out pulse-width modulation (PWM) with the 2nd information, and the rising edge number of obtaining in 1 code element only exists 1 data structure (step S2), the end-of-encode of the 2nd information (step S3).

On the other hand, in step S1, under the situation of DEI=" height ", in that (the input chromatic number uses 1 pattern of activation to encode and during serialization according to (RI5～RI0, GI5～GI0, BI5～BI0)) with the 1st information, judge whether the rising edge number is 1 (step S4), be under 1 the situation, will import chromatic number at the rising edge number according to (RI5～RI0, GI5～GI0, BI5～BI0) use 2 patterns of activation to encode (step S5) finish the coding (step S6) of the 1st information.Here, 2 patterns that use to activate have been carried out coded data and have been imported into the dc balance circuit, and (step 10) is counted in the accumulation of the number of the number of " height " in these data and " low ".On the other hand, using 1 pattern of activation to encode and during serialization according to (RI5～RI0, GI5～GI0, BI5～BI0)) will importing chromatic number, is not under 1 the situation, to carry out the processing of step 7 at the rising edge number.

In step 7, to import chromatic number according to (RI5～RI0, GI5～GI0, BI5～BI0) use 2 patterns of activation to encode and during serialization, judge whether the rising edge number is 1 (step S7), be under 1 the situation at the rising edge number, to import chromatic number according to (RI5～RI0, GI5～GI0, BI5～BI0) use 1 pattern of activation to encode (step S8) finish the coding (step S9) of the 1st information.Here, 1 pattern that use to activate has been carried out coded data and has been imported into the dc balance circuit, and the dc balance circuit just accumulation of the number of the number of " height " in these data and " low " is counted (step 10).On the other hand, will import chromatic number according to (RI5～RI0, GI5～GI0, BI5～BI0) use 2 patterns of activation to encode and during serialization, at the rising edge number are not under 1 the situation, to carry out the processing of step S11.

In step S11, evaluation function according to the rules selects to be to use 1 pattern of activation to encode (step S8) to use activating 1 pattern or which kind of pattern in 2 patterns of activating is encoded and estimated, and also is to use 2 patterns of activation encode (step S5).Use selected coding mode, carry out the coding of the 1st information, the coding of the 1st information is finished (step S9 or step S6).At step S11, the cumulative number of " height " the data after encoding and the cumulative number of " low " are input to this evaluation function from the dc balance circuit.Evaluation function selects to be to use 1 pattern of activation to encode, and also is to use 2 patterns of activation to encode, so that the accumulative total of the accumulative total of " height " of the data behind coding number and " low " number converges to number.In addition, at step S11, even in which kind of pattern that use to activate 1 pattern or activate in 2 patterns the 1st information has been carried out under the situation of coding, also the serial data (the rising edge number is 1) with the situation of DEI=" low " is not identical.

More than, cumulative number of the cumulative number of " height " of the data of dc balance circuit after with the coding of the 1st information and " low " number is counted, yet the dc balance circuit also can be to the data behind the coding of the 1st information not only, and comprise in start bit and position of rest and the En position either party at least cumulative number is counted.In the case, in serializer circuit, because start bit and position of rest and En position are predetermined to being " height " or " low ", thereby the dc balance circuit is by storing these information in advance, can comprise start bit and position of rest and the En position is counted cumulative number.And, preferably the data behind the coding of the 2nd information are input to the dc balance circuit, also comprise the start bit of 1 code element of data behind the coding of the 2nd information and the 2nd information and position of rest etc., the cumulative number of " height " and the cumulative number of " low " number are counted, obtained the dc balance of serial data 2515 integral body of institute's serial transfer.

By carrying out above encoding process, the serial data by the data encoded structure under the situation of the situation of DEI=" low " and DEI=" height " can clearly be distinguished: be that the rising edge number is 1 (situation of DEI=" low "), or the rising edge number is more than or equal to 2 (situations of DEI=" height ").

And, by carrying out above processing, as the input chromatic number of the 1st information of parallel input according to 2511 and be encoded as the input synchrodata 2512 of the 2nd information after carry out serialization, be sent to receiving element 2521 as serial data 2515 from transmitting element 2501.According to present embodiment, handle owing to carry out dc balance, so that the cumulative number of the cumulative number of " height " of serial data 2515 and " low " converges to number together, thereby can keep the dc balance of serial data 2515.

In receiving element 2521, the serial data of being imported 2515 is imported into decoding circuit 2524 by 2522 parallelizations of parallelization circuit.About the action of receiving element 2521, since identical with above-mentioned execution mode, thereby omit explanation here.

As described abovely like that by using, when chrominance signal and synchronizing signal are clearly distinguished, can carry out serial transfer, can reliably carry out clock at receiver side and extract out according to coding method in the digital data transmission system of present embodiment and coding/decoding method.

And the serial digital data that the data communication system of present embodiment can use a pair of distribution (comprising optical fiber) to carry out from the transmitting element to the receiving element transmits.And obtaining following excellent results is owing to the interaction action that utilizes training signal and confirmation signal that does not need to carry out between transmitting element and receiving element in the past, thereby can adopt simple formation to come the composition data transfer system.Particularly, be applied under the situation that optical fiber transmits, because the not pattern of wants needed intercommunication system when training signal and confirmation signal interactive, thereby can make significantly cost degradation of system.

And, can be in the middle low data (voice data etc.) of transmission frequency of black-out intervals (Hsync, Vsync usually) according to the digital data transmission system of the present invention of present embodiment.

And, according to the data communication system of present embodiment in the clock extracting circuit of receiving element not needs can from serial digital data, reliably extract clock out from the clock input of quartz (controlled) oscillator or external oscillator.Therefore, obtain following effect and be, can tackle the different transfer rates of data, for example the different images size in the view data according to different transfer rates reliable clock of extracting out from these data of data, also can be tackled plug and play etc.

Embodiment 3

Embodiment 3 is other examples that the clock in the data communication system of above-mentioned execution mode restores phase locking circuit (clock extracting circuit).

With reference to Figure 36.Figure 36 is the circuit formation of phase locking circuit (clock extracting circuit) 2600 is restored in expression as the clock of a receiving circuit of the present invention hardware block diagram.The clock extracting circuit 2600 of present embodiment is the clock extracting circuit that also has fine setting frequency comparison circuit 80 in the illustrated in the above-described embodiment clock extracting circuit 2523.In addition, about with above-mentioned execution mode in the illustrated identical inscape of inscape, omit explanation here.

The clock of present embodiment restores phase locking circuit 2600 and has fine setting frequency comparison circuit 80, in the frequency adjustment (frequency rough adjustment) of having carried out voltage-controlled oscillator 30 by frequency comparison circuit 50 afterwards, in the frequency adjustment (phase place adjustment) of carrying out voltage-controlled oscillator 30 by phase-comparison circuit 10 before, carry out the thinner frequency adjustment (frequency trim is whole) of voltage-controlled oscillator 30 by fine setting frequency comparison circuit 80, thereby the fine tuning of oscillating frequency that can carry out voltage control oscillating circuit 30 is whole, after frequency of oscillation in frequency comparison circuit 50 is adjusted, compare with the situation of using phase-comparison circuit 10 to carry out the frequency of oscillation adjustment same as before, can shorten the convergence time of frequency of oscillation.

With reference to Figure 37.Figure 37 represents the circuit block diagram of the fine setting frequency comparison circuit 80 in the present embodiment.Fine setting frequency comparison circuit 80 has along extracting circuit 80a, initial/as to stop to infer circuit 80b and frequency detection circuit 80c.

Sampler (sampling circuit) 40 uses the sampling pulse that is generated at voltage control oscillating circuit 30, will sample from the serial data 300 that transmitting element sent, and generates parallel data 301 (Deserialized Data).As shown in figure 37, parallel data 301 at first be imported into the fine setting frequency comparison circuit 80 along extracting circuit 80a., generate according to the parallel data of being imported 301 along extracting circuit 80a along sign (Edge Flag) 80d.Here, exist edge sign (Edge Flag) 80d between the position of rising edge to become high level.Then, along extracting circuit 80 initial outputing to along sign (Edge Flag)/stop to infer circuit 80b.Initial/stop to infer circuit 80b according to imported along sign (Edge Flag) 80d, generates initial/stop to indicate (Start/StopFlag) 80e, output to frequency detection circuit 80c.Frequency detection circuit 80c according to imported initial/stop the sign (Start/Stop Flag) 80e, the deviation of the frequency in the frequency of the oscillator signal of detection voltage control oscillating circuit 30 and the rising edge cycle of the serial data in 1 code element outputs to voltage control oscillating circuit 30 to the control signal corresponding with this frequency departure by charge pump 60b and loop filter 20.

Here, Figure 38 represents that the generating along the situation of sign (Edge Flag) 80d and along the circuit of extracting circuit 80a along extracting circuit 80a of fine setting frequency comparison circuit 80 of present embodiment constitutes.Figure 38 represents the corresponding relation of serial data 300 and parallel data 301 (Deserialized Data＜0 〉～＜20 〉).In addition, the final data (Privious Deserialized Data＜20 〉) that the serial data 300 of last 1 code element has been carried out parallelization also is imported into along extracting circuit 80a with the parallel data 301 of the serial data 300 of current 1 code element having been carried out parallelization (Deserialized Data＜0 〉～＜20 〉).

As shown in figure 38, the parallel data 301 of being sampled by sampler 40 is imported into each the AND circuit that constitutes along extracting circuit 80a., generate according to the parallel data of being imported 301 along extracting circuit 80a along sign (Edge Flag＜0 〉～＜20 〉) 80d.Corresponding with the border of start bit (Start) and position of rest (Stop) at this along existing among sign (Edge Flag＜0 〉～＜the 20 〉) 80d, have data " height " initial/stop to indicate (Start/Stop Flag).

Being imported into along sign (Edge Flag＜0 〉～＜20 〉) 80d of being generated be initial/stop to infer circuit 80b.Figure 39 represent in the present embodiment initial/stop to infer that the circuit of circuit 80b constitutes.Initial/as to stop to infer that circuit 80b has AND circuit 80b-1, flip-flop circuit 80b-2 and OR circuit 80b-3.Initial/stop to infer circuit 80b from along infer sign (Edge Flag＜0 〉～＜the 20 〉) 80d be equivalent to initial/stop sign (Start/Stop Flag) along sign.

Initial/stop to infer among the circuit 80b, when the frequency of the frequency of the oscillator signal of voltage control oscillating circuit 30 and serial data 300 is identical, always be in along sign initial/stop the position of sign (Start/Stop Flag).And, when both frequencies depart from a little, initial/stop the sign (Start/Stop Flag) the position little by little depart from.Therefore, will be last time the front and back numerical digit of estimation result of (before 1 code element) as existing the initial/position that stops sign (Start/Stop Flag) in current 1 code element to carry out mask, by obtain with when forward position sign (EdgeFlag＜0 〉～＜20 〉) " with " (AND), can infer residing be current initial/stop the position of sign (Start/Stop Flag), promptly initial/as to stop which sign in the sign (Start/Stop Flag＜0 〉～＜20 〉).

Here, with reference to Figure 40, the circuit of frequency detection circuit 80c is constituted and action describes.By initial/to stop to infer that circuit 80b generated initial/stop sign (Start/StopFlag＜0 〉～＜20 〉) to be imported into frequency detection circuit 80c.Frequency detection circuit 80c have flip-flop circuit 80c-1 and with AND circuit ([0,0)～[20,20]) constitute rectangular circuit 80c-2,80c-3 and 80c-4.

Frequency detection circuit 80c according to imported initial/stop sign (Start/StopFlag＜0 〉～＜20 〉), detect frequency poor of the frequency of oscillator signal of voltage control oscillating circuit 30 and serial data 300.Frequency detection circuit 80c adopts and followingly to constitute: will use that parallel data 301 before 1 code element that is kept by flip-flop circuit 80c-1 generated initial/stop sign (Start/Stop Flag＜0 〉～＜20 〉) and use that the parallel data 301 of current 1 code element generated initial/stop to indicate that (Start/Stop Flag＜0 〉～＜20 〉) compares by AND circuit 80c-2,80c-3 and 80c-4, detect sign residing initial/stop the mark position, by indicate residing initial/position of rest move the difference on the frequency that detects both.Specifically, under the situation of mark position by AND circuit 80c-2 detection, (a) because sign moves to the back of code element, thereby the frequency height of the frequency ratio serial data 300 of the oscillator signal of voltage control oscillating circuit 30, the control signal that frequency of oscillation is reduced is sent to voltage control oscillating circuit 30.And, under the situation of mark position by AND circuit 80c-3 detection, (b) because the position consistency of sign, thereby the frequency of the oscillator signal of voltage control oscillating circuit 30 is consistent with the frequency of serial data 300, phase place comparison of request signal (FFQDEN) is outputed to control circuit 70, control circuit 70 receives this FFQDEN, signal (PHDEN) is enabled in the phase bit comparison outputed to phase-comparison circuit 10, makes phase bit comparison loop carry out function.And, under the situation of mark position by AND circuit 80c-4 detection, (c) because sign moves to the front of code element, thereby the frequency of the frequency ratio serial data 300 of the oscillator signal of voltage control oscillating circuit 30 is low, and the control signal that frequency of oscillation is raise is sent to voltage control oscillating circuit 30.Here, the control signal of frequency detection circuit 80c output is following signal, that is: as shown in figure 37, fast and slow output as frequency detection circuit 80c, (a) under the high situation of the frequency of the frequency ratio serial data 300 of the oscillator signal of voltage control oscillating circuit 30, being set at " low " soon, being set at " height " slowly, (b) under the frequency of the oscillator signal of voltage control oscillating circuit 30 situation consistent with the frequency of serial data 300, being set at " low " soon, being set at " low " slowly, (c) under the low situation of the frequency of the frequency ratio serial data 300 of the oscillator signal of voltage control oscillating circuit 30, being set at " height " soon, being set at " low " slowly.

By repeating a series of actions of this sampler 40, fine setting frequency comparison circuit 80, charge pump 60b, loop filter 20 and voltage control oscillating circuit 30, can carry out the output signal frequency inching of voltage control oscillating circuit 30.Then, after the frequency of oscillation of voltage control oscillating circuit 30 has entered the capture range of regulation, use phase-comparison circuit 10 to carry out the phase place adjustment of the frequency of oscillation of voltage control oscillating circuit 30.

As described above, clock extracting circuit according to present embodiment, can carry out the output signal frequency inching of voltage control oscillating circuit 30, after the frequency rough of carrying out the frequency of oscillation of voltage control oscillating circuit 30 at the frequency of utilization comparison circuit is adjusted, compare with the situation of phase place adjustment of using phase-comparison circuit 10 to carry out the frequency of oscillation of voltage control oscillating circuit 30 same as before, can shorten the convergence time of the frequency of oscillation of voltage control oscillating circuit 30.And so far illustrated function realizes that the unit is not to be used for the present invention is limited, so long as can realize the unit of this function, any circuit or device can, also can use software to realize the part of function.

Embodiment 4

Embodiment 4 is other examples that adopted the coding method of the data communication system of the present invention that the dc balance of the foregoing description 2 handles.In addition, about other formation, since identical with the above-described embodiment and examples 2 described formations, thereby omit explanation here.

Figure 41 represents the transmitting element 3000 of the data communication system of present embodiment.Transmitting element 3000 has CRD testing circuit 3001.Here, CRD (Current Running Disparity: the value of the difference of 1 (" height ") the data after being encoded of this moment that current operation deviation) to be expression send out from transtation mission circuit and the number (cumulative number) of 0 (" low ").CRD testing circuit 3001 after according to the coding of the 1st input information data and the data behind the coding of the 2nd input information, this CRD of computing, according to the value output CDR signal of the CRD of institute's computing, this CDR signal is controlled to the coding of the 1st coding circuit 2504a and the 2nd coding circuit 2504b the absolute value of CRD is reduced.Below, input is described as 8 * 3=24 position of the 1st input information 2511 with as 3 situations of carrying out serial dataization of the 2nd input information 2512.

Figure 42 represents that the circuit of CRD testing circuit 3001 constitutes.CRD testing circuit 3001 is made of nonuniformity testing circuit 3001a, adder 3001b and trigger 3001c.Nonuniformity testing circuit 3001a output 1 data number from 30 bit data that switching circuit 2505 is exported deducts the value of 0 data number.Carry out breech lock by every clock at trigger 3001c with remaining on the value of CRD of trigger 3001c and the value of output valve after adder 3001b addition of nonuniformity testing circuit 3001a, thereby CRD is upgraded.

Below with reference to Figure 43.Figure 43 represents other example of the 1st coding circuit 2504a in the present embodiment.The 1st coding circuit 2504a ' shown in Figure 43 constitutes to 38B/10B coding circuit 2504a '-1,2504a '-2 and 2504a '-3 and the 1st and the 2nd nonuniformity testing circuit 2504a '-4 and 2504a '-5 by the 1st.

8B/10B coding circuit 2504a '-1,2504a '-2 and 2504a '-3 convert the input of 8bit to 10bit separately, so that be at the deviation code of being imported+situation under, make 0 number more than 1 numbers, at the deviation code be-situation under, the data number that makes 1 data is more than the data number of 0 data.In addition, convert to output 10bit in rising edge is necessarily arranged.

18B/10B coding circuit 2504a '-1 obtains D＜23:16 〉, D＜23:16〉convert ENCD＜29:20 to〉export, so that be at the CRD code+situation under, 1 the data number of the 10bit of output is lacked than 0 number, at the CRD code be-situation under, make 1 data number more than 0 data number.

The 1st nonuniformity testing circuit 2504a '-4 detects ENCD＜29:20〉deviation.Adder 2504a '-6 exports the output addition of CRD and the 1st nonuniformity testing circuit 2504a '-4 as CRD1.

28B/10B coding circuit 2504a '-2 obtains D＜15:8 〉, D＜15:8〉convert ENCD＜19:10 to〉export, so that be at the CRD1 code+situation under, 1 the data number of the 10bit of output is lacked than 0 number, at the CRD code be-situation under, make 1 data number more than 0 data number.

The 2nd nonuniformity testing circuit 2504a '-5 detects ENCD＜19:10〉deviation.Adder 2504a '-7 exports the output addition of CRD1 and the 2nd nonuniformity testing circuit 2504a '-5 as CRD2.

38B/10B coding circuit 2504a '-3 obtains D＜7:0 〉, according to CRD2 code and the above-mentioned the same ENCD of converting to＜9:0〉export.

By more than, the 1st coding circuit 2504a ' with the input 24bit encode so that the absolute value of CRD reduces.

The 2nd coding circuit 2504b constitutes: can carry out 2 kinds of different codings of pulsewidth (" height "=1 consecutive numbers) when having carried out serialization at a kind of input data.The 2nd coding circuit 2504b encodes the 2nd input information so that be at the CRD code+situation under, pulsewidth is reduced, that is, 1 data number is lacked than 0 data number, at CRD be-situation under, pulsewidth is increased.The input/output relation of the 2nd coding circuit 2504b for example as shown in the following Table 1.

[table 1]

Input	CRD	The output of the 2nd encoder
			000	-	11_1111_1111_1111_1100_0000_0000_0000
+	11_1111_1111_1111_0000_0000_0000_0000
		001		-	11_1111_1111_1111_1110_0000_0000_0000
+	11_1111_1111_1110_0000_0000_0000_0000
			010	-	11_1111_1111_1111_1111_0000_0000_0000
+	11_1111_1111_1100_0000_0000_0000_0000
		011		-	11_1111_1111_1111_1111_1000_0000_0000
+	11_1111_1111_1000_0000_0000_0000_0000
			100	-	11_1111_1111_1111_1111_1100_0000_0000
+	11_1111_1111_0000_0000_0000_0000_0000
		101		-	11_1111_1111_1111_1111_1110_0000_0000
+	11_1111_1110_0000_0000_0000_0000_0000
			110	-	11_1111_1111_1111_1111_1111_0000_0000
+	11_1111_1100_0000_0000_0000_0000_0000
		111		-	11_1111_1111_1111_1111_1111_1000_0000
+	11_1111_1000_0000_0000_0000_0000_0000

Figure 68 and Figure 69 represent to have carried out the waveform example 1 to 3 of the serial data after the serialization of situation of this coding separately.

The waveform example 1 of Figure 68 is under the situation of DEI (switching signal)=1 (height), the 1st information be 3 pieces of the 10bit behind the coding of 8B/10B at its beginning and end with the form of initial/position of rest, be the code element of 32 of totals.Under the situation of DEI (switching signal)=0 (low), the 2nd information becomes the pulse-width signal of 32 bit periods by the coding of having obtained above-mentioned dc balance.

The waveform example 2 of Figure 69 (A) is to have omitted the waveform of initial/position of rest of the situation of the DEI (switching signal)=1 in the waveform example 1.In the case, the 1st information is 30 code element.Under the situation of DEI (switching signal)=0, the 2nd information is the pulse-width signal of 30 bit periods.

The waveform example 3 of Figure 69 (B) is in the variation of waveform example 2, makes the pulse-width modulation of 10 bit periods line up 3 waveforms that are listed as under the situation of DEI (switching signal)=0.In the case, also obtain dc balance.

The input terminal of above serial data waveform example by change illustrated switching circuit 2505 in execution mode and the annexation of the lead-out terminal of encoder can realize separately.

As mentioned above,, the 1st input information can be encoded into the absolute value of CRD is reduced, promptly obtain dc balance according to the transmitting element 3000 of present embodiment.And, the 2nd input information can be encoded into the pulse-width signal of obtaining dc balance.

In the receiving circuit of the output of the reception transmitting element of present embodiment, the 1st decoding circuit carries out the corresponding decoding of coding with the 1st coding circuit of above-mentioned present embodiment, the 2nd decoding circuit carries out the corresponding decoding of coding with the 2nd coding circuit of above-mentioned present embodiment, thereby the 1st input information and the 2nd input information are restored.

Embodiment 5

Embodiment 5 is the embodiment that adopt the data structure that in 1 code element the DEI data is embedded same as before.Use Figure 44 (A) and (B) to describing according to the numerical data transtation mission circuit of present embodiment and receiving circuit and digital data transmission method and system concept thereof.Figure 44 (A) and (B) be illustrated in digital data transmission method of the present invention and the system thereof is with the input chromatic number digital data of parallel input (RI5～RI0, GI5～GI0, BI5～BI0): be also referred to as input chromatic number digital data group or main information.), input synchrodata (HsyncI (input level synchrodata), VsyncI (input vertical synchronization data), CTRLI (input control): be also referred to as the synchrodata group or from information) and DEI (input select signal (the input data are enabled) has carried out the signal waveform example of serialized serial data 300.In addition, here, about constituting the chromatic number certificate of serial data, each 6 naturally of expression RGB data of all kinds (example of RI5～RI0, GI5～GI0, BI5～BI0), however the present invention is not limited to this certainly.

At first, at DEI (data are enabled)=" height " is between active period, 1 code element of serial data 300 by enable according to start bit (Start), data reverse signal (DEIn), chromatic number according to (RI5, RI4 ..., BI2, BI1, BI0) and the order of position of rest (Stop) carried out serialized data and constituted.

On the other hand, DEI (data are enabled)=" low " is black-out intervals, and 1 code element of serial data 300 has been carried out serialized data by the order of enabling reverse signal (DEIn), coded HsyncI, VsyncI and CTRLI and position of rest (Stop) according to start bit (Start), data and constituted.At DEI=" low " is black-out intervals, with carrying out serialization behind HsyncI, VsyncI and the CTRLI coding, obtains the data structure that only has 1 rising edge in 1 code element in serial data 300.Specifically, HsyncI, VsyncI and CTRLI are encoded, and then by coding circuit output, make and carry out the level ratio LSB height of MSB serialization by serializer circuit from MSB to the LSB order and export.Therefore, these data under the low situation of DEI since in 1 code element the output time of serializer circuit early be high level, thereby generation rising edge when code element is switched only.

By adopting this formation,, can fully reduce the possibility that makes a mistake from when the serial data that comprises synchrodata that black-out intervals sent is restored clock.

With reference to Figure 45 to Figure 50 one execution mode of numerical data transtation mission circuit of the present invention and receiving circuit and digital data transmission method and system thereof is described.

At first, with reference to Figure 45.Figure 45 represents numerical data transtation mission circuit of the present invention and receiving circuit and uses their digital data transmission method and an execution mode of digital data transmission system.

(carried out serialized serial data 415 and sent to receiving element 421 according to 411 by RI5～RI0, GI5～GI0, BI5～BI0) and input synchrodata 412 (HsyncI (input level synchrodata), VsyncI (input vertical synchronization data), CTRLI (input control) and DEI (input select signal (the input data are enabled))) importing chromatic number for transmitting element (transtation mission circuit) 401.

Receiving element (receiving circuit) 421 receives the serial data 415 that is sent from transmitting element 401, carry out parallelization, ((HsyncO (output horizontal synchronization data), VsyncO (output vertical synchronization data), (output selects signal (dateout is enabled) and output clock 434 to export for CTRLO (output control), DEO for RO5～RO0, GO5～GO0, BO5～BO0), output synchrodata 432 according to 431 to be recovered to the output chromatic number.

Transmitting element 401 has: serializer circuit 402 (Serializer), phase locking circuit 403 (PLL circuit: Phase Locked Loop (phase-locked loop) circuit), coding circuit 404 (Encoder), switching circuit 405 and output buffer 406 (Output Buffer).

And, receiver unit 421 has: parallelization circuit 422 (De-serializer), clock extracting circuit (CDRPLL circuit: Clock Data Recovery Phase Locked Loop (clock data recovery phase-locked loop) circuit) 423, decoding circuit 424 (Decoder), switching circuit 425 and 426 and input buffer 427 (Input Buffer).In addition, output buffer 406 and input buffer 427 can be provided with as required.And, in the present embodiment, about the input chromatic number according to 411, each example of 6 naturally of expression RGB data of all kinds, however the present invention is not limited to this certainly.And, also decoding circuit 424 (Decoder) and switching circuit 425 and 426 are referred to as the information separated circuit sometimes.

In transmitting element 401, the input chromatic number is imported into switching circuit 405 according to 411.HSYNCI, VSYNCI and CTRLI in the input synchrodata 412 except DEI are imported into coding circuit 404, by coding circuit 404 codings.Switching circuit 405 as input select signal, when DEI height (High), selects DEI the input chromatic number according to 411, under low situation, selects the output of coding circuit 404, outputs to serializer circuit 402.Input clock 414 is converted into multi-phase clock at phase locking circuit 403, and serializer circuit 402 uses this multi-phase clock that serialization is carried out in the output of switching circuit 405 and the reverse signal of DEI, exports by output buffer 406.

In transmitting element 401, if coding HSYNCI, VSYNCI and CTRLI, when having carried out serialization in 1 code element in time first signal sets be MSB, then be output into the level ratio LSB height of MSB, carry out serialization by serializer circuit 402 from MSB to the LSB order and export by coding circuit.Therefore, these data under the low situation of DEI since in 1 code element the output of serializer circuit in time early be high level, thereby generation rising edge when code element is switched only.

In receiving element 421, at first, clock extracting circuit 423 restores output clock (CLKO) 434 and multi-phase clock from serial data 415.Then, use multi-phase clock to convert serial data 415 to parallel signal at parallelization circuit 422.The reverse signal that includes the DEI signal in the parallel signal.Parallel signal except DEI is imported into decoding circuit 424 and decodes.Switching circuit 425 is activation when DEI is high, (RO5～RO0, GO5～GO0, BO5～BO0) export export low level when DEI is low as output chromatic number certificate as output chromatic number certificate parallel signal.Switching circuit 426 for activating, is exported the output of decoding circuit 424 when DEI is low as the output synchrodata, keep output when DEI is high.

Below with reference to Figure 46.Figure 46 (A) and (B) each input chromatic number of 6 of the parallel input of expression according to (RI5～RI0, GI5～GI0, BI5～BI0), input synchrodata (HsyncI (input level synchrodata), VsyncI (input vertical synchronization data), CTRLI (input control) and DEI (input select signal (the input data are enabled))) are carried out the signal waveform example of serialized serial data 415 in the receiver side unit of present embodiment.

At first, at DEI (data are enabled)=" height " is between active period, 1 code element of serial data 415 by enable according to start bit (Start), data reverse signal (DEIn), chromatic number according to (RI5, RI4 ..., BI2, BI1, BI0) and the order of position of rest (Stop) carried out serialized data and constituted.In addition, in the present embodiment, 1 code element is 21.

On the other hand; DEI (data are enabled)=" low " is black-out intervals, and reverse signal (DEIn), data are enabled guard bit (DE grd), coded HsyncI, VsyncI and CTRLI to 1 code element of serial data 415 by enabling according to start bit (Start), data, the order that stops guard bit (Stop grd) and position of rest (Stop) has been carried out serialized data and constituted.At DEI=" low " is black-out intervals, and HsyncI, VsyncI and CTRLI carry out serialization after being encoded, and adopts the data structure that only has 1 rising edge in 1 code element in serial data 415.In addition, when DEI=" low ",, will import synchrodata and carry out pulse-width modulation according to the n doubling time of the pulsewidth of the numerical data that constitutes input chromatic number certificate.

As present embodiment,,, can fully reduce the possibility that makes a mistake from when the serial data that comprises synchrodata that black-out intervals sent is restored clock by adopting the data structure that in 1 code element, only has 1 rising edge.

And, in present embodiment shown in Figure 46, data are set after data are enabled reverse signal (DEIn) enable guard bit (DE grd).By being set, these data enable guard bit (DE grd); high accuracy is extracted out in the data that become return contact when serial data 415 is restored parallel data and clock and is enabled reverse signal (DEIn), thereby can reduce the possibility of the errors of sampling that synchrodata and clock take place.

With reference to Figure 47.Figure 47 represents the formation of the transmitting element 401 in the present embodiment.Coding circuit 404 has 4 NAND circuit, 4 NOR circuit and 3 inverter circuits.Switching circuit 405 have with the input chromatic number according to 411 (RI5～RI0, GI5～GI0, BI5～BI0) multiplexer 4051 and the inverter 4052 of corresponding number (18).In addition, in the present embodiment, be 7 from the output of coding circuit 404,2 in the multiplexer 4051 are transfused to " height " signal are arranged, and 2 be transfused to " low " signal is arranged, and form and stop guard bit.Figure 51 represents not to be provided with the example that stops guard bit.

Hsync, Vsync and CTRLI are imported into coding circuit 404.The Hsync that is imported, Vsync and CTRLI are by coding circuit 404 codings, and 7 coded bit data are output to switching circuit 405.

Here, with reference to Figure 48 (A) with (B) action of coding circuit 404 is described.The circuit of the coding circuit 404 of Figure 48 (A) expression present embodiment constitutes and 7 output (SYNC[0]～SYNC[6]).And Figure 48 (B) expression is input to the tables of data of Hsync, the Vsync of coding circuit 404 of present embodiment and CTRLI and dateout thereof (SYNC[0]～SYNC[6]).

Shown in the tables of data of Figure 48 (B), has when having imported data Hsync, Vsync and CTRLI the form that the transition number is restricted from the dateout of coding circuit 404 (SYNC[0]～SYNC[6]).In other words, being HsyncI with upper (MSB), being that 3 bit data of CTRLI are { when Hsync, Vsync, CTRLI} are encoded into 7 bit data { SYNC[0] (upper)～SYNC[6] (the most the next) } with the most the next (LSB), be encoded into: the every increase by 1 of this 3 bit data, just export " height " data continuously from the upper order of this 7 bit data.In other words, be encoded into output and in 7 bit data { SYNC[0] (upper)～SYNC[6] (the most the next) }, go up place value always more than or equal to the data of place value down.This way of output is commonly referred to as " Thermo-Code ", and this coding is called as " Thermo-Code " type coding, and this encoder is called as " Thermo-Code " type encoder.

Coding circuit 404 in digital data transmission method of the present invention and the digital data transmission system needs to adopt the Thermo-Code type way of output.In addition, the circuit formation about coding circuit 404 is not limited to the circuit shown in Figure 48 (A) and constitutes, so long as adopt the circuit of the Thermo-Code type way of output to constitute, can adopt any circuit to constitute.Like this, in 1 code element, only generate 1 rising edge.

Here, referring again to Figure 47.Be imported into switching circuit 405 from dateout of coding circuit 404 (SYNC[0]～SYNC[6]) and DEI (the input data are enabled).In the present embodiment, (RI5～RI0, GI5～GI0, BI5～BI0) order is imported into the multiplexer that is connected in parallel 4051 that constitutes switching circuit 405 to the input chromatic number according to 411, " height " is imported into input input chromatic number another input according to the switching circuit 4051 of RI5 in 411 and RI4, and " low " is imported into another input that input has the switching circuit 4051 of BI1 and BI0.And DEI is imported into input input chromatic number another input according to the switching circuit 4051 of the RI5 in 411.According to 411 and from the dateout of coding circuit 404 (SYNC[0]～SYNC[6]), (SR1～SR19) outputs to serializer circuit 402 to switching circuit 405 data according to the DEI that is imported, input chromatic number.

Phase locking circuit 403 forms the different a plurality of clocks of phase place according to input clock 414, outputs to serializer circuit.

Serializer circuit 402 is according to the different a plurality of clocks of being imported from phase locking circuit 403 of phase place, and (SR1～SR19) carry out serialization forms serial data 415, outputs to receiving element 421 by output buffer 406 with the data imported.

Figure 49 represents the formation of the receiving element 421 of present embodiment.The serial data of being exported from transmitting element 401 415 is imported into parallelization circuit 422 and clock extracting circuit 423 by input buffer 427.Clock extracting circuit 423 is extracted clock out from serial data 415, restore the output clock 434 a plurality of clocks different with phase place.Parallelization circuit 422 carries out parallelization according to the different a plurality of clocks of phase place that restored by clock extracting circuit 423 with serial data 415, and (DSR0～DSR20) outputs to decoding circuit 424 and switching circuit 425 and 426 dateout.(data (in the present embodiment, DSR4, DSR6, DSR8, DSR10, DSR12, DSR14, DSR16) corresponding with synchrodata are imported into decoding circuit 424 to dateout among the DSR0～DSR20).Decoding circuit 424 is decoded the data of being imported, and the data corresponding with output synchrodata 432 (HsyncO, VsyncO, CTRLO) are outputed to switching circuit 426.

Here, Figure 50 represents that the circuit of the decoding circuit 424 of present embodiment constitutes.The decoding circuit 424 of present embodiment has 12 NOR circuit, 1 NAND circuit and 2 inverter circuits.In addition, decoding circuit can adopt the circuit that the synchronizing signal after " Thermo-code " change is decoded to constitute, and is not limited to circuit shown in Figure 50 and constitutes.

Referring again to Figure 49.Switching circuit 425 with 426 according to the different a plurality of clocks of phase place imported from clock extracting circuit 423, select the data imported from parallelization circuit 422 and decoding circuit 424, output to flip-flop circuit 428.Flip-flop circuit 428 is made of 22 triggers 4271, and output output chromatic number is according to (RO5～RO0, GO5～GO0, BO5～BO0), output synchrodata 432 (HsyncO, VsyncO, CTRLO) and EDO.

Like this, the input chromatic number of parallel input according to 411, input synchrodata 412 and input clock 414 undertaken sending after the serialization by transmitting element 401, carry out parallelization at receiving element, be recovered to the output chromatic number according to 431, output synchrodata 432 and output clock 434, and with they output.

According to present embodiment, because at black-out intervals, the rising edge number of per 1 code element of serial data is fixed to 1, thereby can be implemented in the minimizing of the mistake that is caused by the waveform deterioration when extracting clock out from serial data, can realize that stable data transmits.

In addition, shown in Figure 52, transmitting element 401 can have the 1st coding circuit 404a and the 2nd coding circuit 404b, can be input to the 1st coding circuit 404a to the input chromatic number according to 411, and input synchrodata 412 is input to the 2nd coding circuit 404b.In the present embodiment, the input chromatic number can be imported into switching circuit 405 by the 1st coding circuit 404a coding according to 411.

Embodiment 6

Embodiment 6 makes the input chromatic number according to being that 6 embodiment 5 is applied to import chromatic number according to being the embodiment of 8 situation.

Figure 53 (A) and (B) each input chromatic number of 8 of the parallel input of expression in the present embodiment according to ((input select signal (the input data are enabled) has carried out the signal waveform example of serialized serial data 1001 in the receiver side unit for RI7～RI0, GI7～GI0, BI7～BI0), synchrodata (HsyncI (input level synchrodata), VsyncI (input vertical synchronization data), CTRLI (input control)) and DEI.

At first; at DEI (data are enabled)=" height " is between active period, 1 code element of serial data 1001 by enable according to start bit (Start), data reverse signal (DEIn), chromatic number according to (RI7, RI6 ..., BI2, BI1, BI0), the order that stops guard bit (Stop grd) and position of rest (Stop) carried out serialized data and constituted.In addition, in the present embodiment, 1 code element is 28.

On the other hand; DEI (data are enabled)=" low " is black-out intervals, and reverse signal (DEIn), data are enabled guard bit (DE grd), coded HsyncI, VsyncI and CTRLI to 1 code element of serial data 1001 by enabling according to start bit (Start), data, the order that stops guard bit (Stop grd) and position of rest (Stop) has been carried out serialized data and constituted.Here, be black-out intervals at DEI=" low ", HsyncI, VsyncI and CTRLI carry out serialization after being encoded, obtain the data structure that only has 1 rising edge in 1 code element in serial data 1001.

As present embodiment,,, can fully reduce the possibility that makes a mistake from when the serial data that comprises synchrodata that black-out intervals sent is restored clock by adopting the data structure that in 1 code element, only has 1 rising edge.

Embodiment 7

Embodiment 7 is the examples that also are provided with DE filter 1101 and flip-flop circuit 1102 in the illustrated receiving element of the present invention 421 shown in Figure 45 of the foregoing description 5.

Figure 54 represents the circuit block diagram of the receiving element of present embodiment.In the present embodiment, (the output DSR1 corresponding with DEI is input to DE filter 1101 DSR0～DSR20) the data of being exported from parallelization circuit 422.

Use Figure 55 that the effect of DE filter 1101 is described.The circuit of Figure 55 (A) expression DE filter 1101 constitutes, the sequential chart of the data (DE0, DE1, DE2, DE0) in Figure 55 (B) expression DE filter 1101.The DE filter 1101 of present embodiment mode has by 1 OR circuit and 3 majority voter 1101a and 3 triggers that the AND circuit constitutes.

As the character of DEI signal, it can not export only 1 pulse, but the numerical digit continuous signal.Therefore, if only 1 pulse is arranged, show that then it is a rub-out signal, this rub-out signal of DE filter 1101 filterings.DE filter 1101 is made of the flip-flop circuit and the majority voter 1101a that are used to DEI is postponed.Majority voter 1101a 1 exports 1,0 for a long time and exports 0 for a long time in 3 inputs.In the waveform shown in Figure 55 (B), the mistake shown in the thick line is by majority voter 2540 filterings.By adopting the circuit shown in Figure 55 (A) to constitute, make a mistake even be input to the DE0 of DE filter 1101, also can be with should the mistake filtering, the probability that output EO makes a mistake is very low.

Referring again to Figure 54.Synchronizing signal Hsync, Vsync that is decoded by decoding circuit 424 and CTRL and the chromatic number exported from parallelization circuit 422 are according to DSR[20:0] be output to flip-flop circuit 1102.Flip-flop circuit 1102 is made of 42 triggers 11021, and data are outputed to switching circuit 425 and 426.

Switching circuit 425 and 426 is selected the data imported according to the DE signal of DE filter 1101, outputs to flip-flop circuit 428.Flip-flop circuit 428 output output chromatic numbers are according to (RO5～RO0, GO5～GO0, BO5～BO0) and output synchrodata 432 (HsyncO, VsyncO, CTRLO).

Like this, the input chromatic number of parallel input according to 411, input synchrodata 412 and input clock 414 undertaken sending after the serialization by transmitting element 401, carry out parallelization at receiving element 421, be recovered to the output chromatic number according to 431, output synchrodata 432 and output clock 434 export.

In the present embodiment, because DE filter 1101 is set, thereby the probability that output DEO makes a mistake is very low.Therefore, can more accurate extraction DEO.

Embodiment 8

Embodiment 8 is in transmitting element, when forming serial data, " dc balance " is handled the example that (processing about equally of the number of 1 data and 0 data) is taken into chromatic number certificate and synchrodata.

Figure 56 represents the data structure of the serial data 1401 in the present embodiment.At first; at DEI (data are enabled)=" height " is between active period, 1 code element of serial data 1401 by according to start bit (Start), RGB chromatic number of all kinds 6 according to be encoded into 8 chromatic number according to (R[5:0], G[5:0], B[5:0]), the order that stops guard bit (Stop grd) and position of rest (Stop) carried out serialized data and constituted.

In the present embodiment, when using the dc balance coding circuit 1505 shown in Figure 57 and Figure 58 (A) that RGB chromatic number certificate of all kinds 6 is encoded into 8, implement " dc balance " and handle, accumulative total of RGB 8 bit data of all kinds " height " (=1) separately in the continuous code element and the accumulative total of " low " (=0) are converged to identical number.For example, shown in Figure 58 (B), 6 situations that the chromatic number digital data is " 000001 " being imported have been considered.In the accumulation of numerical data under " 1 " many situation,, be encoded into 8 by " 01 " additional the next to these 6 chromatic number digital data.And, in the accumulation of numerical data, under " 0 " situation how, make this 6 chromatic number digital data counter-rotatings, further additional to the next " 10 ", thus be encoded into 8.The chromatic number that is encoded into 8 is like this selected according to being output to switching circuit, is output to serializer circuit.8 bit data of being changed necessarily comprise 1 and 0 separately, when they are arranged, become the serial data that necessarily comprises more than or equal to 2 rising edge.

On the other hand; DEI (data are enabled)=" low " is black-out intervals, and 1 code element of serial data 1401 constitutes by having carried out serialized data according to start bit (Start), coded HsyncI, VsyncI and CTRLI, the order that stops guard bit (Stop grd) and position of rest (Stop).Promptly at black-out intervals, HsyncI, VsyncI and CTRLI obtain the data structure that only has 1 rising edge in 1 code element in serial data 1401 having carried out carrying out serialization behind the Thermo-code type coding.And during DEI=" low ", coded HsyncI, VsyncI and CTRLI carry out pulse-width modulation, so that keep dc balance.In the present embodiment, shown in Figure 56 (B), HsyncI, the VsyncI and the CTRLI that have carried out Thermo-code type coding are distributed to pulsewidth α, odd number is modulated into pulsewidth (0.5+ α) sends to switching circuit, even number is modulated into pulsewidth (0.5-α) sends to switching circuit.Like this, the average pulse in 1 code element is 0.5, thereby keeps dc balance.

With reference to Figure 57.Figure 57 represents the numerical data transtation mission circuit and the receiving circuit of present embodiment and digital data transmission method and the digital data transmission system that uses them.

The 1501st, transmitting element (transtation mission circuit), will (RI5～RI0, GI5～GI0, BI5～BI0) and input synchrodata 1512 (HsyncI (input level synchrodata), VsyncI (input vertical synchronization data), CTRLI (input control) and DEI (input select signal (the input data are enabled))) be carried out serialization, form serial data 1515 and send to receiving element 1521 according to 1511 with the input chromatic number of input clock input synchronously.

Receiving element (receiving circuit) 1521 receives the serial data 1515 that is sent from transmitting element 1501, carry out parallelization, (RO5～RO0, GO5～GO0, BO5～BO0), output synchrodata 1532 (HsyncO (output horizontal synchronization data), VsyncO (output vertical synchronization data), CTRLO (output control), DEO (signal (dateout is enabled) is selected in output)) and output clock 1534 are exported according to 1531 to be recovered to the output chromatic number.

Transmitting element 1501 has: serializer circuit 1502 (Serializer), phase locking circuit 1503 (PLL circuit: Phase Locked Loop (phase-locked loop) circuit), coding circuit 1504 (Encoder), dc balance coding circuit 1505 (DC Balance Encoder), switching circuit 1506 and output buffer 1507 (Output Buffer).

And, receiving element 1521 has: parallelization circuit 1522 (De-serializer), clock extracting circuit (CDRPLL circuit: Clock Data Recovery Phase Locked Loop (clock data recovery phase-locked loop) circuit) 1523, decoding circuit 1524 and 1525 (Decoder), switching circuit 1526 and 1527, along number decision circuit 1528 and input buffer 1529 (InputBuffer).In addition, output buffer 1507 and input buffer 1529 can be provided with as required.And, in the present embodiment, about the input chromatic number according to 1511, each example of 6 naturally of expression RGB data of all kinds, however the present invention is not limited to this certainly.

The input chromatic number is implemented dc balance and is handled according to the 1511 dc balance coding circuits 1505 that are imported into transmitting element 1501, outputs to switching circuit 1506.DEI (the input data are enabled) is imported into switching circuit 1506.In addition, other constitutes with shown in Figure 45 routine identical.

In transmitting element 1501, the input chromatic number is encoded into 24 according to being imported into dc balance coding circuit 1505.Carry out this coding so as R, G, B separately 6 convert 8 that have carried out dc balance to.Because each 8 both sides that comprise " 1 " and " 0 ", thereby when 24bit carried out serialization according to the order of R, G, B, comprise rising edge more than or equal to 2.

HSYNCI, VSYNCI and CTRLI in the input synchrodata 1512 except DEI are imported into coding circuit 1504, carry out Thermo-Code type coding.Then, if when having carried out serialization in 1 code element on the time first signal sets be MSB, then be output into the level ratio LSB height of MSB by coding circuit 1504, carry out serialization by serializer circuit 1502 from MSB to the LSB order and export.Therefore, these data are because under the low situation of DEI, in 1 code element the output of serializer circuit in time early be high level, thereby generation rising edge when code element is switched only.

Switching circuit 1506 is used as input select signal to DEI, under the high situation of DEI, selection will be imported chromatic number according to the result who has carried out coding at dc balance coding circuit 1505, under low situation, select the output of coding circuit 1504, output to serializer circuit 1502.Input clock 1514 is converted into multi-phase clock at phase locking circuit 1503, and serializer circuit 1502 uses this multi-phase clock that serialization is carried out in the output of switching circuit 1506, exports by output buffer 1507.

By adopting this formation, when DEI was high, the rising edge in 1 code element can exist when the code element switching timing in addition more than or equal to 2, and when DEI was low, the rising edge in 1 code element only existed when the code element switching timing.

In receiving element 1521, at first, clock extracting circuit 1523 restores output clock (CLKO) 1534 and multi-phase clock from serial data 1515.Then, use multi-phase clock that serial data 1515 is converted to parallel signal at parallelization circuit 2522.Parallel signal is imported into along number decision circuit 1528., exporting as DEO high under the situation of rising edge beyond the code element switching timing along number decision circuit 1528, be not in this case, exports as DEO hanging down.Parallel signal is imported into decoding circuit 1524, is decoded into the coding of the dc balance coding circuit 1505 that returns transmitting element 1501.Parallel signal equally also is imported into decoding circuit 1525, is decoded into the coding of the coding circuit 1504 that returns transmitting element 1501.Switching circuit 1526 for activating, is exported the output of decoding circuit 1524 when DEO is high as the output chromatic number number of it is believed that 1531, when low low level is exported as output chromatic number certificate.Switching circuit 1527 for activating, is exported the output of decoding circuit 1525 when DEO is low as output synchrodata 1532, keep output when high.

In addition, shown in the dotted line of Figure 58 (A), the input chromatic number is provided with the dc balance counter according to carrying out in the dc balance coding circuit 1505 that dc balance handles, can obtaining the dc balance of the chromatic number certificate of being exported from dc balance coding circuit 1505.

Embodiment 9

Embodiment 9 does not use coding circuit in the transmitter side unit, and does not use the embodiment of decoding circuit in the receiver side unit.

Figure 59 (A) and (B) expression will walk abreast each 6 chromatic number of input according to (RI5～RI0, GI5～GI0, BI5～BI0) and synchrodata (HsyncI, VsyncI, CTRLI0～2, DEI) have been carried out the signal waveform example of serialized serial data 1715 in the receiver side unit of present embodiment.

At first, at DEI (data are enabled)=" height " is between active period, 1 code element of serial data 1715 obtain according to start bit (Start), data enable reverse signal (DEIn), chromatic number according to (RI5, RI4 ..., BI2, BI1, BI0) and the order of position of rest (Stop) carried out serialized data structure.

On the other hand; DEI (data are enabled)=" low " is black-out intervals, and 1 code element of serial data 1715 obtains enables according to start bit (Start), data that reverse signal (DEIn), data are enabled guard bit (DE grd), HsyncI, VsyncI and CTRLI0～2, the order that stops guard bit (Stop grd) and position of rest (Stop) has been carried out serialized data structure.

In the present embodiment, data are set and enable guard bit (DE grd) after data are enabled reverse signal (DEIn).By being set, these data enable guard bit (DE grd); more high accuracy is extracted the data that become return contact when serial data 1715 is recovered to parallel data out and is enabled reverse signal (DEIn); thereby can reduce the possibility of the errors of sampling that synchrodata takes place, but high accuracy is carried out clock and is restored.

And in the present embodiment, setting stops guard bit (Stop grd) after synchrodata.Like this, can the more accurate extraction of carrying out next synchrodata, the reliability of synchronous data transmission improves, and can realize that stable data transmits.

Here, with reference to Figure 60 the formation of the data communication system of present embodiment is described.The 1701st, transmitting element, (RI5～RI0, GI5～GI0, BI5～BI0), input synchrodata 1712 (HsyncI (input level synchrodata), VsyncI (input vertical synchronization data), CTRLI0～2 (input control), DEI (input select signal (the input data are enabled))) and input clock 1714 carry out serialization, form serial data 1715 and send to receiving element 1721 according to 1711 with the input chromatic number imported.

Receiving element 1721 receives the serial data 1715 that is sent from transmitting element 1701, carry out parallelization, (RO5～RO0, GO5～GO0, BO5～BO0), output synchrodata 1732 (HsyncO (output horizontal synchronization data), VsyncO (output vertical synchronization data), CTRLO0～2 (output control 0～2)), output select signal 1733 (DEO (dateout is enabled)) and output clock 1734 to export according to 1731 to be recovered to the output chromatic number.

Transmitting element 1701 has: serializer circuit 1702 (Serializer), phase locking circuit 1703 (PLL circuit), switching circuit 1704 and output buffer 1705 (Output Buffer).

And receiving element 1721 has: parallelization circuit 1722 (De-serializer), clock extracting circuit (CDRPLL circuit) 1723, switching circuit 1724 and input buffer 1725 (Input Buffer).

In addition, output buffer 1705 and input buffer 1725 can be provided with as required.And, in the present embodiment, about the input chromatic number according to 1711, each example of 6 naturally of expression RGB data of all kinds, however the present invention is not limited to this certainly.

The input chromatic number according to 1711 and input synchrodata 1712 be imported into the switching circuit 1704 of transmitting element 1701.Input clock 1714 is imported into phase locking circuit 1703, is converted into a plurality of clocks with phase difference at phase locking circuit 1703, and these a plurality of clocks with phase difference are imported into serializer circuit 1702.Switching circuit 1704 selects to output to the data of serializer circuit 1702 under the situation of the situation of DEI=" height " and DEI=" low ".Serializer circuit 1702 according to the input chromatic number of being imported from switching circuit 1704 according to 1711, input synchrodata 1712 and a plurality of clocks of being imported from phase locking circuit 1703 with phase difference, form serial data 1715.

Serial data 1715 is output to receiving element 1721 through output buffer 1705.The parallelization circuit 1722 of receiving element 1721 will carry out parallelization through the serial data 1715 that input buffer 1725 is imported, and this output is outputed to switching circuit 1724.Clock extracting circuit 1723 is according to the data recovery output clock 1734 a plurality of clocks of being imported different with phase place, and a plurality of clocks different these phase places output to parallelization circuit 1722.Switching circuit 1724 is when DE is high, and the output chromatic number of output institute parallelization is exported low level when low according to 1731 as output chromatic number certificate.And switching circuit 1724 is exported the synchrodata of institute's parallelization when DE is low as output synchrodata 1523, keeps output when high.

With reference to Figure 61.Figure 61 represents the formation of the transmitting element 1701 in the present embodiment.The input chromatic number is according to 1711 (RI5～RI0, GI5～GI0, BI5～BI0) be imported into switching circuit 1704 with input synchrodata (HsyncI, VsyncI, CTRLI0～2, DEI).In the present embodiment, (RI5～RI0, GI5～GI0, BI5～BI0) order is imported into an input of the multiplexer that is connected in parallel 17041 that constitutes switching circuit 1704 to the input chromatic number according to 1711, " height " is imported into input another input according to the multiplexer 17041 of RI5 in 1711 and RI4 of input chromatic number, and " low " is imported into another input that input has the multiplexer 17041 of BI0.And, HsyncI is imported into another input that input has the multiplexer 17041 of RI3, RI2 and RI1, VsyncI is imported into another input that input has the multiplexer 17041 of RI0, GI5 and GI4, and CTRLI0～2 are imported into another input that input has the multiplexer 17041 of GI3, GI2 and GI1, GI0, BI5 and BI4, BI3, BI2 and BI1 separately.According to 1711 and input synchrodata 1712, (SR1～SR19) outputs to serializer circuit 1702 to switching circuit 1704 data according to the DEI that is imported, input chromatic number.

Phase locking circuit 1703 forms the different a plurality of clocks of phase place according to input clock 1714, outputs to serializer circuit 1702.

Serializer circuit 1702 is according to the different a plurality of clocks of being imported from phase locking circuit 1703 of phase place, and (SR1～SR19) carry out serialization forms serial data 1715, outputs to receiving element 1721 by output buffer 1705 with the data imported.

Figure 62 represents the formation of the receiving element 1721 of present embodiment.The serial data of being exported from transmitting element 1,701 1715 is imported into parallelization circuit 1722 and clock extracting circuit 1723 by input buffer 1725.Clock extracting circuit 1723 is extracted clock out from serial data 1715, restore the output clock 1733 a plurality of clocks different with phase place.Parallelization circuit 1722 carries out parallelization according to the different a plurality of clocks of phase place that restored by clock extracting circuit 1723 with serial data 1715, and (DSR0～DSR20) outputs to switching circuit 1724 dateout.Data (the DSR0～DSR20), output to the flip-flop circuit 1726 that comprises a plurality of triggers 17261 that switching circuit 1724 selections are imported from parallelization circuit 1722.Flip-flop circuit 1726 output output chromatic numbers are (RO5～RO0, GO5～GO0, BO5～BO0) and output synchrodata 1732 (HsyncO, VsyncO, CTRLO0～2, DEI) according to 1731.

Like this, the input chromatic number of parallel input according to 1711, input synchrodata 1712 and input clock 1714 undertaken sending after the serialization by transmitting element 1701, carry out parallelization at receiving element, be recovered to the output chromatic number according to 1731, output synchrodata 1732 and output clock 1734 export.

In the present embodiment; data are set after the reverse signal (DEIn) and enable guard bit (DE grd) by enabling continue data; more high accuracy is extracted the data that become return contact when serial data 1715 is recovered to parallel data out and is enabled reverse signal (DEIn); thereby can reduce the possibility of the errors of sampling that synchrodata takes place, but high accuracy is carried out clock and is restored.And in the present embodiment, setting stops guard bit (Stop grd) after synchrodata.Like this, can the more accurate extraction of carrying out next synchrodata, the reliability of synchronous data transmission improves, and can realize that stable data transmits.

Embodiment 10

Embodiment 10 does not use coding circuit in the transmitter side unit, and does not use other embodiment of the data communication system of decoding circuit in the receiver side unit.

Figure 63 (A) and (B) expression will walk abreast each 6 chromatic number of input according to (RI5～RI0, GI5～GI0, BI5～BI0) and synchrodata (HsyncI (input level synchrodata), VsyncI (input vertical synchronization data), CTRLI (input control), DEI (the input data are enabled)) have been carried out the signal waveform example of serialized serial data 2000 in the receiver side unit of present embodiment.In addition, in the present embodiment, 1 code element is 21.

At first, at DEI (data are enabled)=" height " is between active period, 1 code element of serial data 2000 obtain according to start bit (Start), data enable reverse signal (DEIn), chromatic number according to (RI5, RI4 ..., BI2, BI1, BI0) and the order of position of rest (Stop) carried out serialized data structure.

On the other hand; DEI (data are enabled)=" low " is black-out intervals, and 1 code element of serial data 2000 obtains enables according to start bit (Start), data that reverse signal (DEIn), data are enabled SpecialCase (particular size is write) data of guard bit (DE grd), HsyncI, VsyncI and CTRLI0～2, system reset etc., the order that stops guard bit (Stop grd) and position of rest (Stop) has been carried out serialized data structure.

In the present embodiment, data are set and enable guard bit (DE grd) after data are enabled reverse signal (DEIn).By being set, these data enable guard bit (DE grd); more high accuracy is extracted the data that become return contact when serial data 1715 is recovered to parallel data out and is enabled reverse signal (DEIn); thereby can reduce the possibility of the errors of sampling that synchrodata takes place, but high accuracy is carried out clock and is restored.

And in the present embodiment, setting stops guard bit (Stop grd) after synchrodata.Like this, can the more accurate extraction of carrying out next synchrodata, the reliability of synchronous data transmission improves, and can realize that stable data transmits.

Embodiment 11

Embodiment 11 is a kind of modes of above-mentioned execution mode and embodiment 1 to 5 spendable clock extracting circuit.

Figure 64 represents the circuit block diagram of clock extracting circuit.The 2201st, phase-comparison circuit (PD), the 2202nd, phase place mlultiplying circuit (LPF), the 2203rd, oscillating circuit.Adopt following formation: the serial data 2204 of exporting and be input to receiving element from transmitting element is carried out signal processing by phase-comparison circuit 2201, phase place mlultiplying circuit 2202 and oscillating circuit 2203, and this output is fed back to phase-comparison circuit 2201.

Numerical data transtation mission circuit of the present invention, receiving circuit, encoder, clock extracting circuit and digital data transmission method and digital data transmission system can be applicable between device, to walk abreast all devices of transmitting-receiving of supplied digital data.Particularly, can be applicable to: the numerical data transmitting-receiving between personal computer and active matrix-type liquid crystal display device, and the transmitting-receiving of the numerical data between auto navigation main body and active matrix-type liquid crystal display device.And in the above-described embodiment and examples, the data transmit-receive about between transmitter side unit and receiver side unit is described unidirectional situation, yet can carry out the bi-directional data transmitting-receiving.And in the above-described embodiment and examples, the expression serial data is used the example that distribution is received and dispatched, and uses many distributions to receive and dispatch yet serial data can be cut apart.

Claims (30)

1. transfer approach, this transfer approach be with the 1st information and the 2nd information each during the comfortable the 1st and the digital data transmission method that alternate cycle transmits during the 2nd, it is characterized in that,

The amount of information of the time per unit of described the 1st information during the described the 1st is more than the amount of information of the time per unit of described the 2nd information during the described the 2nd;

Described the 1st information during the described the 1st doubly is that the serial data of 1 code element transmits as the n with minimum pulse width, and the serial data of described the 2nd information during the described the 2nd after as pulse-width modulation transmits.

2. transfer approach according to claim 1 is characterized in that, the serial data after the described pulse-width modulation, last place value always more than or equal to following place value, only have 1 rising edge in 1 code element.

3. transfer approach according to claim 1 is characterized in that described serial data is encoded, so that carry out dc balance.

4. transfer system, this transfer system be with the 1st information and the 2nd information each during the comfortable the 1st and the transfer system that alternate cycle is carried out serial transfer during the 2nd, it is characterized in that, comprise:

The 2nd encoder is encoded described the 2nd information, so that carry out serialization and when becoming the serial data of 1 code element in order, becomes the pulse-width signal in n cycle doubly of the minimum pulse width of the serial data when described the 1st information carried out serialization;

The 1st encoder is encoded described the 1st information, so that make the serial data of 1 code element when having carried out serialization in proper order different with described pulse-width signal;

Serializer circuit, described coded described the 1st information translation is become the serial data of described 1 code element, described coded described the 2nd information translation is become serial data as the described pulse-width signal of described 1 code element, 1 code-element string line data of described the 1st information and 1 code-element string line data alternate cycle of described the 2nd information are carried out serialization;

Transfer path transmits described serialized data;

The clock extracting circuit is extracted the reference clock in these serial datas out the serial data of the 1st information that is transmitted or the serial data of described the 2nd information from described transfer path;

The information judging circuit, described different according to the data of the serial data of described the 1st information and the serial data of described the 2nd information are differentiated the serial data of described the 1st information and the serial data of described the 2nd information;

The 1st decoder is decoded into described the 1st information with the serial data of described described the 1st information of separating is corresponding with described the 1st encoder; And

The 2nd decoder is decoded into described the 2nd information with the serial data of described described the 2nd information of separating is corresponding with described the 2nd encoder;

The amount of information of the time per unit of described the 1st information that is transmitted during the described the 1st is more than the amount of information of the time per unit of described the 2nd information that is transmitted during the described the 2nd.

5. transfer system, this transfer system be with the 1st information and the 2nd information each during the comfortable the 1st and the transfer system that alternate cycle is carried out serial transfer during the 2nd, it is characterized in that having:

The 2nd encoder is encoded described the 2nd information, so that carry out serialization and when becoming the serial data of 1 code element in order, becomes the pulse-width signal in n cycle doubly of the minimum pulse width of the serial data when described the 1st information carried out serialization;

The 1st encoder is encoded described the 1st information, so that make the serial data of 1 code element when having carried out serialization in proper order different with described pulse-width signal;

Serializer circuit, described coded described the 1st information translation is become the serial digital data of described 1 code element, described coded described the 2nd information translation is become serial data as the described pulse-width signal of described 1 code element, 1 code-element string line data of described the 1st information and 1 code-element string line data alternate cycle of described the 2nd information are carried out serialization;

Transfer path transmits described serialized data;

The clock extracting circuit is extracted the reference clock in these serial datas out the serial data of the 1st information that is transmitted or the serial data of described the 2nd information from described transfer path;

The information judging circuit, described different according to the data of the serial data of described the 1st information and the serial data of described the 2nd information are discerned the serial data of described the 1st information and the serial data of described the 2nd information;

The 1st decoder is decoded into described the 1st information with the serial data of described described the 1st information of separating is corresponding with described the 1st encoder; And

The 2nd decoder is decoded into described the 2nd information with the serial data of described described the 2nd information of separating is corresponding with described the 2nd encoder;

Described clock extracting circuit has:

Phase bit comparison loop comprises: voltage control circuit, the phase-comparison circuit that the output phase of described serial data and voltage control oscillating circuit is compared, and the loop filter that generates the control voltage of described voltage control circuit;

Sampling circuit uses and at the multi-phase clock that described voltage control oscillating circuit generated described serial data is sampled;

Frequency control circuit, the frequency of oscillation of the frequency of the serial data of described 1 code element and described voltage control oscillating circuit is compared, make the frequency of oscillation of voltage control oscillating circuit consistent with the frequency of the serial data of described 1 code element, this frequency control circuit has: along the number decision circuit, judge that rising edge number in the serial signal during described 1 code element that described voltage control oscillating circuit generated is 0 or 1 or in addition; And timer, be 0 at the rising edge number, perhaps be reset time interval output timer signal according to the rules under the disabled situation of frequency control circuit; This frequency control circuit is controlled, so that be under 0 the situation, the frequency of oscillation of voltage control oscillating circuit to be descended at the rising edge number, is exporting under the situation of timer signal from timer, and the frequency of voltage control oscillating circuit is risen;

Charge pump receives the output of described frequency control circuit, and current impulse is outputed to described loop filter; And

The mode switch circuit, import from described phase-comparison circuit under the situation of frequency ratio than the mode request signal, enable frequency control circuit, the forbidding phase-comparison circuit, be to detect continuously more than or equal to stated number under 1 the situation at rising edge number or trailing edge number, the output frequency that is judged to be described voltage control oscillating circuit is in the capture range of described phase bit comparison loop, and the forbidding frequency control circuit is enabled phase-comparison circuit.

6. transtation mission circuit, this transtation mission circuit be with the 1st information and the 2nd information each during the comfortable the 1st and the transtation mission circuit that alternate cycle is carried out serial transfer during the 2nd, have:

The 2nd encoder is encoded described the 2nd information, so that carry out serialization and when becoming the serial data of 1 code element in order, becomes the pulse-width signal of n doubling time of the minimum pulse width of the serial data when described the 1st information carried out serialization;

The 1st encoder is encoded described the 1st information, so that make the serial data of 1 code element when having carried out serialization in proper order different with described pulse-width signal;

Serializer circuit becomes the serial data of described 1 code element to described coded described the 1st information translation, and described coded described the 2nd information translation is become serial data as the described pulse-width signal of described 1 code element.

7. transtation mission circuit according to claim 6 is characterized in that, described the 1st encoder is encoded, so that have the rising edge more than or equal to 2 in the serial data of described 1 code element;

Described the 2nd encoder is encoded, so that only 1 rising edge is configured in the starting point certain position of described 1 code element of distance in the serial data of described 1 code element.

8. transtation mission circuit according to claim 7 is set at trailing edge to described rising edge.

9. transtation mission circuit according to claim 6 is characterized in that, described the 1st encoder has:

Combinational logic circuit has a plurality of corresponding relations of input and output; And

Decision circuit is estimated described the 1st information of importing at least, and output is based on the decision signal of this evaluation;

Described combinational logic circuit carries out the coding of selected described corresponding relation according to described decision signal, and the bits of coded that is used to discern this selected described corresponding relation is given to described output.

10. transtation mission circuit according to claim 9 is characterized in that, described corresponding relation comprises the 1st corresponding relation and the 2nd corresponding relation;

Described the 1st corresponding relation is the relation that described input and output equate;

Described the 2nd corresponding relation is to make output carry out the relations that code reverses with respect to described input every 2.

11. transtation mission circuit according to claim 10, it is characterized in that, described decision circuit is that output makes described combinational logic circuit select the decision signal of described the 2nd corresponding relation under 0 the situation at the rising edge number when described the 1st information has been carried out simple serial conversion.

12. transtation mission circuit according to claim 11 is set at trailing edge to described rising edge.

13. transtation mission circuit according to claim 10, it is characterized in that, described decision circuit carries out simple serial conversion with described the 1st information, when having added different mutually start bit of code and position of rest before and after it, be that output makes described combinational logic circuit select the decision signal of described the 2nd corresponding relation under 1 the situation at the rising edge number.

14. transtation mission circuit according to claim 13 is set at trailing edge to described rising edge.

15. transtation mission circuit according to claim 9, it is characterized in that described decision circuit output makes described combinational logic circuit select the decision signal of the described corresponding relation of the same code consecutive numbers minimum in the serial data of described 1 code element behind the coding in described a plurality of corresponding relation.

16. transtation mission circuit according to claim 9, it is characterized in that the output of described decision circuit makes described combinational logic circuit select same code consecutive numbers in the serial data of described 1 code element behind the coding in described a plurality of corresponding relation to add the decision signal of the little described corresponding relation of value after 1 than 1/2nd of the figure place of the serial data of described 1 code element.

17. transtation mission circuit according to claim 9, it is characterized in that the output of described decision circuit makes the decision signal of the minimum described corresponding relation of the difference of cumulative number separately of the data in the data symmetric relation after described combinational logic circuit selects to make in described a plurality of corresponding relation coding.

18. transtation mission circuit according to claim 9, it is characterized in that, described decision circuit to the SN of the serial digital data that comprises main information transmitted frequency, EMI amount, described 1 code element and described pulse-width signal than or error rate at least one information estimate the decision signal that output is corresponding with this evaluation.

19. a receiving circuit is used to receive the signal of institute's serial transfer, has:

The clock extracting circuit is extracted the reference clock in these serial datas out from the serial data of the serial data of described the 1st information or described the 2nd information;

The information judging circuit, described different according to the data of the serial data of described the 1st information and the serial data of described the 2nd information are differentiated the serial data of described the 1st information and the serial data of described the 2nd information;

The 1st decoder is decoded into described the 1st information with the described serial data of declaring other described the 1st information is corresponding with described the 1st encoder; And

The 2nd decoder is decoded into described the 2nd information with the serial data of described described the 2nd information of separating is corresponding with described the 2nd encoder;

Reception is with the serial data of the 2nd information, promptly as the serial data of the 2nd information after the serial dataization of 1 code element of the pulse-width signal of the n doubling time of the minimum pulse width of the serial data of 1 code element of the 1st information and the serial data of the 1st information, promptly be serialized into the signal that the serial data alternate cycle of the serial data that makes 1 code element 1st information different with described pulse-width signal has been carried out serial transfer.

20. receiving circuit according to claim 19 is characterized in that, the serial data of described the 1st information comprises the bits of coded of recognition coding pattern, and described the 1st decoder carries out the decoding corresponding with described bits of coded.

21. receiving circuit according to claim 19 is characterized in that, described information judging circuit is discerned the serial data of described the 1st information and the serial data of described the 2nd information according to the rising edge number in 1 code element of described serial data.

22. receiving circuit according to claim 21 is set at trailing edge to described rising edge.

23. a receiving circuit is characterized in that having:

Phase bit comparison loop comprises: voltage control circuit, the phase-comparison circuit that the output phase of serial data and voltage control oscillating circuit is compared, and the loop filter that generates the control voltage of described voltage control circuit;

Sampling circuit uses and at the multi-phase clock that described voltage control oscillating circuit generated described serial data is sampled;

Frequency control circuit, the frequency of oscillation of the frequency of described serial data and described voltage control oscillating circuit is compared, make the frequency of oscillation of voltage control oscillating circuit consistent with the frequency of serial data, this frequency control circuit has: along the number decision circuit, judge that rising edge number in the serial signal during 1 code element that described voltage control oscillating circuit generated is 0 or 1 or in addition; And timer, be 0 at the rising edge number, perhaps be reset time interval output timer signal according to the rules under the disabled situation of frequency control circuit; This frequency control circuit is controlled, so that be under 0 the situation, the frequency of oscillation of voltage control oscillating circuit to be descended at the rising edge number, is exporting under the situation of timer signal from timer, and the frequency of voltage control oscillating circuit is risen;

Charge pump receives the output of described frequency control circuit, and current impulse is outputed to described loop filter; And

The mode switch circuit, import from described phase-comparison circuit under the situation of frequency ratio than the mode request signal, enable frequency control circuit, the forbidding phase-comparison circuit, be to detect continuously more than or equal to stated number under 1 the situation at the rising edge number, the output frequency that is judged to be described voltage control oscillating circuit is in the capture range of described phase bit comparison loop, and the forbidding frequency control circuit is enabled phase-comparison circuit.

24. receiving circuit according to claim 23, it is characterized in that, described along the number decision circuit represent zero output according to the count results of the rising edge number in the described signal of sampling and represent not exist from the result that described serial data is directly judged rising edge output " with ", carry out along the judgement of number zero.

25. receiving circuit according to claim 23 is characterized in that, described frequency control circuit preferentially carries out the frequency of oscillation suppression ratio rising of described voltage control oscillating circuit.

26. receiving circuit according to claim 23, it is characterized in that described charge pump makes and receiving the total charge dosage of charging under the situation of rising signals from described frequency control circuit than in that receive the total charge dosage of discharging under the situation of dropping signal from described frequency control circuit big.

27. a clock extracting circuit is extracted clock out from the signal of institute's serial transfer;

The signal of described institute serial transfer is that the 1st information has been carried out the serial digital data of 1 code element of coding and signal that the pulse-width signal alternate cycle has been carried out serial transfer, this pulse-width signal is that the 2nd signal encoding is become different with the serial digital data of described 1 code element, the pulse-width signal that has carried out pulse-width modulation according to the pulsewidth n cycle doubly of the numerical data of the serial digital data that constitutes described 1 code element, only have 1 rising edge or trailing edge in described 1 code element, described rising edge or trailing edge are configured in the frame end certain position apart from described 1 code element;

This clock extracting circuit has:

Voltage-controlled oscillator;

Phase comparator, output with import serial data and from the corresponding phase signal of phase difference of the output signal of described voltage-controlled oscillator;

Frequency comparator, output is with described input serial data with from the corresponding difference on the frequency signal of the output signal frequency difference of described voltage-controlled oscillator; And

The mode switch circuit is selected described phase signal or difference on the frequency signal;

Described frequency comparator has:

Along the number decision circuit, judge that be 0 or 1 from the input data in 1 code-element period of the output signal of described voltage-controlled oscillator along number, export corresponding with result of determination along the number decision signal;

Timer is 0 along number and has selected to be reset under the situation of described phase signal time interval output timer signal according to the rules described; And

Frequency control circuit along number decision signal and described timer signal, is controlled the frequency of oscillation of described voltage-controlled oscillator according to described;

The described official hour of described timer is longer than transmitting the described time interval from information at interval;

Described frequency control circuit described be under 0 the situation along number, the frequency of oscillation of described voltage-controlled oscillator is descended, under the situation of having exported described timer signal, the frequency of oscillation of described voltage-controlled oscillator is risen;

Described mode switch circuit has obtained at number of times in accordance with regulations to be under the situation of 1 result of determination along number, to select described phase signal continuously described;

The frequency of oscillation of described voltage-controlled oscillator is according to being controlled by selected described phase signal of described mode switch circuit or described difference on the frequency signal.

28. clock extracting circuit according to claim 27 is characterized in that, has the fine setting frequency comparison circuit;

Described fine setting frequency comparison circuit is according to the variable quantity of every code element of the rising edge position in 1 code element, calculate described oscillator oscillator signal frequency and based on the frequency departure amount of the frequency in the described rising edge cycle in described 1 frame, the control signal corresponding with described frequency departure amount outputed to described voltage-controlled oscillator.

29. clock extracting circuit according to claim 28 is characterized in that,

Described fine setting frequency comparison circuit has: infer circuit, infer start bit and position of rest in described 1 code element;

According to the variable quantity of per 1 code element of described start bit and described position of rest, derive described voltage-controlled oscillator described oscillator signal frequency and based on the frequency departure amount of the frequency in the described rising edge cycle in described 1 code element;

The control signal corresponding with described frequency departure amount outputed to described voltage-controlled oscillator.

30. clock extracting circuit according to claim 27 is characterized in that having: the sampler circuit, will import data and sample, the output sampling data;

Described have along the number decision circuit: along testing circuit, have or not the edge according to the described input serial data of described input Data Detection, output is along having or not information;

Describedly have or not information to judge according to described data from the sample survey and described edge along number along the number decision circuit.

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