CN1790715A - 产生用于mosfet沟道迁移率调整的局部机械栅极应力的结构和方法 - Google Patents
产生用于mosfet沟道迁移率调整的局部机械栅极应力的结构和方法 Download PDFInfo
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Abstract
本发明提供了一种能够产生用于沟道迁移率调整的局部机械栅极应力的半导体结构和方法。所述半导体结构包括半导体衬底表面上的至少一个NFET和至少一个PFET。所述至少一个NFET具有包括栅极介质、第一栅极电极层、阻挡层和压缩金属的栅极叠层结构,而所述至少一个PFET具有包括栅极介质、第一栅极电极层、阻挡层和拉伸金属或硅化物的栅极叠层。
Description
技术领域
本发明涉及用于模拟或数字应用中的高性能金属氧化物半导体场效应晶体管(MOSFET),具体涉及其中存在用于调整沟道迁移率的局部机械栅极应力的MOSFET。本发明也涉及产生用于MOSFET沟道迁移率调整的局部机械栅极应力的方法。
背景技术
在场效应晶体管(FET)的工作特性中,已经证明了通过应变提高晶体管特性,即,载流子迁移率。对于互补金属氧化物半导体(CMOS)器件,通过提高的载流子迁移率来提高器件特性对于超高速器件的制造具有巨大的潜力。弛豫SiGe衬底上的应变硅是可以产生这种提高的一种系统,例如,参考D.K.Nayak等人的,“High Mobility p-ChannelMetal-Oxide-Semiconductor Field-Effect-Transistor on Strained Si,”Appl.Phys.Lett.,62(22),p.2853-2855(1993)。
关于通过应变产生提高了载流子迁移率的MOSFET的试验研究集中在弛豫SiGe衬底上生长的应变Si上。使用Si/SiGe系统制造的MOSFET显示出如下缺点:(1)在应变Si区域中形成高的源极和漏极结泄露,即FET源极和漏极结,以及沟道区,产生高的结泄漏。(2)Si/SiGe系统MOSFET工艺与具体需要使用分子束外延制备衬底的主流CMOS制造技术不兼容。(3)Si/SiGe系统MOSFET工艺产率低而成本高。
局部机械应力(LMS)对于SiGe上的应变Si是可行的选择。最常见的LMS方法是使用应力SiN接触蚀刻停止以产生沟道应变从而提高电荷载流子迁移率。也可以通过从栅极电极施加应力来产生沟道应变。
公知,一般在半导体工艺中使用的硅化物可以具有高的拉伸应力。然而,为了在沟道上产生明显的影响,硅化物必须接近沟道的表面。所谓“接近”,就意味着硅化物必须在离沟道表面约10nm以内。另外,如果对于所有的CMOS器件要具有一致的沟道应变,硅化物的厚度必须一致。
通过硅化物产生栅极应力的两个主要挑战是要具有接近沟道的一致硅化物。于是,需求能够在具有高度不一致性和控制的栅极叠层内最小化硅化物到沟道的距离的结构。换句话说,需求提供可以产生用于MOSFET沟道迁移率提高的局部机械应力的半导体结构。
发明内容
本发明提供了一种能够产生调整MOSFET的沟道迁移率的局部机械栅极应力的结构和方法。具体地说,需求提供一种具有产生用于NFET的局部机械应力和产生用于PFET的局部机械应力的结构。
广泛地讲,本发明提供了一种半导体结构,包括半导体衬底表面上的至少一个NFET和至少一个PFET,其中所述至少一个NFET具有包括栅极介质、第一栅极电极层、阻挡层和压缩金属的栅极叠层结构;而所述至少一个PFET具有包括栅极介质、第一栅极电极层、阻挡层和拉伸金属或含Si的第二栅极电极层和硅化物的栅极叠层结构。所述拉伸金属或硅化物在所述PFET器件的沟道中产生提高该器件载流子迁移率的局部机械应力,而所述压缩金属产生用于所述NFET的局部机械应力。
本发明也提供了用于形成上述半导体结构的方法。根据本发明的方法,利用下面的工艺步骤制造本发明的半导体结构:
提供具有位于半导体衬底表面上的栅极介质、第一栅极电极层、阻挡层、含Si的第二栅极电极层和硬掩模的半导体结构,所述半导体衬底包含沟槽隔离区;
构图所述层,以提供用于NFET的至少一个构图的栅极叠层和用于PFET的至少一个构图的栅极叠层,所述NFET和PFET通过所述沟槽隔离区分开;
在每个所述构图的栅极叠层的侧壁上形成至少一个隔离层,并在邻近每个所述构图的栅极叠层的所述半导体衬底中形成硅化的源极/漏极区;
形成平面化的介质膜,所述膜暴露每个所述构图的栅极叠层的上表面;
在用于所述NFET的所述至少一个构图的栅极叠层中选择性地形成压缩金属;以及
在用于所述PFET的所述至少一个构图的栅极叠层中选择性地形成硅化物或拉伸金属。
也提供了形成本发明的结构的第二方法,包括以下步骤:
提供具有位于半导体衬底表面上的栅极介质、第一栅极电极层、阻挡层、第二栅极电极层和硬掩模的半导体结构,所述半导体衬底包含沟槽隔离区而所述第二栅极电极层包括拉伸金属或硅化物;
构图所述层,以提供用于NFET的至少一个构图的栅极叠层和用于PFET的至少一个构图的栅极叠层,所述NFET和PFET通过所述沟槽隔离区分开;
在每个所述构图的栅极叠层的侧壁上形成至少一个隔离层,并在邻近每个所述构图的栅极叠层的所述半导体衬底中形成硅化的源极/漏极区;
形成平面化的介质膜,所述膜暴露每个所述构图的栅极叠层的上表面;以及
在用于所述NFET的所述至少一个构图的栅极叠层中选择性地形成压缩金属。
附图说明
图1A-1J(通过截面图)示出了本发明的一个实施例的基本工艺步骤。
图2A-2E(通过截面图)示出了本发明的另一个实施例的基本工艺步骤。
图3示出了用Lpoly=60nm模拟的结构。
图4是对于图3中所示的结构的应力曲线,示出了沟道区中来自2GPa的拉伸硅化物的0.6GPa的应力。
图5是应力与硅化物类型的关系图,示出了在形成之后不同硅化物中的拉伸应力(0.5-2.0GPa)。也示出了在形成之前硅化物金属的最初淀积后(as-deposited)的应力。
图6是从J.Appl.Phys.72(10),4918(1992)复制的现有图表,示出了作为淀积压力的函数的Ta膜中的应力。
图7是从J.Appl.Phys.72(10),4918(1992)复制的现有图表,示出了作为退火温度的函数的压缩Ta膜中的应力。
具体实施方式
本发明提供了能够产生用于沟道迁移率提高的局部机械应力的半导体结构以及方法,现在将通过参考下面的讨论和附图更详细地描述本发明。提供结合本申请的附图用于示意性目的并因此这些附图没有按比例绘制。
首先参考图1A-1J,它示出了产生用于MOSFET沟道迁移率调整的局部机械栅极应力的本发明的一个实施例的基本工艺步骤。本发明的此实施例的工艺开始于首先提供图1A中所示的结构10。如图所示,结构10包括半导体衬底12、至少一个沟槽隔离区14、栅极介质16和第一栅极电极层18。
结构10的半导体衬底12包括任何半导体材料,包括但不局限于:Si、Ge、SiGe、SiC、SiGeC、Ga、GaAs、InAs、InP和所有其它III/V族化合物半导体。半导体衬底也可以包括有机半导体或层叠半导体,例如Si/SiGe、绝缘体上硅(SOI)或绝缘体上SiGe(SGOI)。在本发明的一些实施例中,优选半导体衬底12由含Si的半导体材料构成,即,包括硅的半导体材料。半导体衬底12可以是掺杂的、未掺杂的,或其中包含掺杂或未掺杂的区。
半导体衬底12也可以包括第一掺杂(n-或p-)区,和第二掺杂(n-或p-)区。为了简洁,在本申请的附图中没有具体标记掺杂区。第一掺杂区和第二掺杂区可以是相同的,或者它们可以具有不同的导电性和/或掺杂浓度。这些掺杂区就是公知的“阱”。
利用本领域内的技术人员公知的常规工艺,在半导体衬底12中形成至少一个沟槽隔离区14。通常利用本领域内公知的沟槽隔离技术形成至少一个沟槽隔离14,所述技术包括例如,在衬底的表面上通过光刻形成构图掩模、通过构图掩模中的开口将沟槽蚀刻进衬底、用如SiO2或TEOS的沟槽介质填充沟槽并平面化该结构。在沟槽介质填充之前可以在沟槽内形成光学沟槽衬里,并可在平面化工艺之后进行光学致密化步骤。
如图1A所示,将半导体衬底12分为两个区域12A和12B的至少一个沟槽隔离区14隔离了例如在半导体衬底12上形成的FET器件的半导体器件。
在包括半导体衬底12的结构10的整个表面上,并如果存在隔离区并且如果隔离区是淀积的介质在隔离区上,形成栅极介质16。图1A中的实施例示出了其中栅极介质只位于半导体衬底12上的情况。可以通过例如氧化、氮化或氧氮化的热生长工艺形成栅极介质16。作为选择,可以通过例如化学气相淀积(CVD)、等离子体辅助CVD、原子层淀积(ALD)、蒸发、反应溅射、化学溶液淀积或其它类似淀积工艺的淀积工艺形成栅极介质16。还可以利用上述工艺的任何组合形成栅极介质16。
构成栅极介质16的绝缘材料包括但不局限于:氧化物、氮化物、氧氮化物和/或包括金属硅酸盐和氮化金属硅酸盐的硅酸盐。在一个实施例中,优选栅极介质16由例如SiO2、 HfO2、ZrO2、Al2O3、TiO2、La2O3、SrTiO3、LaAlO3及其混合物的氧化物构成。
栅极介质16的物理厚度可以改变,但通常栅极介质16具有从约0.5到约10nm的厚度,而以从约0.5到3nm的厚度更为典型。
形成栅极介质16之后,在栅极介质16上利用公知的例如物理气相淀积、CVD或蒸发的淀积工艺,形成第一栅极电极材料覆层18。本发明此时淀积的第一栅极电极层18的厚度,即高度,可以根据采用的淀积工艺而变化。通常,第一栅极电极层18具有从约5到约180nm的垂直厚度,而以从约5到约50nm的厚度更为典型。
第一栅极电极层18可以包括任何通常采用作为CMOS结构的栅极的导电材料。这些可以采用作为第一栅极电极层18的导电材料的示意性实例包括但不局限于:多晶硅、导电金属、导电金属合金、导电硅化物、导电氮化物、多晶SiGe及包括其多层的组合。在优选实施例中,第一栅极电极层18为多晶硅层。
然后利用常规光刻工艺在图1A中所示的结构10上形成第一阻挡掩模20。第一阻挡掩模20覆盖了上述区域12A和12B中的一个,并接着将第一导电类型22的离子注入未受第一阻挡掩模20保护的第一栅极电极18。第一导电类型的离子可以为n型杂质(即,来自元素周期表的VA族的如P、As、Sb或Bi的元素),或p型杂质(即,来自元素周期表的IIIA族的如B、Al、Ga、In或Tl的元素),这取决于要在未受第一阻挡掩模20保护的区域中制造的CMOS器件的类型。
未受第一阻挡掩模20保护的第一栅极电极层18的掺杂将改变在未受保护的部分中形成的栅极的功函数。离子注入的典型剂量为1E14(=1×1014)到1E16(=1×1016)atoms/cm2或更典型为1E15到5E15atoms/cm2。通常在约2到约8keV的低能量下实施注入。
为了说明性的目的,第一阻挡掩模20覆盖了其中将形成至少一个PFET的部分半导体衬底12A,而留下未受保护的区域12B。参照图1B。在此所示实施例中,第一导电类型22的离子为n性杂质,而第一栅极电极层的未受保护的部分掺有n性杂质。因此,所示的实施例中的区域12B是其中要形成至少一个NFET的区域。
在将第一导电类型22的离子注入未受第一阻挡掩模20保护的区域之后,利用常规的抗蚀剂剥离工艺,例如氧灰化(ash)工艺,除去第一阻挡掩模20。
然后利用常规光刻工艺在结构10上形成第二阻挡掩模24。第二阻挡掩模覆盖了上述先前未受第一阻挡掩模20保护的区域12A和12B中的一个。具体地说,第二阻挡掩模24覆盖了接收第一导电类型的离子的区域。将与第一导电类型22的离子不同的第二导电类型26的离子注入未受第二阻挡掩模24保护的第一栅极电极层18。第二导电类型26的离子可以为n型杂质(即,来自元素周期表的VA族的如P、As、Sb或Bi的元素),或p型杂质(即,来自元素周期表的IIIA族的如B、Al、Ga、In或Tl的元素),这取决于要在未受第二阻挡掩模24保护的区域中制造的CMOS器件的类型,附加一点,第二导电类型26的离子与第一导电类型22的离子的导电性不同。
未受第二阻挡掩模24保护的第一栅极电极层18的掺杂将改变在未受保护的部分中形成的栅极的功函数。离子注入的典型剂量为1E14(=1×1014)到1E16(=1×1016)atoms/cm2或更典型为1E15到5E15atoms/cm2。通常在约2到约8keV的低能量下实施注入。
为了说明性的目的,第二阻挡掩模24覆盖了其中将形成至少一个NFET的部分半导体衬底12B,而留下未受保护的区域12A。参照图1C。在此所示实施例中,第二导电类型26的离子为p性杂质,而第一栅极电极层的未受保护的部分掺有p性杂质。因此,所示的实施例中的区域12A是其中要形成至少一个PFET的区域。
在将第二导电类型26的离子注入未受第二阻挡掩模24保护的区域之后,利用常规的抗蚀剂剥离工艺,例如氧灰化工艺,除去第二阻挡掩模24。
接下来,包括预掺杂的第一栅极电极层18的结构经过热激活步骤,该步骤能够激活注入到第一栅极电极层18中的离子。热激活步骤可以包括烤炉退火、快速热退火、激光退火或峰值退火。尽管使用了退火工艺,但是通常在900℃以上的温度下进行激活退火。在一个实施例中,快速热退火用以激活杂质,而且在约1000℃的温度下进行退火持续少于60秒的时间段。
然后在预掺杂的第一栅极电极层18上形成作为蚀刻停止的阻挡层28。通过例如,CVD、PECVD、化学溶液淀积等的常规淀积工艺形成阻挡层28。阻挡层28的厚度可以根据材料,以及用于淀积它的方法而改变。通常,作为淀积的阻挡层28的厚度为约5到约50nm,而以从约5到约20nm的厚度更为典型。
阻挡层28由抗氧和/或金属扩散的材料构成。用于阻挡层28的材料的示意性实例包括当不局限于:WN、TaN、TiN、TaSiN或其组合和多层。
接下来,在阻挡层28上形成含Si的第二栅极电极层30。含Si的第二栅极电极层30由多晶硅、SiGe(包括多晶SiGe)或其组合或多层构成。含Si的第二栅极电极层30的目的是(1)提供一部分在栅极叠层蚀刻工艺之后可除去的栅极叠层或(2)形成硅化物金属栅极。
含Si的第二栅极电极层30的厚度可以变化;层30的典型厚度范围为从约20到150nm,而以从约40到约100nm的厚度范围更为典型。利用例如在形成第一栅极电极层18中使用的淀积工艺形成含Si的第二栅极电极层30。
然后通过例如CVD或PECVD的常规淀积工艺在含Si的第二栅极电极层30上形成包括,例如,氮化物或氧化物的硬掩模32。作为选择,可以通过热氧化或氮化工艺形成硬掩模32。在一个实施例中,优选由SiN构成硬掩模32。硬掩模32的厚度通常为从约10到约150nm,而以从约30到约60nm的厚度更为典型。
例如,图1D中示出了包括阻挡层28、含Si的第二栅极电极层30和硬掩模32的结构。
接着,使用常规光刻工艺(在附图中未具体示出)在硬掩模32上构图抗蚀剂图案。然后使用例如反应离子蚀刻(RIE)、离子束蚀刻、等离子体蚀刻或激光切除的干蚀刻工艺将抗蚀剂图案的图形转移到图1D所示的各层中,以分别提供构图的栅极叠层34和36。在图1E所示的具体实施例中,构图的栅极叠层34用于PFET,而构图的栅极叠层36用于NFET。其中也预期相反的栅极叠层结构。同样,虽然在区域12A和12B中只示出了单个的构图的栅极叠层,但是本发明预期在每个区域中形成多个这种构图的栅极叠层。在附图中,为了清楚,并为了强调在每个构图的栅极叠层的上部区域中发生了什么,而减小了第一栅极电极层18的厚度。
在提供图1E中所示的构图的栅极叠层之后,接着使用CMOS器件制造领域内公知的标准工艺,提供图1F中所示的结构。具体地说,标准CMOS器件制造工艺包括通过离子注入形成源极/漏极延伸区(未示出)。接下来,在每个构图的栅极叠层的侧壁上形成至少一个隔离层38。至少一个隔离层38由例如氧化物、氮化物、氧氮化物或其多层的绝缘材料构成。至少一个隔离层38的宽度必须足够宽,以使源极和漏极硅化物接触(后续形成)不会超过每个构图的栅极叠层的边缘。通常,当至少一个隔离层38在底部测量时具有从约15到约80nm的宽度时,源极/漏极硅化物不会超过构图的栅极叠层的边缘。
在隔离层形成之后,将源极/漏极扩散区(未具体示出)形成进衬底12中。利用离子注入和退火步骤形成源极/漏极扩散区。退火步骤用于激活在前面的注入步骤中注入的杂质。用于离子注入和退火的条件对于本领域内的技术人员是公知的。
在本发明的一些实施例中,当衬底不包括硅时,可以在衬底的暴露部分上形成含Si层,以提供用于形成硅化物接触的源。可以使用的含Si材料的示意性实例包括,例如,Si、单晶Si、多晶Si、SiGe和无定形Si。本发明的此实施例未在附图中示出。
接下来,利用本领域内公知的标准硅化工艺硅化源极/漏极扩散区,以形成硅化的源极/漏极接触40。这包括在整个结构上形成能与Si反应的金属、在金属上形成氧阻挡层、加热结构以形成硅化物、除去未反应的金属,以及如果需要进行第二个加热步骤。在第一加热步骤没有形成最低电阻相的硅化物的一些情况下需要第二加热步骤。
然后利用例如高密度等离子体淀积的淀积工艺,在图1F中所示的结构上形成由与例如氧化物的硬掩模32不同的材料构成的介质膜42,并将介质膜42平面化到每个构图的栅极叠层的顶部。图1G中示出了包括平面化的介质膜42的结构。包括化学机械抛光(CMP)或研磨的平面化步骤从每个构图的栅极叠层的顶部除去了硬掩模32。结果,平面化的介质膜42具有与含Si的第二栅极电极层30的上表面共面的表面。
然后形成并构图第二硬掩模44,以覆盖PFET的栅极叠层。在所示的实施例中,在包括栅极叠层34的区域12A上形成第二硬掩模44。例如,参考图1H中所示的结构。第二硬掩模44由例如SiN的氮化物构成,并通过淀积、光刻和蚀刻形成。包括用于NFET的栅极叠层36的结构的剩余部分不受第二硬掩模44的保护。
然后利用相对于绝缘体选择性地除去多晶Si或SiGe的蚀刻工艺,除去暴露的区域例如,所示实施例中的区域12B中的含Si的第二栅极叠层30,在阻挡层28上停止。具体地说,使用其中使用例如TMAH、KOH或HF/HNO3的化学蚀剂的湿化学蚀刻工艺,除去NFET器件区,例如,区域12B中的暴露的含Si的第二栅极电极叠层30。
然后在前面被区域12B上的NFET栅极叠层中的含Si的第二电极层30占据的区域中淀积压缩金属46,例如W、Ta、Mo、Nb、V、Pt、Ru、Re、Rh或其合金。术语“压缩金属”指能够给下面的沟道区提供压缩应变的任何金属。通过例如溅射、CVD、PECVD、PVP、化学溶液淀积、金属有机淀积或其它类似淀积工艺的淀积工艺形成压缩金属46。在淀积之后,通过平面化工艺除去在介质膜42的上表面上延伸的压缩金属46,以提供图1H中所示的结构。淀积参数和后面的退火温度是至关紧要的,以使压缩金属46能够保持其压缩状态。
作为实例,在低压(<100mTorr)和高偏置(>0V)下溅射淀积的Ta膜可以显示出高达1-2Gpa的淀积后的压缩应力(参照图6)。只要后面的工艺不需要高于600℃的温度,Ta膜将保持在压缩状态。
使用选择性蚀刻工艺除去整个第二硬掩模44。接下来,并如图1I中所示,在包括前面形成的压缩金属46的区域上形成第三硬掩模48。在所示的实施例中,包括构图的栅极叠层36的区域12B受到第三硬掩模48的保护,而区域12A未得到保护。然后利用相对于绝缘体选择性地除去多晶Si或SiGe的蚀刻工艺,除去暴露区域,例如,所示实施例中的区域12A中的含Si的第二栅极电极30,在阻挡层28上停止。具体地说,使用其中使用例如TMAH、KOH或HF/HNO3的化学蚀剂的湿化学蚀刻工艺除去PFET器件区,例如,区域12A中的暴露的含Si的第二栅极电极叠层30。
然后在前面被区域12A上的PFET栅极叠层中的含Si的第二电极层30占据的区域中淀积拉伸金属50,例如W、Ta、Mo、Nb、V、Pt、Ru、Re、Rh或其合金。术语“拉伸金属”指能够给下面的沟道区提供拉伸应变的任何金属。通过例如溅射、CVD、PECVD、PVP、化学溶液淀积、金属有机淀积或其它类似淀积工艺的淀积工艺形成拉伸金属50。在淀积之后,通过平面化工艺除去在介质膜42的上表面上延伸的拉伸金属50,以提供图1I中所示的结构。
作为实例,在高压(>100mTorr)和无偏置(0V)下溅射淀积的Ta膜可以显示出高达1-2Gpa的淀积后的拉伸应力(参照图6)。在低压(<100mTorr)和高偏置(>0V)下溅射淀积的Ta膜可以显示出高达1-2Gpa的淀积后的压缩应力(参照图6),在高于750℃的温度下退火时此应力会变成拉伸力。
在另一个实施例中,一部分含Si的第二电极30保留在PFET区,例如,12A中,并形成如图1J中所示的硅化物55。通过硅化工艺形成硅化物55,此工艺包括:在包括构图的第二硬掩模48的结构的暴露表面上淀积金属、选择地淀积覆层、第一退火以形成硅化物、如果需要选择性蚀刻包括覆层地任何未反应的金属、以及如果需要进行第二退火步骤。
在含Si的第二栅极电极层30的上表面中形成硅化物(或硅化物接触)55中使用的金属包括任何能够与硅反应以形成金属硅化物的金属。此类金属的实例包括但不局限于:Ti、Ta、W、Co、Ni、Pt、Pd或其合金。在一个实施例中,Co为优选的金属。在此实施例中,需要第二退火步骤。在另一个实施例中,优选Ni和Pt。在此实施例中,通常不进行第二退火步骤。
可以使用包括,例如,溅射、化学气相淀积、蒸发、化学溶液淀积、电镀等的任何常规淀积工艺淀积该金属。
通常在低于第二退火步骤的温度下进行第一退火步骤。通常,在从约300℃到约600℃的温度下,使用连续加热形式或不同斜度(ramp)和浸泡加热循环来进行可以或不可以形成高电阻硅化物相材料的第一退火步骤。更加优选在从约350℃到约550℃的温度下进行第一退火步骤。在从约600℃到约800℃的温度下,使用连续加热形式或不同斜度和浸泡加热循环来进行第二退火步骤。更加优选在从约650℃到约750℃的温度下进行第二退火步骤。第二退火通常会将高阻硅化物转变成低阻硅化物相。
在例如He、Ar、N2或形成气体的气体中执行硅化物退火。硅化物接触退火步骤可以使用不同的气体,或者退火步骤可以在相同的气体中执行。例如,He可以同时在退火步骤中使用,或者He可以在第一退火步骤中使用而在第二退火步骤中可以使用形成气体。
在实施此步骤之后,如上所述,除去第三硬掩模48,以提供与图1I中所示结构类似的结构,除了缺少第三硬掩模48。
然后可以使图1I和1J中所示的所得结构经过BOEL(后段制程)工艺步骤,以在延伸到硅化的源极/漏极区的介质膜42中,也在每个构图的栅极叠层的上面形成接触过孔。
如此形成的所得半导体结构(参考图1I和1J)包括半导体衬底12的表面上的至少一个NFET36和至少一个PFET34,其中所述至少一个NFET36具有包括栅极介质16、第一栅极导体层18、阻挡层28和压缩金属46的栅极叠层结构,而所述至少一个PFET34具有包括栅极介质16、第一栅极电极层18、阻挡层28、拉伸金属50或第二含Si的栅极电极层30和硅化物55的栅极叠层结构。拉伸金属50或硅化物55在PFET器件的沟道中产生局部机械应力,此应力提高了器件的载流子迁移率,而压缩金属46在NFET器件的沟道中产生局部机械应力。
现在将更详细地描述图2A-2E中所示的本发明地第二方法。本发明的第二方法开始于提供图2A中所示的结构100。结构100包括半导体衬底12、至少一个沟槽隔离区14、栅极介质16、第一栅极电极层18、阻挡层28、第二栅极电极层105和硬掩模32。使用上述形成图1D中所示结构的第一方法中的工艺步骤形成图2A中所示的结构,除了第二栅极电极层105由拉伸金属或硅化物构成。通过如CVD、PECVD、溅射等淀积工艺形成第二栅极电极层105,而且第二栅极电极层105通常具有淀积之后从约20到约100nm的厚度。通过常规硅化工艺形成硅化物。为了清楚,在本发明名的此实施例中未示出对第一栅极电极18的不同注入。然而,要实施它们以形成不同的区域12A和12B。
然后通过淀积在图2A中所示的结构上形成抗蚀剂(未示出),并在此后通过光刻构图抗蚀剂。然后通过蚀刻将抗蚀剂图形转移到下面的硬掩模32。在提供构图的硬掩模之后,蚀刻包括层16、18、28和105的栅极叠层,以分别形成构图的栅极叠层34和36。图2B中示出了包括构图的栅极叠层34和36的结构。
接下来,实施如上所述的关于制造图1F中所示结构的标准工艺,以形成图2C中所示的结构。标准工艺包括如上面在本发明的第一方法中所描述的形成至少一个隔离层38,以及形成硅化的源极/漏极接触40。
然后通过淀积形成和平面化介质膜42,以提供图2D中所示的结构。在本发明的此实施例中使用的淀积和平面化与上面所述的关于形成图1G中所示结构的一样。
然后在PFET所在的区域,例如12A上形成阻挡掩模(未示出),并利用相对于介质材料选择性地除去第二栅极电极层105的蚀刻工艺,从其中将要形成NFET的区域上除去第二栅极电极层105。例如,可以使用H2O2∶H2SO4从其中将要在后面形成NFET地区域上选择性地蚀刻第二栅极电极层105。选择性蚀刻在阻挡层28的上表面停止。
然后在包括阻挡掩模的图2D中所示的结构上形成压缩金属46,并在此后平面化该结构,以填充其中第二栅极电极层105在前面被除去的构图的栅极叠层36。平面化工艺也从结构除去了阻挡掩模。例如,图2E中示出了所得结构。
这样形成的所得半导体结构包括半导体衬底12的表面上的至少一个NFET36和至少一个PFET34,其中所述至少一个NFET36具有包括栅极介质16、第一栅极电极层18、阻挡层28、压缩金属46的栅极叠层结构,而所述至少一个PFET34具有包括栅极介质16、第一栅极电极层18、阻挡层28和拉伸金属或例如第二栅极电极层105的硅化物的栅极叠层结构。剩余的包括拉伸金属或硅化物的第二栅极电极层105在PFET器件的沟道中产生局部机械应力,此应力可以提高该器件的载流子迁移率,而压缩金属46在NFET的沟道上提供局部机械应力。
在上述每个实施例中,通常拉伸或压缩金属在PFET或NFET的沟道中提供从约0.2到约2GPa的局部机械应力,而以从约0.5到约1GPa的栅极应力更为典型。PFET中的硅化物金属提供从约0.5到约2GPa的应力,而以从约0.6到约1.6GPa的栅极应力更为典型。
图3通过截面图示出了用Lpoly=60nm模拟的结构。图4为对于图3中所示结构的所得应力曲线,示出了沟道区中来自2GPa的拉伸硅化物的0.6GPa的应力。
图5是应力与硅化物类型的关系图,示出了在形成之后不同硅化物中的拉伸应力(0.5-2.0GPa)。也示出了在形成之前硅化物金属的最初淀积后的应力。在图中,未填充方块表示淀积后的金属,而填充方块代表退火,即,硅化之后的金属。
图6是从J.Appl.Phys.72(10),4918(1992)复制的现有图表,示出了作为淀积压力的函数的最初应变的Ta膜中的应力。图7是从J.Appl.Phys.72(10),4918(1992)复制的现有图表,示出了作为退火温度的函数的压缩Ta膜中的应力。
尽管参考其优选实施例具体示出和描述了本发明,本领域内的技术人员应该理解,在不脱离本发明的精神和范围的情况下,可以在形式和细节上进行上述和其它改变。因此,本发明旨在不限于描述和示出的具体形式和细节,而是落入所附权利要求的范围之内。
Claims (27)
1.一种半导体结构,包括:半导体衬底表面上的至少一个NFET和至少一个PFET,其中所述至少一个NFET具有包括栅极介质、第一栅极电极层、阻挡层和压缩金属的栅极叠层结构,而所述至少一个PFET具有包括栅极介质、第一栅极电极层、阻挡层和拉伸金属或硅化物的栅极叠层结构。
2.根据权利要求1的半导体结构,其中所述半导体衬底包括Si、Ge、SiGe、SiC、SiGeC、Ga、GaAs、InAs、InP、Si/SiGe、绝缘体上硅(SOI)或绝缘体上硅锗。
3.根据权利要求1的半导体结构,其中沟槽隔离区将所述至少一个NFET与所述至少一个PFET分开,所述沟槽隔离区位于所述半导体衬底中。
4.根据权利要求1的半导体结构,其中所述栅极介质包括氧化物、氮化物、氧氮化物、硅酸盐或其组合与多层。
5.根据权利要求1的半导体结构,其中所述第一栅极电极层包括多晶硅、导电金属、包含至少一种导电金属的合金、导电硅化物、导电氮化物、多晶SiGe或其组合与多层。
6.根据权利要求1的半导体结构,其中用第一导电类型的杂质掺杂所述第一栅极电极层的一部分,而用第二导电类型的杂质掺杂所述第一栅极导体层的另一部分,其中所述第一导电类型的杂质与所述第二导电类型的杂质不同。
7.根据权利要求1的半导体结构,其中所述阻挡层包括WN、TaN、TiN或TaSiN中的一种。
8.根据权利要求1的半导体结构,其中所述含Si的第二栅极电极层包括多晶硅或多晶SiGe中的一种。
9.根据权利要求1的半导体结构,其中所述拉伸金属包括W、Ta、Mo、Nb、V、Pt、Ru、Re或Rh中的一种。
10.根据权利要求1的半导体结构,其中所述硅化物为包括Ti、Ta、W、Co、Ni、Pt或Pd或其合金中的一种的金属硅化物。
11.根据权利要求1的半导体结构,还包括具有至少延伸到位于所述半导体衬底中的硅化的源极/漏极区的导电填充过孔的介质膜。
12.一种形成具有局部机械栅极应力的半导体结构的方法,包括以下步骤:
提供具有位于半导体衬底表面上的栅极介质、第一栅极电极层、阻挡层、含Si的第二栅极电极层和硬掩模的半导体结构,所述半导体衬底包含沟槽隔离区;
构图所述层,以提供用于NFET的至少一个构图的栅极叠层和用于PFET的至少一个构图的栅极叠层,所述NFET和PFET通过所述沟槽隔离区分开;
在每个所述构图的栅极叠层的侧壁上形成至少一个隔离层,并在邻近每个所述构图的栅极叠层的所述半导体衬底中形成硅化的源极/漏极区;
形成平面化的介质膜,所述膜暴露每个所述构图的栅极叠层的上表面;
在用于所述PFET的所述至少一个构图的栅极叠层中选择性地形成硅化物或拉伸金属;以及
在用于所述NFET的所述至少一个构图的栅极叠层中选择性地形成压缩金属。
13.根据权利要求12的方法,还包括将第一导电类型的杂质选择性地注入所述第一栅极电极层的一部分中,而将与所述第一导电类型的杂质不同的第二导电类型的杂质选择性地注入所述第一栅极电极层的另一部分中,其中在所述构图步骤之前实施所述注入步骤。
14.根据权利要求12的方法,其中所述选择性地形成硅化物的步骤包括在所述NFET上形成硬掩模,在包括所述PFET的暴露区域上形成金属,以及进行硅化物退火步骤。
15.根据权利要求12的方法,其中所述选择性地形成拉伸金属的步骤包括在所述NFET上形成硬掩模,除去所述PFET中的所述含Si的第二栅极电极层的暴露部分,以及在前面包括所述含Si的第二栅极电极层的所述区域中淀积所述拉伸金属。
16.根据权利要求12的方法,其中所述选择性地形成压缩金属的步骤包括在所述PFET上形成硬掩模,除去所述NFET中的所述含Si的第二栅极电极层的暴露部分,以及在前面包括所述含Si的第二栅极电极层的所述区域中淀积所述压缩金属。
17.根据权利要求12的方法,其中所述拉伸金属包括Ta。
18.根据权利要求12的方法,其中所述压缩金属包括Ta。
19.根据权利要求12的方法,其中在低压和高衬底偏置下溅射淀积所述压缩金属。
20.根据权利要求12的方法,其中在高压和无衬底偏置下溅射淀积所述拉伸金属。
21.一种形成具有局部机械栅极应力的半导体结构的方法,包括以下步骤:
提供具有位于半导体衬底表面上的栅极介质、第一栅极电极层、阻挡层、第二栅极电极层和硬掩模的半导体结构,所述半导体衬底包含沟槽隔离区而所述第二栅极电极层包括拉伸金属或硅化物;
构图所述层,以提供用于NFET的至少一个构图的栅极叠层和用于PFET的至少一个构图的栅极叠层,所述NFET和PFET通过所述沟槽隔离区分开;
在每个所述构图的栅极叠层的侧壁上形成至少一个隔离层,并在邻近每个所述构图的栅极叠层的所述半导体衬底中形成硅化的源极/漏极区;
形成平面化的介质膜,所述膜暴露每个所述构图的栅极叠层的上表面;以及
在用于所述NFET的所述至少一个构图的栅极叠层中选择性地形成压缩金属。
22.根据权利要求21的方法,还包括将第一导电类型的杂质选择性地注入所述第一栅极电极层的一部分中,而将与所述第一导电类型的杂质不同的第二导电类型的杂质选择性地注入所述第一栅极电极层的另一部分中,其中在所述构图步骤之前进行所述注入步骤。
23.根据权利要求21的方法,其中所述选择性地形成压缩金属的步骤包括在所述PFET上形成硬掩模,除去所述NFET中的所述含Si的第二栅极电极层的暴露部分,以及在前面包括所述含Si的第二栅极电极层的所述区域中淀积所述压缩金属。
24.根据权利要求21的方法,其中所述拉伸金属包括Ta。
25.根据权利要求21的方法,其中所述压缩金属包括Ta。
26.根据权利要求21的方法,其中在低压和高衬底偏置下溅射淀积所述压缩金属。
27.根据权利要求21的方法,其中在高压和无衬底偏置下溅射淀积所述拉伸金属。
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US10/905,101 US7173312B2 (en) | 2004-12-15 | 2004-12-15 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN103548145A (zh) * | 2011-06-23 | 2014-01-29 | 三菱电机株式会社 | 半导体装置以及半导体装置的制造方法 |
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Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006156807A (ja) * | 2004-11-30 | 2006-06-15 | Toshiba Corp | 半導体装置およびその製造方法 |
KR100596487B1 (ko) * | 2005-04-12 | 2006-07-04 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
JP4880958B2 (ja) * | 2005-09-16 | 2012-02-22 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP5109660B2 (ja) * | 2005-09-21 | 2012-12-26 | 日本電気株式会社 | 半導体装置 |
US20070200149A1 (en) * | 2006-02-28 | 2007-08-30 | Veronika Polei | Semiconductor device and method of production |
US20070281405A1 (en) * | 2006-06-02 | 2007-12-06 | International Business Machines Corporation | Methods of stressing transistor channel with replaced gate and related structures |
US7605045B2 (en) * | 2006-07-13 | 2009-10-20 | Advanced Micro Devices, Inc. | Field effect transistors and methods for fabricating the same |
US8304342B2 (en) * | 2006-10-31 | 2012-11-06 | Texas Instruments Incorporated | Sacrificial CMP etch stop layer |
JP2008117963A (ja) * | 2006-11-06 | 2008-05-22 | Nec Electronics Corp | 電界効果トランジスタおよび半導体装置、ならびにそれらの製造方法 |
JP5100137B2 (ja) * | 2007-01-26 | 2012-12-19 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
US20080203485A1 (en) * | 2007-02-28 | 2008-08-28 | International Business Machines Corporation | Strained metal gate structure for cmos devices with improved channel mobility and methods of forming the same |
US20080217700A1 (en) * | 2007-03-11 | 2008-09-11 | Doris Bruce B | Mobility Enhanced FET Devices |
US20080242072A1 (en) * | 2007-03-26 | 2008-10-02 | Texas Instruments Incorporated | Plasma dry etch process for metal-containing gates |
JP2008244059A (ja) * | 2007-03-27 | 2008-10-09 | Renesas Technology Corp | 半導体装置の製造方法 |
US7989901B2 (en) * | 2007-04-27 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with improved source/drain regions with SiGe |
TW200910526A (en) * | 2007-07-03 | 2009-03-01 | Renesas Tech Corp | Method of manufacturing semiconductor device |
US7785952B2 (en) * | 2007-10-16 | 2010-08-31 | International Business Machines Corporation | Partially and fully silicided gate stacks |
US7642153B2 (en) * | 2007-10-23 | 2010-01-05 | Texas Instruments Incorporated | Methods for forming gate electrodes for integrated circuits |
EP2061076A1 (en) * | 2007-11-13 | 2009-05-20 | Interuniversitair Micro-Elektronica Centrum Vzw | Dual work function device with stressor layer and method for manufacturing the same |
US7790541B2 (en) * | 2007-12-04 | 2010-09-07 | International Business Machines Corporation | Method and structure for forming multiple self-aligned gate stacks for logic devices |
US7745270B2 (en) * | 2007-12-28 | 2010-06-29 | Intel Corporation | Tri-gate patterning using dual layer gate stack |
US7955926B2 (en) * | 2008-03-26 | 2011-06-07 | International Business Machines Corporation | Structure and method to control oxidation in high-k gate structures |
US8349732B2 (en) * | 2008-07-18 | 2013-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implanted metal silicide for semiconductor device |
KR101603500B1 (ko) | 2008-12-10 | 2016-03-15 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8288795B2 (en) | 2010-03-02 | 2012-10-16 | Micron Technology, Inc. | Thyristor based memory cells, devices and systems including the same and methods for forming the same |
US8507966B2 (en) | 2010-03-02 | 2013-08-13 | Micron Technology, Inc. | Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same |
US9608119B2 (en) * | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
US8513722B2 (en) | 2010-03-02 | 2013-08-20 | Micron Technology, Inc. | Floating body cell structures, devices including same, and methods for forming same |
US9646869B2 (en) | 2010-03-02 | 2017-05-09 | Micron Technology, Inc. | Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices |
CN102299154B (zh) * | 2010-06-22 | 2013-06-12 | 中国科学院微电子研究所 | 半导体结构及其制作方法 |
US8461034B2 (en) * | 2010-10-20 | 2013-06-11 | International Business Machines Corporation | Localized implant into active region for enhanced stress |
US8598621B2 (en) | 2011-02-11 | 2013-12-03 | Micron Technology, Inc. | Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor |
US8952418B2 (en) * | 2011-03-01 | 2015-02-10 | Micron Technology, Inc. | Gated bipolar junction transistors |
US8519431B2 (en) | 2011-03-08 | 2013-08-27 | Micron Technology, Inc. | Thyristors |
US8772848B2 (en) | 2011-07-26 | 2014-07-08 | Micron Technology, Inc. | Circuit structures, memory circuitry, and methods |
CN102832135A (zh) * | 2012-09-05 | 2012-12-19 | 北京大学 | 锗、三五族半导体材料衬底上制备FinFET的方法 |
US10438856B2 (en) | 2013-04-03 | 2019-10-08 | Stmicroelectronics, Inc. | Methods and devices for enhancing mobility of charge carriers |
US9105662B1 (en) | 2014-01-23 | 2015-08-11 | International Business Machines Corporation | Method and structure to enhance gate induced strain effect in multigate device |
US9947772B2 (en) | 2014-03-31 | 2018-04-17 | Stmicroelectronics, Inc. | SOI FinFET transistor with strained channel |
CN111801796A (zh) * | 2018-02-08 | 2020-10-20 | 英特尔公司 | 集成晶体管器件的硅化物结构及其提供方法 |
US10832960B2 (en) * | 2019-02-07 | 2020-11-10 | International Business Machines Corporation | Quadruple gate dielectric for gate-all-around transistors |
Family Cites Families (90)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3602841A (en) * | 1970-06-18 | 1971-08-31 | Ibm | High frequency bulk semiconductor amplifiers and oscillators |
US4853076A (en) * | 1983-12-29 | 1989-08-01 | Massachusetts Institute Of Technology | Semiconductor thin films |
US4655415A (en) * | 1985-01-24 | 1987-04-07 | The Garrett Corporation | Helicopter flotation |
US4665415A (en) | 1985-04-24 | 1987-05-12 | International Business Machines Corporation | Semiconductor device with hole conduction via strained lattice |
EP0219641B1 (de) * | 1985-09-13 | 1991-01-09 | Siemens Aktiengesellschaft | Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung |
US4958213A (en) * | 1987-12-07 | 1990-09-18 | Texas Instruments Incorporated | Method for forming a transistor base region under thick oxide |
US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
US5006913A (en) * | 1988-11-05 | 1991-04-09 | Mitsubishi Denki Kabushiki Kaisha | Stacked type semiconductor device |
US5108843A (en) * | 1988-11-30 | 1992-04-28 | Ricoh Company, Ltd. | Thin film semiconductor and process for producing the same |
US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
US5060030A (en) * | 1990-07-18 | 1991-10-22 | Raytheon Company | Pseudomorphic HEMT having strained compensation layer |
US5081513A (en) * | 1991-02-28 | 1992-01-14 | Xerox Corporation | Electronic device with recovery layer proximate to active layer |
US5371399A (en) * | 1991-06-14 | 1994-12-06 | International Business Machines Corporation | Compound semiconductor having metallic inclusions and devices fabricated therefrom |
US5134085A (en) * | 1991-11-21 | 1992-07-28 | Micron Technology, Inc. | Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories |
US5391510A (en) * | 1992-02-28 | 1995-02-21 | International Business Machines Corporation | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps |
US6008126A (en) * | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US5561302A (en) * | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US5670798A (en) * | 1995-03-29 | 1997-09-23 | North Carolina State University | Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same |
US5679965A (en) * | 1995-03-29 | 1997-10-21 | North Carolina State University | Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same |
US5557122A (en) * | 1995-05-12 | 1996-09-17 | Alliance Semiconductors Corporation | Semiconductor electrode having improved grain structure and oxide growth properties |
US5861340A (en) * | 1996-02-15 | 1999-01-19 | Intel Corporation | Method of forming a polycide film |
KR100213196B1 (ko) * | 1996-03-15 | 1999-08-02 | 윤종용 | 트렌치 소자분리 |
US6403975B1 (en) * | 1996-04-09 | 2002-06-11 | Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev | Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates |
US5880040A (en) * | 1996-04-15 | 1999-03-09 | Macronix International Co., Ltd. | Gate dielectric based on oxynitride grown in N2 O and annealed in NO |
US5861651A (en) * | 1997-02-28 | 1999-01-19 | Lucent Technologies Inc. | Field effect devices and capacitors with improved thin film dielectrics and method for making same |
US5940736A (en) * | 1997-03-11 | 1999-08-17 | Lucent Technologies Inc. | Method for forming a high quality ultrathin gate oxide layer |
US6309975B1 (en) * | 1997-03-14 | 2001-10-30 | Micron Technology, Inc. | Methods of making implanted structures |
US6025280A (en) * | 1997-04-28 | 2000-02-15 | Lucent Technologies Inc. | Use of SiD4 for deposition of ultra thin and controllable oxides |
US5960297A (en) * | 1997-07-02 | 1999-09-28 | Kabushiki Kaisha Toshiba | Shallow trench isolation structure and method of forming the same |
JP3139426B2 (ja) * | 1997-10-15 | 2001-02-26 | 日本電気株式会社 | 半導体装置 |
US6066545A (en) * | 1997-12-09 | 2000-05-23 | Texas Instruments Incorporated | Birdsbeak encroachment using combination of wet and dry etch for isolation nitride |
US6274421B1 (en) * | 1998-01-09 | 2001-08-14 | Sharp Laboratories Of America, Inc. | Method of making metal gate sub-micron MOS transistor |
KR100275908B1 (ko) * | 1998-03-02 | 2000-12-15 | 윤종용 | 집적 회로에 트렌치 아이솔레이션을 형성하는방법 |
US6361885B1 (en) * | 1998-04-10 | 2002-03-26 | Organic Display Technology | Organic electroluminescent materials and device made from such materials |
US6165383A (en) * | 1998-04-10 | 2000-12-26 | Organic Display Technology | Useful precursors for organic electroluminescent materials and devices made from such materials |
US5989978A (en) * | 1998-07-16 | 1999-11-23 | Chartered Semiconductor Manufacturing, Ltd. | Shallow trench isolation of MOSFETS with reduced corner parasitic currents |
JP4592837B2 (ja) * | 1998-07-31 | 2010-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6319794B1 (en) * | 1998-10-14 | 2001-11-20 | International Business Machines Corporation | Structure and method for producing low leakage isolation devices |
US6235598B1 (en) * | 1998-11-13 | 2001-05-22 | Intel Corporation | Method of using thick first spacers to improve salicide resistance on polysilicon gates |
US6117722A (en) * | 1999-02-18 | 2000-09-12 | Taiwan Semiconductor Manufacturing Company | SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof |
US6255169B1 (en) * | 1999-02-22 | 2001-07-03 | Advanced Micro Devices, Inc. | Process for fabricating a high-endurance non-volatile memory device |
US6284626B1 (en) * | 1999-04-06 | 2001-09-04 | Vantis Corporation | Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench |
US6281532B1 (en) * | 1999-06-28 | 2001-08-28 | Intel Corporation | Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering |
US6656822B2 (en) * | 1999-06-28 | 2003-12-02 | Intel Corporation | Method for reduced capacitance interconnect system using gaseous implants into the ILD |
US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
US6228694B1 (en) * | 1999-06-28 | 2001-05-08 | Intel Corporation | Method of increasing the mobility of MOS transistors by use of localized stress regions |
KR100332108B1 (ko) * | 1999-06-29 | 2002-04-10 | 박종섭 | 반도체 소자의 트랜지스터 및 그 제조 방법 |
TW426940B (en) | 1999-07-30 | 2001-03-21 | United Microelectronics Corp | Manufacturing method of MOS field effect transistor |
US6483171B1 (en) * | 1999-08-13 | 2002-11-19 | Micron Technology, Inc. | Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same |
US6284623B1 (en) * | 1999-10-25 | 2001-09-04 | Peng-Fei Zhang | Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect |
US6476462B2 (en) * | 1999-12-28 | 2002-11-05 | Texas Instruments Incorporated | MOS-type semiconductor device and method for making same |
US6221735B1 (en) * | 2000-02-15 | 2001-04-24 | Philips Semiconductors, Inc. | Method for eliminating stress induced dislocations in CMOS devices |
US6531369B1 (en) * | 2000-03-01 | 2003-03-11 | Applied Micro Circuits Corporation | Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe) |
US6368931B1 (en) * | 2000-03-27 | 2002-04-09 | Intel Corporation | Thin tensile layers in shallow trench isolation and method of making same |
US6493497B1 (en) * | 2000-09-26 | 2002-12-10 | Motorola, Inc. | Electro-optic structure and process for fabricating same |
US6501121B1 (en) * | 2000-11-15 | 2002-12-31 | Motorola, Inc. | Semiconductor structure |
US7312485B2 (en) * | 2000-11-29 | 2007-12-25 | Intel Corporation | CMOS fabrication process utilizing special transistor orientation |
US6563152B2 (en) * | 2000-12-29 | 2003-05-13 | Intel Corporation | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
US20020086497A1 (en) * | 2000-12-30 | 2002-07-04 | Kwok Siang Ping | Beaker shape trench with nitride pull-back for STI |
US6265317B1 (en) | 2001-01-09 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Top corner rounding for shallow trench isolation |
US6403486B1 (en) * | 2001-04-30 | 2002-06-11 | Taiwan Semiconductor Manufacturing Company | Method for forming a shallow trench isolation |
US6531740B2 (en) * | 2001-07-17 | 2003-03-11 | Motorola, Inc. | Integrated impedance matching and stability network |
US6498358B1 (en) * | 2001-07-20 | 2002-12-24 | Motorola, Inc. | Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating |
US6908810B2 (en) * | 2001-08-08 | 2005-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation |
JP2003060076A (ja) * | 2001-08-21 | 2003-02-28 | Nec Corp | 半導体装置及びその製造方法 |
WO2003025984A2 (en) * | 2001-09-21 | 2003-03-27 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US20030057184A1 (en) * | 2001-09-22 | 2003-03-27 | Shiuh-Sheng Yu | Method for pull back SiN to increase rounding effect in a shallow trench isolation process |
US6656798B2 (en) * | 2001-09-28 | 2003-12-02 | Infineon Technologies, Ag | Gate processing method with reduced gate oxide corner and edge thinning |
US6635506B2 (en) * | 2001-11-07 | 2003-10-21 | International Business Machines Corporation | Method of fabricating micro-electromechanical switches on CMOS compatible substrates |
US6461936B1 (en) * | 2002-01-04 | 2002-10-08 | Infineon Technologies Ag | Double pullback method of filling an isolation trench |
JP2003243531A (ja) * | 2002-02-13 | 2003-08-29 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6621392B1 (en) * | 2002-04-25 | 2003-09-16 | International Business Machines Corporation | Micro electromechanical switch having self-aligned spacers |
US7388259B2 (en) * | 2002-11-25 | 2008-06-17 | International Business Machines Corporation | Strained finFET CMOS device structures |
US6825529B2 (en) * | 2002-12-12 | 2004-11-30 | International Business Machines Corporation | Stress inducing spacers |
US6974981B2 (en) * | 2002-12-12 | 2005-12-13 | International Business Machines Corporation | Isolation structures for imposing stress patterns |
US6717216B1 (en) * | 2002-12-12 | 2004-04-06 | International Business Machines Corporation | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device |
US6887798B2 (en) * | 2003-05-30 | 2005-05-03 | International Business Machines Corporation | STI stress modification by nitrogen plasma treatment for improving performance in small width devices |
US7279746B2 (en) * | 2003-06-30 | 2007-10-09 | International Business Machines Corporation | High performance CMOS device structures and method of manufacture |
JP4449374B2 (ja) * | 2003-09-04 | 2010-04-14 | 株式会社日立製作所 | 半導体装置 |
US6890808B2 (en) * | 2003-09-10 | 2005-05-10 | International Business Machines Corporation | Method and structure for improved MOSFETs using poly/silicide gate height control |
US7119403B2 (en) * | 2003-10-16 | 2006-10-10 | International Business Machines Corporation | High performance strained CMOS devices |
US8008724B2 (en) * | 2003-10-30 | 2011-08-30 | International Business Machines Corporation | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers |
US6977194B2 (en) * | 2003-10-30 | 2005-12-20 | International Business Machines Corporation | Structure and method to improve channel mobility by gate electrode stress modification |
US7015082B2 (en) * | 2003-11-06 | 2006-03-21 | International Business Machines Corporation | High mobility CMOS circuits |
US7122849B2 (en) * | 2003-11-14 | 2006-10-17 | International Business Machines Corporation | Stressed semiconductor device structures having granular semiconductor material |
US7247912B2 (en) * | 2004-01-05 | 2007-07-24 | International Business Machines Corporation | Structures and methods for making strained MOSFETs |
US20050214998A1 (en) * | 2004-03-26 | 2005-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Local stress control for CMOS performance enhancement |
US7053400B2 (en) * | 2004-05-05 | 2006-05-30 | Advanced Micro Devices, Inc. | Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility |
-
2004
- 2004-12-15 US US10/905,101 patent/US7173312B2/en not_active Expired - Fee Related
-
2005
- 2005-11-09 CN CN200510115838.6A patent/CN1790715A/zh active Pending
-
2006
- 2006-12-30 US US11/618,751 patent/US7314789B2/en active Active
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US9240351B2 (en) | 2009-12-31 | 2016-01-19 | Institute of Microelectronics, Chinese Academy of Sciences | Field effect transistor device with improved carrier mobility and method of manufacturing the same |
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US20070111421A1 (en) | 2007-05-17 |
US7173312B2 (en) | 2007-02-06 |
US20060124974A1 (en) | 2006-06-15 |
US7314789B2 (en) | 2008-01-01 |
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