CN1819297B - 侧壁有源接脚存储器及其制造方法 - Google Patents

侧壁有源接脚存储器及其制造方法 Download PDF

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CN1819297B
CN1819297B CN2005101248240A CN200510124824A CN1819297B CN 1819297 B CN1819297 B CN 1819297B CN 2005101248240 A CN2005101248240 A CN 2005101248240A CN 200510124824 A CN200510124824 A CN 200510124824A CN 1819297 B CN1819297 B CN 1819297B
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electrode
impedance material
programmable impedance
sidewall
width
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CN1819297A (zh
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龙翔澜
陈士弘
陈逸舟
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Macronix International Co Ltd
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Abstract

本发明涉及一种形成具有复合层的存储单元的方法。此复合层具有一第一电极、覆盖此第一电极的一绝缘层与覆盖此绝缘层的一第二电极。形成一侧壁间隙壁，此侧壁间隙壁包括一个具有可程序化阻抗材料与第一电极及第二电极形成电连接。通过沉积覆盖在复合层侧壁上的可程序化阻抗材料层、各向异性地蚀刻此可程序化阻抗材料层，以除去非侧壁的部分与根据一图案选择性地蚀刻此可程序化阻抗材料层，以定义该侧壁间隙壁的宽度。在实施例中，该宽度约小于等于40纳米。

Description

侧壁有源接脚存储器及其制造方法
技术领域
本发明涉及一种可程序化阻抗材料的高密度存储装置及其制造方法，特别是涉及一种以相变化为依据的存储材料。 
背景技术
硫属化合物(Chalcogenide)广泛运用于可擦写的光盘片上。此材料具有至少两种固相变化，通常为结晶相(amorphous)及非晶相(crystalline)。激光脉冲波用于光盘片上以转换相位且在相变化后读取硫属化合物材料上的光学特性。 
应用电流脉波也可使硫属化合物达成相变化，此特性使用可程序化阻抗形成非挥发性存储器电路。 
发展的方向之一为朝向使用小量的可程序化阻抗材料，特别是在微小细孔当中。而关于发展微小细孔的专利有：Ovshinsky，″Multibit Single Cell Memory Element Having Tapered Contact，″美国专利第5,687,112号，issued  November 11，1997；Zahorik等人，″Method of Making Chalogenide[sic]Memory Device，″美国专利第5,789,277号，issuedAugust 4，1998；Doan等人，″Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same，″美国专利第6,150,253号，issued November 21，2000。 
申请人于美国专利申请书刊载No.US-2004-0026686-A1上揭露了一相变化存储单元，其相变化元件包括了在电极/电介质/电极的复合层上的一侧壁。数据的储存通过电流在相变化材料的结晶相与非晶相之间转变而达成。电流加热此材料且在两状态之间造成变化。施加一低电流使得状态由非晶相改变至结晶相；施加一高电流，则使得状态由结晶相改变至非晶相，于此称为重置(reset)。降低使相变化材料由结晶相改变至非晶相的重置电流的大小实为必要。降低重置电流的大小的方法即为减少相变化材料元件(element)在存储单元中的大小及减少于电极及相变化材料间接触面积的大小。 
因此，形成具有小量可程序化阻抗材料的存储单元的方法及结构的设计机会大大提升。 
发明内容
本发明包括形成狭窄侧壁间隙壁及接脚的存储单元的装置及方法，该狭窄侧壁间隙壁或接脚具有可程序化阻抗材料。 
本发明的实施例之一就是在提供一种形成存储单元的方法，包括形成一电极复合层。该电极复合层具有一第一电极，一绝缘层配置于第一电极之上，一第二电极配置于绝缘层之上，在电极复合层的至少一绝缘层上具有一侧壁。一侧壁间隙壁包括一可程序化阻抗材料，与第一电极及第二电极电连接。该侧壁间隙壁具有一长度、一宽度与一厚度。长度沿着侧壁从第一电极延展至第二电极，宽度与长度垂直，而厚度取决于用以形成侧壁间隙壁的相变化材料的厚度。间隙壁以沉积可程序化阻抗材料在电极复合层上而形成，各向异性蚀刻可程序化阻抗材料以移除非侧壁的区域，且依据一图案选择性地蚀刻可程序化阻抗材料用以界定该侧壁间隙壁的宽度。在本实施例中，宽度小于50纳米且优选地为40纳米或小于40纳米。 
选择性蚀刻可程序化阻抗材料依据一图案以界定具有狭小宽度的侧壁间隙壁，一技术包括形成一具有光刻图案的蚀刻光掩模以界定一光刻宽度，然后缩减蚀刻光掩模以提供一缩减光掩模以界定一用以定义侧壁间隙壁宽度的图案。在一例子中，蚀刻光掩模包括一光致抗蚀剂，该光致抗蚀剂被含氧(oxygen based)的等离子体各向异性蚀刻以形成一缩减光掩模。在另一例子中，蚀刻光掩模包括一使用光刻工艺形成的硬掩模，此硬掩模被蚀刻以缩减宽度以形成缩减光掩模。 
在存储单元中的相变化接脚的工作区的三维尺寸优选的是小于50纳米，且皆小于用以形成存储单元的光刻工艺的最小特征尺寸。此三维尺寸通过相变化材料的薄膜厚度、电介质的薄膜厚度及缩减光掩模所界定。因此，存储单元的尺寸(即为相变化材料的体积)非常小(小于F3，其中F为用以制造存储单元的工艺的最小光刻特征尺寸)。相变化材料的存储单元包括一在电极复合层的侧壁上的狭窄接脚。接触区域位于至少一上电极及下电极，且相变化材料接脚的高度由次光刻程通过电极层的厚度所定义，且光致抗蚀剂图案缩减工艺用以界定接点的宽度。小存储单元及小接点区域允许提供具有非常小的重置电流及低能源消耗的存储器。 
根据本发明的实施例之一，提出一种存储装置包括电极复合层，此电极复合层包括一第一电极、一电介层及一第二电极、一间隙壁。电介层配置于第一电极之上，第二电极配置电介层之上。电极复合层具有一侧壁至少覆盖在至该绝缘层。具有可程序化阻抗材料的间隙壁在侧壁上与第一电极及第二电极电连接。间隙壁具有一长度、一宽度及一厚度，长度沿着侧壁从第一电极延展至第二电极，宽度与长度垂直。在本实例中所揭露的技术，间隙壁的宽度及厚度少于40纳米。可程序化阻抗材料包括一相变化材料，为可逆地可程序化。 
根据本发明的另一实施例，提出一种存储器阵列，包括多个具有通道晶体管的存储装置，排列于高密度的行列的阵列中。在半导体基板上，通道晶体管包括源极及漏极，以及一栅极耦接至沿着存储单元的列的字线。存储单元形成于集成电路的通道晶体管之上，具有从相对应的通道晶体管漏极延展至在个别存储装置的下电极的多个接点插塞结构。图案化金属层提供多个接点，涂布在一电介填充层上，该电介填充层涂布在该些存储单元上，该些接点与在该些位线中的具有相对应该些位线的各该些存储单元的该些上电极接触。在本实施例中，二列的存储单元共有源接点，此源接点具有一共源线耦接至源接点，且大致上与阵列中的字线平行。 
根据本发明的再一实施例，提出一种形成相变化接脚的方法。此相变化接脚可形成一非常小的接脚在一集成电路或其它装置上。此接脚的尺寸小于最小特征尺寸，第一代光刻工艺即可提供。举例来说，小尺寸的接脚可形成于其它型式的薄膜复合层之上，例如是薄膜电介质的复合层，具有或不具有接触接脚的电极层。纳米技术装置使用非相变化材料以提供非常小的接脚结构，比如是金属、电介质、有机材料、半导体等。 
为让本发明的上述目的、特征、和优点能更明显易懂，以下配合附图以及优选实施例，以更详细地说明本发明。 
附图说明
图1绘示一侧壁有源接脚存储单元10的透视图。 
图2绘示一存储阵列的示意图。 
图3绘示依照本发明优选实施例的集成电路的简化方块图。 
 图4绘示多个侧壁有源接脚相变化随机存取存储单元100-103的剖面图。 
图5绘示结构99在前段工艺后形成标准的互补金氧半导体元件依照本实施例在图2的阵列中的字线、共源线及通道晶体管。 
图6A绘示光掩模图案的上视图。 
图6B绘示电极复合层60、65的剖面图。 
图7绘示一结构在沉积后，例如是溅射，一锗锑碲的顺应性层170或其它可程序化阻抗材料涂布于电极复合层60、65。 
图8A绘示蚀刻侧壁的平面图。 
图8B绘示侧壁171及172的剖面图。 
图9绘示电介质填充工艺。 
图10绘示氧化膜化学机械研磨工艺应用于平坦化表面，且暴露出锗锑碲侧壁171及172的顶端181及182。 
图11绘示光致抗蚀剂图案修整用以形成次光刻光掩模以修减侧壁171及172。 
图12A绘示侧壁存储单元宽度蚀刻的平面图。 
图12B绘示蚀刻移除暴露的锗锑碲留下一狭窄的侧壁接脚124于电极复合层的剖面图。 
图13绘示工艺的下一步骤的平面图。 
图14绘示填充小接缝及氧化沉积的步骤。 
图15绘示为位线的导孔成形及金属化且位线接触存储单元。 
图16绘示在锗锑碲层侧壁蚀刻的沉积后一电极复合层的剖面图。 
图17为绘示用以形成掺杂区域115、116、117的工作区300的展开图。 
图18绘示用以界定一电极复合层的矩形306。 
图19为绘示用以形成光致抗蚀剂掩模(或硬掩模)的光刻掩模的展开图。 
图20为绘示用以定义配置插塞的导孔位置的光掩模的展开图。 
图21绘示一具有二电极复合层310、311的位置及出现于上左边的成对存储单元中的侧壁有源接脚312、313的8个存储单元阵列结构。 
简单符号说明 
5、201：接脚 
6：第一电极 
7：第二电极 
8、151、160、165、180、195：电介层 
9：电介质 
10、35、36、100、101、102、103：侧壁有源接脚存储单元 
23、24、62：字线 
32、33、150：下电极 
34、37、152、202：上电极 
28、305：共源线 
41、42、64：位线 
50、51、52、53：通道晶体管 
55：存储器阵列 
56：列译码器 
58、67：总线 
59：感应放大器/数据输入结构 
63：行译码器 
68：偏压配置电源电压 
69：偏压配置状态机 
71：数据输入线 
72：数据输出线 
74：其它电路系统 
75：集成电路 
99：结构 
110：半导体基板 
111、112：电介沟槽 
116：共源区域 
115、117：漏极区域 
113、114：多晶硅字线 
118、127：电介填充层 
141、120、196、197、303、304、324、325、326、327、328、329、330、331：接点插塞结构 
119：共源线 
121：薄膜下电极 
122：薄膜电介层 
123、123A：薄膜上电极 
124、124A、312、313：侧壁接脚 
125：薄氧化层 
126：钨插塞 
129、130、131、132：接点 
153：保护上电介层 
155：第一矩形 
156：第二矩形 
60、65、310、311：电极复合层 
61、66、171、172：垂直侧壁 
170：顺应性层 
173：表面 
181、182：顶端 
185、186：矩形延展部 
187、188：光掩模 
W1、W2：宽度 
190：接缝 
193、194：隔热填充物 
198：图案化金属层 
203：残留层 
210：狭窄区域 
301、302、335、336、337、338：多晶硅线 
300、320、321、322、323：工作区 
306：矩形 
307：光刻掩模 
308：导孔图案 
316：边缘 
339、340：金属线 
具体实施方式
以下的详细说明皆佐以图示以供参考。并且本实例所揭露的内容用以支持本发明，并不会对本发明的范围进行限缩，且本发明的欲保护范围以权利要求所界定。具有通常知识者可依本实施例的说明做适当变化。 
请参照图1，其绘示一侧壁有源接脚存储单元10的透视图。此存储单元包括一狭窄的侧壁间隙壁。请参照在电极复合层的侧壁上的接脚5。此电极复合层包括一第一薄膜电极6及一电极间电介层8(inter-electrode dielectric layer)所隔开的一第二薄膜电极7。在本实施例中一电介质9覆盖于此一电极复合层上。接脚5包括了一可程序化阻抗材料比如是一相变化材料。接脚5具有一工作区(active region，亦称活性区或有源区)，相变化材料形成于此工作区中。此工作区具有在一第一电极6及一第二电极7之间的长度L，且L的长度取决于一电介层8的厚度。接脚5的工作区则具有一厚度T，而T的厚度取决于形成在电极复合层的侧壁上薄膜的厚度。电极复合层经由一光刻工艺或其它形式的光刻工艺形成，所以其宽度约与光刻工艺中的最小特征尺寸(minimum feature size)相等。至于进阶的光刻工艺，电极复合层的宽度W大约是90纳米。接脚5的工作区具有一宽度，该宽度小于电极复合层光刻工艺界定的最小特征尺寸。在本实例中，接脚5的工作区宽度大约为40纳米或小于40纳米。 
如上所述，接脚5的工作区的长度L取决于电介层8的薄膜厚度，在本实施例中此厚度的范围大约在20纳米至50纳米之间。同样地，接脚5的工作区的厚度T取决于形成侧壁接脚的材料的薄膜厚度。在本实施例中此厚度的范围在大约在10纳米至50纳米间。因此接脚5的三维尺寸在本发明的实施例中皆小于50纳米，且优选地为约40纳米或小于40纳米。 
在本实施例中，可程序化阻抗材料包括一相变化材料，比如是Ge2Sb2Te5或其它以下提到的材料。在接脚5之内的材料容积非常小，其中相变化在图1所示的结构中被感应。因本实施例中的接脚5工作区的长度L、宽度W及厚度T皆小于40纳米，所以工作区的体积小于64x 10-24m3。因此，改变相变化的重置电流的量很小。 
本实施例中，存储单元的侧壁接脚5包括以相变化为依据的存储器材料，此材料包括以硫属化合物为根据的材料或其它材料。硫族元素(chalcogens)包括下列四种元素其中之一，氧(O)、硫(S)、硒(Se)、碲(Te)在周期 表中形成了部分的第6A族元素。硫属化合物包括了具有带正电或自由基的硫族元素。硫属化合物合金包括硫属化合物与其它材料例如是过渡金属的组合。硫属化合物合金在周期表第6A栏的元素中通常包括一个或多个元素，例如为锗(Ge)和锡(Sn)。硫属化合物合金的组合包括一个或多个的锑(Sb)，镓(Ga)，铟(In)和银(Ag)。很多相变化存储器材料在科技文献中被揭露，包括的金合有：Ga/Sb，In/Sb，In/Se，Sb/Te，Ge/Te，Ge/Sb/Te，In/Sb/Te，Ga/Se/Te，Sn/Sb/Te，In/Sb/Ge，Ag/In/Sb/Te，Ge/Sn/Sb/Te，Ge/Sb/Se/Te以及Te/Ge/Sb/S。在Ge/Sb/Te的家族合金中，有相当广泛范围的合金化合物可供应用。此化合物可以TeaGebSb100-(a+b)表示，其中a及b代表组成元素的原子的100％中原子的百分比。有研究者曾指出，最有用的合金当中的锡平均浓度在沉积物中优选地低于70％，通常低于60％。且一般范围从最低约23％的锡至约50％的锡，而最佳约为48％至58％的锡。锗(Ge)的浓度大约在5％以上，而在沉积物中其范围平均约从8％至30％，通常维持在低于50％。锗的浓度范围最佳的约为8％至40％。在此化合物中主要组成元素的残留为锑(Sb)(Ovshinsky美国专利第5,687,112号，10-11栏)。另一位研究者指出其它适用的特殊合金，包括Ge2Sb2Te5、GeSb2Te4及GeSb4Te7.(Noboru Yamada，“Potential of Ge-Sb-Te Phase-Change Optical Disks for High-Data-Rate Recording”，SPIE v.3109，pp.28-37(1997))。一般来说，过渡金属例如是铬(Cr)，铁(Fe)，镍(Ni)，铌(Nb)，钯(Pd)，铂(Pt)和混合物及其合金可与锗/锑/碲(Ge/Sb/Te)结合以形成具有可程序化阻抗特性的相变化合金。可用的存储器材料在Ovshinsky美国专利第5,687,112号，11-13栏中有详细说明，此些实例于此一同并入参考。 
相变化材料可在第一结构状态(first structural state)与第二结构状态(second structural state)之间转换。其中在第一结构状态中相变化材料为非晶相，而在第二结构状态中为结晶相且此结晶相在存储单元的有源通道区域中维持原本的排列。此些相变化材料至少为双定态的材料。非晶态指的是一较无组织的结构，相较于一单晶体更无组织，而非晶态所具有的特性例如是相对于非晶态有较高的电阻率。而结晶态指的是较有组织的结构，相较于一非晶态更有组织。而结晶态所具有的特性例如是相对于非晶态有较低的电阻率。相变化材料可在区域排列(local order)内电性转换不同两种状态，区域排列在光谱中横跨完全非晶态及完全结晶态。而其它材料的特性会被结晶 态与非晶态之间的变化影响，包括了原子的排列，自由电子密度及启动能。此相变化材料可在不同固相、两固相的混合或更固态的固相间转换，在完全非晶态与完全结晶态之间提供一灰色阶段(gray scale)。在相变化材料间的电性特质可对应地调整变更。 
相变化材料可应用电流脉波使其从一相位改变至另一相位。一较短较高的振幅脉波会使得相变化材料改变至一般的非晶相，而一较长较低的振幅脉波则会使得相变化材料改变至一般的结晶相。较短较高的振幅脉波的能量高得足以使结晶结构键结破裂，而短得足以防止原子重新结合至一结晶态。适当的脉波图表可由经验决定，并不须过度的实验，特别是一特定的相变化合金。 
以下所揭露的内容，其中相变化材料指称为锗锑碲(GST)，而其它型式的相变化材料同样可使用。而于此揭露的Ge2Sb2Te5为一适当材料以形成存储单元。 
具有效用的可程序化阻抗材料的特性，像是相变化材料包括一材料具有可程序化的阻抗且可逆的特性，比如具有经由电流感应即互相可逆的至少二固相。此至少二固相包括了一非晶相及一结晶相。然而，在操作中，可程序化阻材料无法完全转化为非晶相或结晶相其中之一。中间相位或二相位的混合在材料特性上有显着的不同。此二固相应为双定态且具有不同的电性特性。可程序化阻抗材料可为硫属化合物材料，硫属化合物材料包括锗锑碲，或者可程序化阻抗材料可为以上所述其它相变化材料之一。 
请参照图2，其绘示一存储阵列的示意图。如图2所示，共源线28(common source line)、字线23(word line)及字线24大致上平行排列于Y方向。位线41(bit line)及42大致上平行排列于X方向。因此，Y译码器及在方块45中的字线驱动器耦接至字线23及24。X译码器及在方块46中的一组感应放大器耦接至位线41及42。共源线28耦接至通道晶体管50、51、52及53的源极。通道晶体管50的栅极耦接至字线23。通道晶体管51的栅极耦接至字线24。而通道晶体管52的栅极耦接至字线23。通道晶体管53的栅极耦接至字线24。因具有上电极元件34的侧壁有源接脚存储单元35，通道晶体管50的漏极耦接至下电极32。此上电极元件34耦接至位线41。同样地，因具有上电极37的侧壁有源接脚存储单元36，通道晶体管51的漏极耦接至下电极33。上电极元件37耦接至字线41。通道晶体管52及53 同样地耦接至于字线42上，相对应的侧壁接脚存储单元。共源线28上有二列的存储单元，在示意图中其排列方向为Y方向。在其它的实施例中，通道晶体管可由其它可在阵列中控制电流以在阵列中选取装置以读写数据的结构取代。 
请参照图3，其绘示依照本发明优选实施例的集成电路的简化方块图。集成电路75包括一存储器阵列55，在一半导体基板上，侧壁有源接脚相变化存储单元用以提供此存储器阵列55。列译码器56与多个字线62耦接，且沿着存储器阵列的列排列。行译码器63与沿着存储器阵列55的行排列的多个位线64耦接，且此些位线64用以在存储器阵列55中的侧壁接脚有源存储单元里读写数据。地址的提供从总线58至行译码器63及列译码器56，方块59中的感应放大器及数据输入结构经由数据总线67耦接至行译码器63。数据从集成电路75的输出/输入端口经由数据输入线71流入，或者从其它数据源经内部或外部至集成电路75及至方块59中的数据输入结构。在以图佐证的本实施例中，其它电路系统包括在集成电路中，且集成电路例如是一般用途处理器(general purpose processor)或是特殊用途应用电路系统(special purpose application circuitry)，或者是具有由薄膜熔丝的相变化存储单元阵列所支持的单芯片系统设计功能的模块组合。数据从方块59中的感应放大器至输入/输出端口经由数据输出线72后流出，或是从感应放大器至其它数据目的由内部或外部至集成电路75。 
本实施例所提供的控制器为使用偏压配置状态机69控制偏压配置电源电压68的应用，例如为读、写、清除、清除验证及写入验证电流。此控制器可使用现有特殊用途逻辑电路系统。在另一实施例中，此控制器包括了一般用途处理器。此用途处理器可于相同集成电路上提供，且此集成电路用以执行一计算机程序以控制设备的运作。 
请参照图4，其绘示多个侧壁有源接脚相变化随机存取存储单元100-103的剖面图。存储单元100-103形成于半导体基板110上。隔离结构(isolation structures)例如是浅沟槽隔离(STI)电介沟槽111及112。电介沟槽111及112隔离了数对成列的存储单元通道晶体管。此通道晶体管由基板110上的共源区域116及漏极区域115及117所形成。多晶硅字线113及114形成通道晶体管的栅极。电介填充层118形成于多晶硅字线113及114之上。接点插塞(contact plug)结构141及120个别接触通道晶体管的漏极，且共源线 119沿着阵列中的一列与共源区域接触。共源线119与共源区域116接触。接点插塞结构120与存储单元101的下电极121接触。存储单元101，如存储单元101、102及103，包括一薄膜下电极121，一薄膜电介层122、一薄膜上电极123及一包括锗锑碲或其它相变化材料的侧壁接脚124。一电介填充层127涂布在存储单元100-103上。钨插塞126接触上电极123。一图案化的金属层提供了接点129、130、131、132，以上涂布在电介填充层127上。一般来说，接点129至132为图2所示的为译码电路而延展的单位线。一薄氧化层125涂布在上电极123。此薄氧化层125如下所述用以加工(process)边缘。 
在具代表性的实施例当中，图案化金属层(接点129-132)包括铜金属化工艺。其它的金属化工艺，包括铝及铝合金同样可被利用。上电极及下电极(比如是121、123)包括氮化钛(TiN)或氮化钽(TaN)，具有10至30纳米的厚度。另外，上下电极也可为氮化铝钛(TiAlN)或氮化铝钽(TaAlN)，或为包括一种或多种元素，由钛(Ti)、钨(W)、钼(Mo)、铝(Al)、钽(Ta)、铜(Cu)、(Pt)、铱(Ir)、镧(La)、镍(Ni)、钌(Ru)及氧(O)中任选。而电介层可为氧化硅(silicon Oxide)、氧氮化硅(silicon oxynitride)、氮化硅(silicon nitride)、三氧化二铝(Al2O3)、其它低介电质电介层或一ONO或SONO的多层结构。另外，电介层也可包括一种或多种元素，由硅(Si)、钛(Ti)、铝(Al)、钽(Ta)、氮(N)、氧(O)及碳(C)。而电介层的厚度为10至200纳米且优选的是50纳米或小于50纳米。而第二电极可为氮化钛(TiN)或氮化钽(TaN)。 
请参照图5，其绘示结构99在前段工艺后形成标准的互补金氧半导体(CMOS)元件依照本实施例在图2的阵列中的字线、共源线及通道晶体管。如图5所示，共源线119位于掺杂区域116在半导体基板上方，其中掺杂区域116与在图标左边的第一晶体管的源极及在图示右边的第二通道晶体管相对应。在本实例中，共源线119延展至结构99的上表面。在其它实施例中，共源线并无延展与表面接触。掺杂区域115与第一通道晶体管的漏极相对应。一字线包括多晶硅113及一硅掩模(未绘示于图中)用以作为第一通道晶体管的栅极。插塞120接触掺杂区域115且提供一导通路径至结构99的表面，用以接触如下所述的存储单元电极。第二通道晶体管的漏极由掺杂区域117所提供。一字线包括多晶硅线114及硅化物掩模(未绘示于图中)，用以作 为第二晶体管的栅极。插塞141接触掺杂区域117且提供一导通路径至结构99的上表面，用以接触如下所述的存储单元电极。独立沟槽111及112从相邻的两晶体管结构中将二耦接至插塞120及141的晶体管结构分开。图5中的结构99提供一用以形成存储单元元件的基板，以下为更详细的说明。 
在形成结构99中的插塞120、141及源线119后，再形成一多层薄膜结构包括下电极150、上电极152、电介层151及保护上电介层153。下电极150具有小于50纳米的厚度，且优选在范围10至30纳米。上电极152也具有小于50纳米的厚度，且优选在范围10至30纳米，且上下电极可为不同的厚度。举例来说，上电极152的厚度可稍微大于下电极150的厚度，使用钨插塞技术或其它相似技术，为了增进加工边缘以达到信赖接触。上电介质153提供加工边缘予机械化学研磨使用以平坦化，修整侧壁间隙壁蚀刻。其它实施例省去上电介质153。 
请参照图6A及图6B。图6A绘示光掩模(mask)图案的上视图，其中包括用以蚀刻图5的多层薄膜结构的第一矩形155及第二矩形156，以形成电极复合层60、65。图6B绘示电极复合层60、65的剖面图。电极复合层60包括下电极121、电介层122及上电极123。电极复合层60具有一侧壁61。同样地，电极复合层65具有侧壁66。反应性离子蚀刻(Reactive ion etching，REI)用以尽可能形成垂直侧壁61、66。虽未绘示于图中，反应性离子蚀刻可能过度蚀刻至电介填充层118。在一般的工艺中，其过度蚀刻约为20纳米。此工艺使用基本配方(recipe)三氯化硼(BCl3)及/或氯气(Cl2)。 
请参照图7，其绘示一结构在沉积后，例如是溅射，一锗锑碲的顺应性层170或其它可程序化阻抗材料涂布于电极复合层60、65。锗锑碲可在摄氏250度的温度下使用未瞄准的溅射以沉积。当使用Ge2Sb2Te5为相变化材料时，此结果使薄膜在电极复合层上具有大约60至80纳米的厚度，而侧壁大约为20至30纳米的厚度，以及在电极复合层间的厚度约60至80纳米。工艺中的许多实施例可在平坦表面上溅射整个芯片至40到100纳米。 
请参照图8A，其绘示蚀刻侧壁的平面图。此蚀刻通过蚀刻工艺将锗锑碲层从平坦表面上移除，且分别留下侧壁171、172在电极复合层60及65上，且完全包围电极复合层60及65。各向异性的配方三氯化硼(BCl3)及/或氯气(Cl2)的反应性离子蚀刻工艺可被使用。图8B绘示侧壁171及172的剖面图。因为轻微的过度蚀刻，二侧壁的顶端微低于电介层160的顶端， 其为确保侧壁171及172完全脱离结构99的表面173。 
请参照图9，其绘示电介质填充工艺。此工艺包括一低温线性氧化物，一氮化硅层或一氧化硅层(未绘示于图中)，且在具有相变化材料的侧壁上，约使用小于摄氏200度的工艺温度。其它适合的工艺应用使用等离子体辅助化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)的二氧化硅。在形成线性氧化物后，电介层180的填充使用高温工艺例如是二氧化硅或其它相似材料的高密度等离子体化学气相沉积(HDP-CVD)。 
请参照图10，其绘示氧化膜化学机械研磨(chemical mechanical polishing，CMP)工艺应用于平坦化表面，且暴露出锗锑碲侧壁171及172的顶端181及182。在电极复合层上的电介层用以确保进行化学机械研磨时不会触碰上方的电极材料，例如是氮化钛(TiN)，且使上方电极材料免去反应性离子蚀刻工艺及其它蚀刻步骤。 
请参照图11，其绘示光致抗蚀剂图案缩减(photoresist pattern trimming)用以形成次光刻光掩模以缩减侧壁171及172。光致抗蚀剂图案的形成是利用光刻技术。此技术包括了将图案由一光掩模或一组光掩模转移至光致抗蚀剂层。此光致抗蚀剂层包括了在电极复合层60及65上的矩形延展部185及186，如虚线外框所示。在光致抗蚀剂形成后，延展部185及186的宽度接近最小特征尺寸，使得光刻工艺形成延展部185及186。接着，延展部185及186的宽度W1通过光致抗蚀剂缩减减少至次光刻工艺的宽度W2且留下一狭窄修减后的光掩模187及188。例如，含氧等离子体(oxide plasma)用以各向异性蚀刻光致抗蚀剂以修整图案化光致抗蚀剂的宽度及厚度，直到本实施中的宽度W2小于50纳米，且直到在0.2微米(200纳米)最小特征尺寸的光刻工艺环境中的宽度W2约为40纳米。 
在其它实施例中，一硬掩模层(未绘示于图中)例如是氮化硅(SiN)或二氧化硅(SiO2)的低温沉积层，可设置于光致抗蚀剂图案及电极复合层60、65的表面之间，以预防蚀刻损坏存储单元。假如光致抗蚀剂或者锗锑碲的选择性蚀刻在缩减工艺后的厚度不够，则硬掩模通过硬掩模改善。 
请参照图12A，其绘示侧壁存储单元宽度蚀刻的平面图依照缩减后的光掩模187及188，使用一以氯为基础的反应离子蚀刻因此电介层180未被蚀刻。蚀刻移除了暴露的锗锑碲，留下了一狭窄的侧壁接脚124在电极复合层上，如图12B的剖面图所示。一接缝190包围在电介层180上的电极复合层 60及65。此电介层180优选地延展至完全移除锗锑碲的结构99的上表面173。在此工艺的实施例中，所有在接缝190中的锗锑碲皆必须移除。接缝190中锗锑碲的显着部分已被移除，因此在上下电极中的电流可集中在一电极复合层的电介层的狭窄接脚上。 
请参照图13，其绘示工艺的下一步骤的平面图。其中包括了移除光掩模(trimmed photoresist mask)187、188及硬掩模层(假如有)。于本实施例的工艺中，在电极复合层60及65上的侧壁接脚124及124A具有约为40纳米或小于40纳米的次光刻宽度W。 
请参照图14，其绘示填充小接缝及氧化沉积的步骤。因移除侧壁而留下的接缝190(图13)可使用原子层沉积以填充电性及/或隔热填充物193及194。在本实施例中，原子层沉积用以沉积电介材料例如是二氧化铝(AlO2)或二氧化铪(HfO2)及其它类似的材料。在其它实施例中，接缝可在玻璃或低介电值的材料上使用无机旋转而通过氧化硅的旋涂法填充。另一种方法，接缝被密封形成一大致上排他的空间，为存储单元提供优选的隔热。接下来，一上氧化沉积层覆盖电极复合层具有一电介层195。此电介层195被平坦化用以预备随后的金属化法。上氧化沉积层优选地由离子体辅助化学气相沉积(PECVD)所形成或其它低温工艺。 
请参照图15，其绘示为位线的导孔成形及金属化且位线接触存储单元。在电介层195蚀刻导孔且填充钨或其它导通材料以形成插塞196及197，且与在电极复合层60及65的上电极123及123A导通。一图案化金属层198提供位线在平面图上延以译码电路。如上所述，插塞120及141在电极复合层60及65的下电极与通道晶体管的漏极115及117之间提供连接。字线113、114由多晶硅栅极在通道晶体管上所形成。而共源区域116及共源线119用以感应电流从位线经由存储单元至通道晶体管且至共源线。 
请参照图16，其绘示在锗锑碲层侧壁蚀刻的沉积后一电极复合层的剖面图。例如为电极复合层60，在其它实施例中，锗锑碲层仅在复合电极层的四周部分蚀刻，留下残留层203在电极复合层的周围的接缝(190，请参照图12B)底部。在图16中，接脚201具有次光刻宽度，且此接脚接触延伸至电介层的上电极202，因此电流集中在相变化材料接脚的狭窄区域210。 
图17至图21为绘示上述工艺中所使用的光掩模的展开图。图17为绘示用以形成掺杂区域115、116、117的工作区300的展开图。在本实施例中， 工作区的宽度大约为0.4微米。另外，用以形成字线113、114(如图4所示)的多晶硅线301、302也在图中。多晶硅线301、302与工作区交错且通常在掺杂区域前形成。在本实例中，多晶硅线301、302的宽度大约是0.18微米。在此例中，通道晶体管具有一晶体管宽度约0.4微米且一晶体管长度约为0.18微米。同样在图17中绘示钨共源线305的展开图且在303与304与插塞接触，用以形成共源线119及图4的插塞120、141。在本实施例中，共源线305大约为0.2微米宽，且钨插塞大约为0.2微米平方。在本实施例中，钨插塞303、304被配置在离工作区300的边缘约0.1微米，离多晶硅线301、302的一侧约0.16微米。 
请参照图18，其绘示用以界定一电极复合层的矩形306，例如是用以形成图4中的存储单元101的复合层。在本实施例中，矩形约为0.4微米宽，且约为0.55微米长。受制于光掩模校准变异(subject to mask alignment)，矩形306的边缘316从钨插塞303的边缘至多晶硅线301大约为0.25微米。同样的，矩形306的边缘316从共源线305的边缘至多晶硅线301大约为0.25微米。 
图19为绘示用以形成光致抗蚀剂掩模(或硬掩模)的光刻掩模的展开图。因光刻工艺具有0.2微米最小特征尺寸，光刻掩模307具有约0.2微米的宽度。如图19所示，在图案形成后，光刻掩模307如上所述被缩减以定义出一侧壁工作区的宽度。在本实施例中，此光掩模延展至电极复合层的边缘在0.15微米的范围内。受制于光掩模校准变异，此电极复合层由矩形306所定义，且配置靠近于矩形306的中心。 
图20为绘示用以定义配置插塞的导孔位置的光掩模的展开图，例如为图4中的插塞126，用以使上电极与金属化位线接触。在本实施例中，导孔图案308约为0.28微米平方，且离覆盖多晶硅线301的矩形306的边缘316，以及离定义电极复合层的边缘约0.06微米。 
图21绘示一具有二电极复合层310、311的位置及出现于上左边的成对存储单元中的侧壁有源接脚312、313的8个存储单元阵列结构。工作区320、321、322、323绘示于图中。存储单元电极复合层310、311配置于第一工作区的接点插塞324、325上；存储单元电极复合层(未绘示于图中)配置于第二工作区321的插塞326、327上；存储单元电极复合层(未绘示于图中)配置于第三工作区322的插塞328、329上；存储单元电极复合层(未绘示 于图中)配置于第四工作区323的插塞330、331上。多晶硅字线335、336沿着个别存储单元的列配置于工作区320及322上。同样地，多晶硅字线337、338沿着个别存储单元的列配置于工作区321及323上。金属线339在覆盖工作区320及322的多晶硅字线335及336之间延展，也就是在耦接至多晶硅线字线335、336的二列存储单元之间延展。相同地，金属线340在覆盖工作区321及323的多晶硅字线337及338之间延展，也就是在耦接至多晶硅线字线337、338的二列存储单元之间延展。在展开图中，工作区320、321之间分开约0.26微米。同样地，工作区320及322也是分开约0.26微米。 
以上佐以图17至图21为参考的尺寸，为具有最小特征尺寸约0.2微米的光刻工艺的典型代表，且用以提供存储单元的生产过程可依照实际情况做适当变化。 
综上所述，虽然本发明以优选实施例揭露如上，然而其并非用以限定本发明，本领域的技术人员在不脱离本发明的精神和范围内，可作些许的更动与润饰，因此本发明的保护范围应当以后附的权利要求所界定者为准。 

Claims (21)

1.一种形成一存储单元的方法，包括：
形成一第一电极，一绝缘层配置于该第一电极之上，及一第二电极配置于该绝缘层之上，且该绝缘层具有一侧壁；
在一侧壁上形成一间隙壁，该间隙壁包括一可程序化阻抗材料，该可程序化阻抗材料与该第一电极及该第二电极电连接，该间隙壁具有一长度、一宽度及一厚度，该长度沿着该侧壁从该第一电极延展至该第二电极，该宽度与该长度垂直，而该厚度取决于该可程序化阻抗材料形成在该侧壁的薄膜厚度，且其中形成该间隙壁包括：
沉积一可程序化阻抗材料层于该侧壁上；
各向异性蚀刻可程序化阻抗材料层以移除除该侧壁外的部分区域的可程序化阻抗材料；及
依据一图案选择性地蚀刻可程序化阻抗材料以界定该间隙壁的该宽度，该宽度小于40纳米；
其中该选择性地蚀刻包括形成一蚀刻光掩模，该蚀刻光掩模具有一光刻图案以定义一光刻宽度，以及修减或各向异性地蚀刻该蚀刻光掩模，以提供一修减后光掩模以定义该图案，该图案用以定义该宽度。
2.如权利要求1所述的方法，其中该各向异性蚀刻包括使用一等离子体蚀刻工艺。
3.如权利要求1所述的方法，其中该各向异性蚀刻包括使用一反应性离子蚀刻工艺。
4.如权利要求1所述的方法，其中该绝缘层在该第一电极及该第二电极间具有一厚度，且其中该间隙壁、该第一电极及该第二电极具有个别的厚度，且该些厚度小于40纳米。
5.如权利要求1所述的方法，其中该可程序化阻抗材料包括一硫属化合物。
6.如权利要求1所述的方法，其中该可程序化阻抗材料具有至少二固相，且该二固相通过感应一电流而可逆。
7.如权利要求1所述的方法，其中该可程序化阻抗材料具有至少二固相，该二固相包括一非晶相及一结晶相。
8.如权利要求1所述的方法，其中该可程序化阻抗材料包括Ge2Sb2Te5。
9.如权利要求1所述的方法，其中该可程序化阻抗材料包括一种或多种材料选自锗、锑、碲、硒、铟、钛、镓、铋、锡、铜、钯、铅、银、硫或是金。
10.一种形成一间隙壁存储单元的方法，包括：
形成一第一电极，一绝缘层配置于一第一电极之上，及一第二电极配置于该绝缘层之上，且该绝缘层具有一使用光刻工艺的侧壁；以及
在一侧壁上形成一间隙壁，该间隙壁包括一可程序化阻抗材料，该可程序化阻抗材料与该第一电极及该第二电极电连接，该间隙壁具有一长度、一宽度及一厚度，该长度沿着该侧壁从该第一电极延展至该第二电极，该宽度与该长度垂直，而该厚度取决于该可程序化阻抗材料形成在该侧壁的薄膜厚度，且其中形成该间隙壁包括：
沉积一可程序化阻抗材料层于该侧壁上；
各向异性蚀刻可程序化阻抗材料层以移除除该侧壁以外的部分区域的可程序化阻抗材料；及
依据一图案选择性地蚀刻可程序化阻抗材料，此可程序化阻抗材料具有一尺寸小于一光刻工艺中的0.2微米最小特征尺寸，以定义该间隙壁的宽度且该宽度小于该0.2微米最小特征尺寸，
其中该选择性地蚀刻包括形成一蚀刻光掩模，该蚀刻光掩模具有一光刻图案以定义一光刻宽度，以及修减或各向异性地蚀刻该蚀刻光掩模，以提供一修减后光掩模以定义该图案，该图案用以定义该宽度。
11.如权利要求10所述的方法，其中该可程序化阻抗材料包括一硫属化合物。
12.如权利要求10所述的方法，其中该可程序化阻抗材料具有至少二固相，且该二固相通过感应一电流而可逆。
13.如权利要求10所述的方法，其中该可程序化阻抗材料具有至少二固相，该二固相包括一非晶相及一结晶相。
14.如权利要求10所述的方法，其中该可程序化阻抗材料包括Ge2Sb2Te5。
15.如权利要求10所述的方法，其中该可程序化阻抗材料包括一种或多种材料选自锗、锑、碲、硒、铟、钛、镓、铋、锡、铜、钯、铅、银、硫或是金。
16.一种集成电路，包括：
一半导体基板；
多个通道晶体管形成的一阵列，该阵列具有多个电极，该电极于该半导体基板上包括多个掺杂区域用以与该些通道晶体管的各个漏极连接至一参考电势；
多条字线沿着通道晶体管阵列中相对应的列耦接至该些通道晶体管的栅极；
多个可程序化存储单元的一阵列，该些可程序化存储单元在该阵列中分别包括一下电极，一绝缘层配置在该下电极上，该绝缘层具有一侧壁，一上电极配置于该绝缘层上，及一可程序化阻抗材料间隙壁沿着该绝缘层的侧壁且与该上电极及该下电极电连接，该间隙壁具有一长度、一宽度及一厚度，该长度在该绝缘层沿着该侧壁从该下电极延展至该上电极，该宽度与该长度垂直，且其中该宽度及该厚度小于40纳米；
多条位线配置在该些存储单元之上，且该些位线分别沿着该些可程序化存储单元的一阵列中的多个存储单元的多个栏排列；
多个接点插塞结构，该些接点插塞结构连接各个存储单元的下电极与该通道晶体管阵列中相对的通道晶体管的漏极；以及
一图案化金属层，提供多个接点，涂布在一电介填充层上，该电介填充层涂布在该些存储单元上，该些接点与在该些位线中的具有相对应该些位线的各该些存储单元的该些上电极接触。
17.如权利要求16所述的集成电路，其中，该间隙壁包括一可程序化阻抗材料，该可程序化阻抗材料具有至少二固相，且该二固相通过感应一电流而可逆。
18.如权利要求17所述的集成电路，其中该至少二固相包括一非晶相及一结晶相。
19.如权利要求17所述的集成电路，其中该间隙壁、该下电极及该上电极具有不同的厚度，该些厚度小于用以形成该集成电路的光刻工艺的0.2微米最小特征尺寸。
20.如权利要求16所述的集成电路，其中该可程序化阻抗材料包括Ge2Sb2Te5。
21.如权利要求16所述的集成电路，其中该可程序化阻抗材料包括一种或多种材料选自锗、锑、碲、硒、铟、钛、镓、铋、锡、铜、钯、铅、银、硫或是金。
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