CN1848454A - 鳍片场效应晶体管及制造鳍片场效应晶体管的方法 - Google Patents

鳍片场效应晶体管及制造鳍片场效应晶体管的方法 Download PDF

Info

Publication number
CN1848454A
CN1848454A CN200610007485.2A CN200610007485A CN1848454A CN 1848454 A CN1848454 A CN 1848454A CN 200610007485 A CN200610007485 A CN 200610007485A CN 1848454 A CN1848454 A CN 1848454A
Authority
CN
China
Prior art keywords
stress
finfet
raceway groove
grid
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200610007485.2A
Other languages
English (en)
Other versions
CN100452432C (zh
Inventor
朱慧珑
B·B·多里斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1848454A publication Critical patent/CN1848454A/zh
Application granted granted Critical
Publication of CN100452432C publication Critical patent/CN100452432C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

用应力材料替代FINFET的栅极的一部分以给FINFET的沟道施加应力以提高电子和空穴迁移率并提高性能。FINFET具有SiGe/Si叠层栅极，并且在栅极的SiGe部分硅化之前有选择地蚀刻以形成栅极间隙，所述栅极间隙使栅极足够薄以便完全硅化。在硅化后，用应力氮化物膜填充栅极间隙以在沟道中产生应力并提高FINFET的性能。

Description

鳍片场效应晶体管及制造鳍片场效应晶体管的方法
技术领域
本发明主要涉及具有很薄垂直硅层(鳍片)用于沟道的应变双栅极金属氧化物半导体场效应晶体管(MOSFET)的结构，称为FINFET，以及制造应变FINFET的方法，该方法用应力材料替代FINFET的栅极的一部分以向FINFET的沟道提供应力。该应力提高电子和空穴迁移率并提高FINFET的性能。更具体地说，用应力氮化物膜替代FINFET的SiGe/Si叠层栅极的SiGe部分以向FINFET的沟道提供应力。
背景技术
在过去的大约25年，超大规模集成(VLSI)的主要挑战是具有高产量和可靠性的金属氧化物半导体场效应晶体管(MOSFET)的集成数目的不断提高。这在现有技术中主要通过降低MOSFET沟道长度而没有过多短沟道效应获得。如本领域的技术人员公知的，短沟道效应是因为在栅极和源极/漏极扩散区域之间共享的二维静电电荷引起短沟道器件中阈值电压Vt的降低效应。
为了降低MOSFET沟道长度而没有过多短沟道效应，在提高沟道掺杂浓度时必须减小栅极氧化物的厚度。然而，Yan等人的“Scaling the SiMOSFET：From bulk to SOI to bulk”，IEEE Trans.Elect.Dev.，Vol.39，p.1704，July 1992，示出为了减小亚0.05μm MOSFET的短沟道效应，重要的是在结构中存在背部传导层以从沟道屏蔽漏极场。Yan等人的结果示出双栅极MOSFET和具有顶部栅极和背部接地平面的MOSFET对短沟道效应有更高的免疫力并且因此可以比常规MOSFET降低到更短的尺寸。
现有双栅极MOSFET的典型结构包括很薄垂直硅层(鳍片)用于沟道，具有两个栅极，在沟道的每一侧各有一个。这里使用术语“鳍片(Fin)”表示用作FET的主体的半导体材料。这两个栅极是电连接的以便用于调制沟道。在这样的结构中短沟道效应被极大地抑制，因为两个栅极很有效地终止漏极场线，抑制在沟道的源极末端感应到漏极电势。从而，伴随漏极电压和现有双栅极MOSFET的栅极长度的阈值电压的改变显著小于相同沟道长度的常规单栅极结构。
对于FinFET CMOS(互补金属氧化物半导体)的应用，有益的是尽可能为器件主体提供具有最薄单晶硅Fin的结构。然而，这使得源极和漏极区域的接触非常困难。为了促进硅化物的生长和金属接触的配置，优选地，Fin的器件部分非常薄，而源极和漏极区域较厚。
现有技术已知，应力可以提高FINFET沟道中的电子和空穴的迁移率，但是在FINFET沟道中提供大的应力很困难。沿沟道的压缩纵向应力增加p-型场效应晶体管(pFET)中的驱动电流并减小n-型场效应晶体管(nFET)中的驱动电流。如果拉伸强度在1.0Gpa或更小的量级，沿沟道的拉伸纵向应力增加nFET中的驱动电流并减小pFET中的驱动电流。
发明内容
本发明提供了应变FINFET的结构和制造应变FINFET的方法，该方法用应力材料替代栅极的一部分以给FINFET的沟道施加应力以提高电子和空穴迁移率并提高FINFET的性能。该FINFET具有SiGe/Si叠层栅极并且在栅极的SiGe部分硅化之前有选择地蚀刻以形成栅极间隙，所述栅极间隙使栅极足够薄以便完全硅化。在硅化后，用应力氮化物膜填充栅极间隙。这在沟道中产生应力并提高FINFET的性能。
附图说明
通过随后本发明的几个实施例的详细描述并参考附图，本领域的技术人员将更容易理解用于制造应变FINFET的结构和方法的本发明的前述目的和优点，其中在所有几个视图中相似的元素用同样的标号表示，其中：
图1示出了在掩埋氧化物(BOX)上的绝缘体上硅(SOI)。
图2示出了制造Si鳍片的常规步骤。
图3示出了在BOX上形成的Si鳍片。
图4示出了热氧化以在Si鳍片的侧壁上形成栅极氧化物。
图5示出了沉积多晶-Si层并随后沉积多晶-SiGe层。
图6和6A示出了构图光致抗蚀剂(PR)用于栅极反应离子蚀刻(RIE)，图6中示出顶视图，以及图6A中示出沿图6中箭头A-A的侧面截面图。
图7、7A和7B示出了RIE多晶-SiGe并且RIE多晶-Si以形成栅极，图7中示出顶视图，图7A中示出沿图7中箭头A-A的侧面截面图，以及图7B中示出沿图7中箭头B-B的侧面截面图。
图8是顶视图，示出了热重氧化以形成薄氧化物来保护栅极侧壁和/或用作延伸注入的隔离物。
图9B是沿箭头B-B(如图8中)的侧面截面图，示出了用于延伸形成的倾斜掺杂剂注入。
图10、10A、10B、10C和10D示出了沉积氮化物并RIE氮化物以在栅极侧壁上形成氮化物隔离物，图10中示出顶视图，图10A中示出沿图10中箭头A-A的侧面截面图，图10B中示出沿图10中箭头B-B的侧面截面图，图10C中示出沿图10中箭头C-C的侧面截面图，以及图10D中示出沿图10中箭头D-D的侧面截面图。
图11A和11D示出了SD(源极漏极)注入和退火，图11A中示出沿箭头A-A(如图10中)的侧面截面图，以及图11D中示出沿箭头D-D(如图10中)的侧面截面图。
图12、12A和12C示出了对Si具有选择性地蚀刻多晶-SiGe，图12中示出顶视图，图12A中示出沿图12中箭头A-A的侧面截面图，以及图12C中示出沿图12中箭头C-C的侧面截面图。
图13、13A和13C示出了形成硅化物接触的常规方法，图13中示出顶视图，图13A中示出沿图13中箭头A-A的侧面截面图，以及图13C中示出沿图13中箭头C-C的侧面截面图。
图14、14A和14C示出了沉积应力氮化物膜以填充栅极间隙，图14中示出顶视图，图14A中示出沿图14中箭头A-A的侧面截面图，以及图14C中示出沿图14中箭头C-C的侧面截面图。
图15、15A和15C示出了各向同性回蚀刻应力氮化物膜，图15中示出顶视图，图15A中示出沿图15中箭头A-A的侧面截面图，以及图15C中示出沿图15中箭头C-C的侧面截面图。
具体实施方式
应力可以提高电子和空穴的迁移率，但是在FINFET器件的沟道中提供大的应力很困难。本发明用应力材料替代FINFET的栅极的一部分以向FINFET的沟道提供应力以提高电子和空穴迁移率并且提高FINFET的性能。更具体地说，本发明用应力氮化物膜替代FINFET的SiGe/Si叠层栅极的SiGe部分以向FINFET的沟道提供应力来提高电子和空穴迁移率并且提高FINFET的性能。
通常，本发明使用SiGe/Si叠层栅极替代多晶-Si栅极。在硅化前，选择性蚀刻栅极的SiGe部分以使栅极足够薄以完全硅化。在硅化并蚀刻残余金属后，用应力氮化物膜重填充栅极间隙。这在沟道中产生应力并提高FINFET的性能。其它工艺步骤可以与用于制造常规FINFET的步骤相同。
随后的步骤一般对应图1到15中所示的步骤。
初始，由在BOX(掩埋氧化物)16上的SOI 10(硅12在氧化物绝缘体14上)晶片开始(SOI厚～50-100nm)，如在图1中所示。衬底优选SOI，但不仅限于SOI，还可以包括任意如GaAs，InAs以及其它类似半导体的半导体材料。含硅材料包括但并不仅限于：Si，体Si，单晶Si，多晶Si，SiGe，非晶Si，绝缘体上硅(SOI)，绝缘体上硅锗(SGOI)，绝缘体上应变硅，退火多晶Si和多晶硅线结构。
当衬底10是绝缘体上硅(SOI)或绝缘体上硅锗(SGOI)衬底时，在掩埋绝缘层顶部的含硅层的厚度可以具有10nm或更大的量级。绝缘体或介质可以是氧化物，氮化物或氧氮化物。SOI或SGOI衬底可以使用本领域的技术人员公知的技术形成。例如，SOI或SGOI衬底可以使用热接合工艺或可选地由离子注入工艺形成，这在技术上称为氧离子注入隔离(SIMOX)。
在衬底顶部形成的栅极介质层优选氧化物或氮化物材料，并且通常大于0.8nm厚，并且优选从约1.0nm到约6.0nm厚。栅极介质层还可以由氧氮化物或这样的材料的组合构成。栅极介质层可以使用如化学气相沉积(CVD)，原子层CVD(ALCVD)，脉冲CVD，等离子体辅助CVD，溅射以及化学溶液沉积等常规技术形成，或可选地，栅极介质层可以由热生长工艺形成，该工艺可以包括氧化，氧氮化，氮化和/或等离子体或放射处理。可以用作栅极介质的氧化物的合适例子包括但并不仅限于：SiO2，Al2O3，ZrO2，HfO2，Ta2O3，TiO2，钙钛矿型氧化物及其组合和多层。随后蚀刻栅极介质层以形成栅极介质。
随后是常规步骤制造Si鳍片。沉积硬掩膜氮化物层18(～20-40nm)并构图光致抗蚀剂(PR)20，如图2中所示。反应离子蚀刻(RIE)氮化物18，RIE SOI 10在BOX 16上停止，定时RIE氧化物/BOX以获得～20-40nm的蚀刻深度(以提供更均匀的应力经过Si鳍片，蚀刻入BOX)并移除PR 20，如图3中所示。
该结构利用本领域的技术人员公知的常规工艺形成。例如利用如化学气相沉积(CVD)，等离子体辅助CVD，化学溶液沉积等常规沉积工艺在半导体材料层10顶部形成硬掩膜18。可选地，利用常规的热氧化工艺并随后进行氮化工艺在半导体主体上生长硬掩膜。这两种热处理工艺即氧化和氮化对本领域的技术人员都是公知的。本发明还期望通过沉积形成一种硬掩膜材料层，并通过热氧化/氮化工艺形成另一材料层。
下一步，如在图2A-2B中所示，利用常规的平版印刷和蚀刻构图氮化物层18。具体地，平版印刷工艺包括向氮化物层提供光致抗蚀剂，将光致抗蚀剂层暴露于辐射图形并利用常规抗蚀剂显影液将图形显影在光致抗蚀剂中。在构图光致抗蚀剂后，利用移除氮化物与移除氧化物相比有高选择性的蚀刻工艺移除没有被构图的光致抗蚀剂保护的氮化物层的暴露部分。
可以用于形成构图的氮化物层的合适的蚀刻类型包括但不仅限于：反应离子蚀刻，离子束蚀刻，等离子体蚀刻或激光烧蚀。在此蚀刻步骤后，可以从该结构移除光致抗蚀剂。
随后热氧化Si鳍片22以在Si鳍片的侧壁上形成栅极氧化物24，如图4中所示。在可选的实施例中，通过使用氮化物和氧氮化物可以获得其它形式的侧壁保护。
下一步，沉积多晶-Si层26(～20-30nm)并随后沉积多晶-SiGe层28(～80-100nm)，如图5中所示。多晶-Si 26还可以是这里提到的其它形式的半导体或Si。同样，多晶-SiGe层28还可以是如Ge的其它形式的半导体。在随后的蚀刻步骤中对两种材料进行不同的蚀刻是重要的，如图12中所示。
随后，构图PR 30用于栅极RIE，如图6的顶视图和沿图6中箭头A-A的图6A的侧面截面图所示。下一步RIE多晶-SiGe 28并RIE多晶-Si 26以形成栅极，并移除PR 30，如图7的顶视图，沿图7中箭头A-A的图7A的侧面截面图，和沿图7中箭头B-B的图7B的侧面截面图所示。
随后，热重氧化以形成薄氧化物32来保护栅极侧壁和/或用作延伸注入的隔离物，如图8的顶视图所示。在可选的实施例中，在氮化物和氧氮化物中可利用其它形式的保护。然而，当倒角拐角时优选热重氧化。
下一步，进行倾斜掺杂剂注入34用于延伸形成，如沿箭头B-B(如图8中)的图9B的侧面截面图所示。如果需要，可以进行如图8中晕圈离子/注入(晕圈I/I)箭头指示的晕圈注入。所有的注入步骤与那些常规的FINFET制造步骤相同。
随后，沉积氮化物(30～50nm)并RIE该氮化物以在栅极侧壁上形成氮化物隔离物36，如图10的顶视图，沿图10中箭头A-A的图10A的侧面截面图，沿图10中箭头B-B的图10B的侧面截面图，沿图10中箭头C-C的图10C的侧面截面图，沿图10中箭头D-D的图10D的侧面截面图所示。这些工艺又与用于形成FINFET隔离物的常规步骤相同。
下一步，进行SD(源极漏极)掺杂剂注入38并进行SD退火。SD掺杂剂注入38掺杂SD区域和栅极，并且对于FINFET的完全硅化栅极可以用于调节FINFET器件的阈值电压，如在沿箭头A-A(如图10中)的图11A的侧面截面图，和沿箭头D-D(如图10中)的图11D的侧面截面图所示。执行常规的注入步骤以便在结构中在与鳍片22邻接的区域中形成源极/漏极注入区域。此时掺杂可以是n或p-型。在本发明的一个实施例中，使用如As和B的不同的注入核素掺杂与鳍片22邻接的暴露区域以便分别形成具有施主或受主杂质的源极/漏极区域。
随后，对Si 26具有选择性地干蚀刻(等离子体)多晶-SiGe 28，如在图12的顶视图，沿图12中箭头A-A的图12A的侧面截面图，和沿图12中箭头C-C的图12C的侧面截面图所示，图12C示出了移除栅极的SiGe部分以在多晶-Si上形成间隙40并使栅极足够薄以便完全硅化。在此实例中，蚀刻掉栅极的SiGe部分以形成间隙并且使栅极变薄，这增加了栅极的电阻。最后的硅化工艺降低栅极的电阻到较能接受的水平。
随后，跟随常规方法以制造硅化物接触，如图13的顶视图，沿图13中箭头A-A的图13A的侧面截面图，以及沿图13中箭头C-C的图13C的侧面截面图所示。首先在SD区域中湿蚀刻薄氧化物。随后沉积薄金属膜(优选4-10nm Ni)并且退火(在300-450℃)以形成NiSi 42。随后湿蚀刻残留金属。在硅化工艺期间多晶-Si转变为NiSi 42。
下一步，沉积应力氮化物膜44以填充栅极的间隙，如图14的顶视图，沿图14中箭头A-A的图14A的侧面截面图，以及沿图14中箭头C-C的图14C的侧面截面图所示。优选为nFINFET沉积压缩氮化物膜并为pFINFET沉积拉伸氮化物膜。如技术人员所公知的，可以通过改变等离子体沉积功率选择沉积压缩氮化物膜或拉伸氮化物膜。在本发明中可以使用其它应力材料如钨的金属替代氮化物膜，但是氮化物膜在一致性上有优势。
本发明的应力产生膜可以包括氮化物，优选Si3N4或可选地TiN，氧化物，Al2O3，HfO2，ZrO2，HfSiO，以及在半导体工艺中普通的其它介质材料或其任意组合。应力产生膜具有的厚度范围从约10nm到约100nm。应力产生膜可以在器件沟道中提供压缩应力以提高pFET性能或在器件沟道中提供拉伸应力以提高nFET性能。
随后各向同性回蚀刻应力氮化物膜，如图15的顶视图，沿图15中箭头A-A的图15A的侧面截面图，以及沿图15中箭头C-C的图15C的侧面截面图所示。来自栅极中和SD区域中的应力膜的沟道中的应力可以互相抵消或减小。因为移除了在SD区域中的应力膜，此氮化物回牵步骤提高沟道中的应力。此步骤后，跟随常规工艺以完成器件。
另外的选择是使用另一应力氮化物膜覆盖整个器件以增加沟道应力。此时对nFINFET优选使用拉伸膜并且对pFINFET优选使用压缩膜。
虽然这里从细节上描述了本发明的结构和用于制造应变FINFET的方法的几个实施例和变化，对本领域的技术人员来说明显的是，本发明的公开和教导还暗示许多可选的设计。

Claims (27)

1.一种鳍片场效应晶体管(FINFET)，具有施加到FINFET沟道的应力以提高电子和空穴迁移率以提高性能，包括：
源极，漏极和栅极；
所述栅极包括叠层栅极，其中有选择地蚀刻所述栅极的一部分以形成栅极间隙，所述栅极间隙用应力膜重填充以在所述FINFET沟道中产生应力，以提高电子和空穴迁移率并且提高FINFET的性能。
2.根据权利要求1的FINFET，其中所述栅极包括多晶-SiGe/多晶-Si叠层栅极，并且有选择地蚀刻所述栅极的多晶-SiGe部分以形成栅极间隙，所述栅极间隙用应力膜重填充以在所述FINFET沟道中产生应力。
3.根据权利要求1的FINFET，其中所述栅极间隙用应力氮化物膜重填充以在所述FINFET沟道中产生应力。
4.根据权利要求1的FINFET，其中所述栅极间隙用压缩应力氮化物膜重填充以在pFINFET沟道中产生应力。
5.根据权利要求1的FINFET，其中所述栅极间隙用拉伸应力氮化物膜重填充以在nFINFET沟道中产生应力。
6.根据权利要求1的FINFET，包括另一应力氮化物膜，覆盖所述FINFET以进一步给所述沟道施加应力。
7.根据权利要求1的FINFET，包括另一拉伸应力氮化物膜，覆盖nFINFET以进一步给nFINFET的沟道施加应力。
8.根据权利要求1的FINFET，包括另一压缩应力氮化物膜，覆盖pFINFET以进一步给pFINFET的沟道施加应力。
9.根据权利要求1的FINFET，在集成电路(IC)中，具有所述FINFET作为所述IC的一个元件。
10.一种制造应变鳍片场效应晶体管(FINFET)的方法，所述方法使用应力材料替代栅极的一部分以给FINFET的沟道施加应力，所述方法包括以下步骤：
形成FINFET，具有源极，漏极以及由具有不同蚀刻特性的两种不同类型的半导体材料构成的叠层栅极；
有选择地蚀刻所述叠层栅极的两种不同类型的半导体材料的一种以形成栅极间隙；
用应力膜重填充所述栅极间隙以在FINFET沟道中产生应力，以提高电子和空穴迁移率并且提高FINFET的性能。
11.根据权利要求10的方法，包括形成如多晶-SiGe/多晶-Si叠层栅极的叠层栅极，并且有选择地蚀刻所述栅极的多晶-SiGe部分以形成所述栅极间隙。
12.根据权利要求10的方法，包括用应力氮化物膜重填充所述栅极间隙以在FINFET沟道中产生应力。
13.根据权利要求10的方法，包括用压缩应力氮化物膜重填充所述栅极间隙以在pFINFET沟道中产生应力。
14.根据权利要求10的方法，包括用拉伸应力氮化物膜重填充所述栅极间隙以在nFINFET沟道中产生应力。
15.根据权利要求10的方法，包括用另一应力氮化物膜覆盖所述FINFET以进一步给所述沟道施加应力。
16.根据权利要求10的方法，包括用另一拉伸应力氮化物膜覆盖nFINFET以进一步给nFINFET的沟道施加应力。
17.根据权利要求10的方法，包括用另一压缩应力氮化物膜覆盖pFINFET以进一步给pFINFET的沟道施加应力。
18.一种用于制造应变鳍片场效应晶体管(FINFET)的方法，所述方法使用应力材料替代栅极的一部分以给FINFET的沟道施加应力，所述方法包括以下步骤：
起始于Si鳍片，在所述Si鳍片的侧壁上具有侧壁保护层，在所述Si鳍片上沉积多晶-Si层并随后沉积多晶-SiGe；
构图光致抗蚀剂(PR)用于栅极反应离子蚀刻(RIE)；
RIE多晶-SiGe并且RIE多晶-Si以形成栅极；
对多晶-Si具有选择性地蚀刻多晶-SiGe，其中蚀刻掉所述栅极的所述SiGe部分以在所述栅极中形成间隙；
形成硅化物接触；以及
沉积应力膜以填充所述栅极中的所述间隙。
19.根据权利要求18的方法，其中在RIE步骤之后包括以下步骤：
注入掺杂剂用于延伸形成；
沉积氮化物并RIE所述氮化物以在所述栅极侧壁上形成氮化物隔离物；以及
源极和漏极(S/D)掺杂剂注入并退火。
20.根据权利要求18的方法，其中在RIE步骤之后包括以下步骤：
热重氧化所述栅极侧壁以形成薄氧化物来保护所述栅极侧壁和/或用作延伸注入的隔离物；以及
倾斜掺杂剂注入用于延伸形成。
21.根据权利要求18的方法，其中在所述沉积应力膜的步骤之后，各向同性回蚀刻所述应力膜以移除在源极和漏极区域中的应力膜。
22.根据权利要求18的方法，包括通过湿蚀刻源极和漏极区域中的薄氧化物形成硅化物接触，沉积薄Ni层并退火以形成NiSi。
23.根据权利要求18的方法，包括为pFINFET沉积压缩应力氮化物膜。
24.根据权利要求18的方法，包括为nFINFET沉积拉伸应力氮化物膜。
25.根据权利要求18的方法，包括用另一应力氮化物膜覆盖所述FINFET以进一步给所述沟道施加应力。
26.根据权利要求18的方法，包括用另一拉伸应力氮化物膜覆盖nFINFET以进一步给所述沟道施加应力。
27.根据权利要求18的方法，包括用另一压缩应力氮化物膜覆盖pFINFET以进一步给所述沟道施加应力。
CNB2006100074852A 2005-02-15 2006-02-14 鳍片场效应晶体管及制造鳍片场效应晶体管的方法 Active CN100452432C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/906,335 2005-02-15
US10/906,335 US7224033B2 (en) 2005-02-15 2005-02-15 Structure and method for manufacturing strained FINFET

Publications (2)

Publication Number Publication Date
CN1848454A true CN1848454A (zh) 2006-10-18
CN100452432C CN100452432C (zh) 2009-01-14

Family

ID=36814811

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100074852A Active CN100452432C (zh) 2005-02-15 2006-02-14 鳍片场效应晶体管及制造鳍片场效应晶体管的方法

Country Status (3)

Country Link
US (2) US7224033B2 (zh)
CN (1) CN100452432C (zh)
TW (1) TW200636996A (zh)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102157378A (zh) * 2010-02-11 2011-08-17 中国科学院微电子研究所 一种半导体器件的制造方法
CN101677085B (zh) * 2008-09-20 2011-08-31 台湾积体电路制造股份有限公司 在鳍式场效应晶体管器件中提高迁移率的金属栅应力膜
CN102194756A (zh) * 2010-03-17 2011-09-21 台湾积体电路制造股份有限公司 鳍式场效晶体管及其制法
CN102263131A (zh) * 2010-05-25 2011-11-30 中国科学院微电子研究所 一种半导体器件及其形成方法
WO2012000302A1 (zh) * 2010-07-01 2012-01-05 中国科学院微电子研究所 一种半导体器件及其形成方法
CN102623405A (zh) * 2011-01-30 2012-08-01 中国科学院微电子研究所 一种形成半导体结构的方法
CN102683192A (zh) * 2011-02-22 2012-09-19 格罗方德半导体公司 用后期鳍片蚀刻形成于图案化sti区上的鳍式管
CN102117808B (zh) * 2009-12-31 2013-03-13 中国科学院微电子研究所 具有改善的载流子迁移率的场效应晶体管器件及制造方法
CN103021827A (zh) * 2011-09-27 2013-04-03 中芯国际集成电路制造(上海)有限公司 鳍式场效应管、cmos鳍式场效应管的形成方法
CN103828057A (zh) * 2011-09-30 2014-05-28 英特尔公司 用于晶体管栅极的帽盖介电结构
CN103890905A (zh) * 2011-10-19 2014-06-25 国际商业机器公司 FinFET结构和用于调整FinFET结构中的阈值电压的方法
US9425316B2 (en) 2011-10-01 2016-08-23 Intel Corporation Source/drain contacts for non-planar transistors
CN103828057B (zh) * 2011-09-30 2016-11-30 英特尔公司 用于晶体管栅极的帽盖介电结构
US9580776B2 (en) 2011-09-30 2017-02-28 Intel Corporation Tungsten gates for non-planar transistors
US9634124B2 (en) 2011-12-06 2017-04-25 Intel Corporation Interlayer dielectric for non-planar transistors
CN106653609A (zh) * 2016-12-15 2017-05-10 东莞市联洲知识产权运营管理有限公司 一种新型鳍式场效应晶体管及其制作方法

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909186B2 (en) * 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
US9153645B2 (en) * 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
KR101225816B1 (ko) * 2005-05-17 2013-01-23 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 감소한 변위 결함 밀도를 가지는 래티스 미스매칭된 반도체구조 및 디바이스 제조를 위한 관련 방법
US20070267722A1 (en) * 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7649230B2 (en) * 2005-06-17 2010-01-19 The Regents Of The University Of California Complementary field-effect transistors having enhanced performance with a single capping layer
CN101268547B (zh) * 2005-07-26 2014-07-09 琥珀波系统公司 包含交替有源区材料的结构及其形成方法
US7326617B2 (en) * 2005-08-23 2008-02-05 United Microelectronics Corp. Method of fabricating a three-dimensional multi-gate device
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
JP4880958B2 (ja) * 2005-09-16 2012-02-22 株式会社東芝 半導体装置及びその製造方法
US7615806B2 (en) 2005-10-31 2009-11-10 Freescale Semiconductor, Inc. Method for forming a semiconductor structure and structure thereof
US7575975B2 (en) * 2005-10-31 2009-08-18 Freescale Semiconductor, Inc. Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
EP2062290B1 (en) 2006-09-07 2019-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US20080070355A1 (en) * 2006-09-18 2008-03-20 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US7799592B2 (en) 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
DE102006051494B4 (de) * 2006-10-31 2009-02-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur, die einen Feldeffekt-Transistor mit verspanntem Kanalgebiet umfasst
US20080173942A1 (en) * 2007-01-22 2008-07-24 International Business Machines Corporation STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8779495B2 (en) * 2007-04-19 2014-07-15 Qimonda Ag Stacked SONOS memory
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
US7630121B2 (en) * 2007-07-02 2009-12-08 Qualcomm Mems Technologies, Inc. Electromechanical device with optical function separated from mechanical and electrical function
JP5141686B2 (ja) 2007-07-12 2013-02-13 富士通セミコンダクター株式会社 半導体デバイス及び半導体デバイスの製造方法
US7476578B1 (en) 2007-07-12 2009-01-13 International Business Machines Corporation Process for finFET spacer formation
US7745847B2 (en) 2007-08-09 2010-06-29 United Microelectronics Corp. Metal oxide semiconductor transistor
JP2010538495A (ja) 2007-09-07 2010-12-09 アンバーウェーブ・システムズ・コーポレーション 多接合太陽電池
JP5193583B2 (ja) * 2007-12-17 2013-05-08 株式会社東芝 フィン型トランジスタ
US8133793B2 (en) * 2008-05-16 2012-03-13 Sandisk 3D Llc Carbon nano-film reversible resistance-switchable elements and methods of forming the same
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
WO2009153712A1 (en) * 2008-06-17 2009-12-23 Nxp B.V. Finfet method and device
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8569730B2 (en) * 2008-07-08 2013-10-29 Sandisk 3D Llc Carbon-based interface layer for a memory device and methods of forming the same
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US20100032639A1 (en) * 2008-08-07 2010-02-11 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods of forming the same
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8835892B2 (en) * 2008-10-30 2014-09-16 Sandisk 3D Llc Electronic devices including carbon nano-tube films having boron nitride-based liners, and methods of forming the same
US8421050B2 (en) * 2008-10-30 2013-04-16 Sandisk 3D Llc Electronic devices including carbon nano-tube films having carbon-based liners, and methods of forming the same
US20100108976A1 (en) * 2008-10-30 2010-05-06 Sandisk 3D Llc Electronic devices including carbon-based films, and methods of forming such devices
US8183121B2 (en) 2009-03-31 2012-05-22 Sandisk 3D Llc Carbon-based films, and methods of forming the same, having dielectric filler material and exhibiting reduced thermal resistance
EP2415083B1 (en) 2009-04-02 2017-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
US8263477B2 (en) * 2010-01-08 2012-09-11 International Business Machines Corporation Structure for use in fabrication of PiN heterojunction TFET
US8368146B2 (en) 2010-06-15 2013-02-05 International Business Machines Corporation FinFET devices
KR20120122776A (ko) * 2011-04-29 2012-11-07 에스케이하이닉스 주식회사 반도체 소자 및 그의 제조 방법
DE112011105926T5 (de) 2011-12-09 2014-09-18 Intel Corporation Belastungskompensation in Transistoren
US8697523B2 (en) * 2012-02-06 2014-04-15 International Business Machines Corporation Integration of SMT in replacement gate FINFET process flow
US9024355B2 (en) 2012-05-30 2015-05-05 International Business Machines Corporation Embedded planar source/drain stressors for a finFET including a plurality of fins
US8669147B2 (en) 2012-06-11 2014-03-11 Globalfoundries Inc. Methods of forming high mobility fin channels on three dimensional semiconductor devices
US8604546B1 (en) 2012-07-09 2013-12-10 International Business Machines Corporation Reducing gate resistance in nonplanar multi-gate transistor
US8835292B2 (en) 2012-10-31 2014-09-16 International Business Machines Corporation Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer
US8946063B2 (en) 2012-11-30 2015-02-03 International Business Machines Corporation Semiconductor device having SSOI substrate with relaxed tensile stress
US9040363B2 (en) 2013-03-20 2015-05-26 International Business Machines Corporation FinFET with reduced capacitance
US9178043B2 (en) * 2013-06-21 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Non-planar transistors with replacement fins and methods of forming the same
US10170315B2 (en) 2013-07-17 2019-01-01 Globalfoundries Inc. Semiconductor device having local buried oxide
US8952420B1 (en) 2013-07-29 2015-02-10 Stmicroelectronics, Inc. Method to induce strain in 3-D microfabricated structures
US9099559B2 (en) 2013-09-16 2015-08-04 Stmicroelectronics, Inc. Method to induce strain in finFET channels from an adjacent region
US9590104B2 (en) 2013-10-25 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Gate device over strained fin structure
US9252272B2 (en) * 2013-11-18 2016-02-02 Globalfoundries Inc. FinFET semiconductor device having local buried oxide
US9391171B2 (en) 2014-01-24 2016-07-12 International Business Machines Corporation Fin field effect transistor including a strained epitaxial semiconductor shell
US9660035B2 (en) 2014-01-29 2017-05-23 International Business Machines Corporation Semiconductor device including superlattice SiGe/Si fin structure
US9178068B1 (en) 2014-06-05 2015-11-03 International Business Machines Corporation FinFET with oxidation-induced stress
US20160035891A1 (en) * 2014-07-31 2016-02-04 Qualcomm Incorporated Stress in n-channel field effect transistors
KR102255174B1 (ko) 2014-10-10 2021-05-24 삼성전자주식회사 활성 영역을 갖는 반도체 소자 및 그 형성 방법
TWI629790B (zh) 2015-01-26 2018-07-11 聯華電子股份有限公司 半導體元件及其製作方法
KR102376481B1 (ko) 2015-05-22 2022-03-21 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 제조방법
US9379242B1 (en) 2015-05-28 2016-06-28 United Microelectronics Corp. Method of fabricating fin field effect transistor
US9537011B1 (en) 2015-12-14 2017-01-03 International Business Machines Corporation Partially dielectric isolated fin-shaped field effect transistor (FinFET)
US9484347B1 (en) * 2015-12-15 2016-11-01 International Business Machines Corporation FinFET CMOS with Si NFET and SiGe PFET
US9653602B1 (en) 2016-03-21 2017-05-16 International Business Machines Corporation Tensile and compressive fins for vertical field effect transistors
US10551749B2 (en) 2017-01-04 2020-02-04 Kla-Tencor Corporation Metrology targets with supplementary structures in an intermediate layer
US10964796B2 (en) 2017-02-08 2021-03-30 Globalfoundries U.S. Inc. Heterojunction bipolar transistors with stress material for improved mobility
US11205723B2 (en) 2019-06-27 2021-12-21 International Business Machines Corporation Selective source/drain recess for improved performance, isolation, and scaling

Family Cites Families (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602841A (en) * 1970-06-18 1971-08-31 Ibm High frequency bulk semiconductor amplifiers and oscillators
US4853076A (en) * 1983-12-29 1989-08-01 Massachusetts Institute Of Technology Semiconductor thin films
US4665415A (en) * 1985-04-24 1987-05-12 International Business Machines Corporation Semiconductor device with hole conduction via strained lattice
ATE59917T1 (de) * 1985-09-13 1991-01-15 Siemens Ag Integrierte bipolar- und komplementaere mostransistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung.
JPS6476755A (en) 1987-09-18 1989-03-22 Hitachi Ltd Semiconductor device
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5459346A (en) * 1988-06-28 1995-10-17 Ricoh Co., Ltd. Semiconductor substrate with electrical contact in groove
US5006913A (en) 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5108843A (en) * 1988-11-30 1992-04-28 Ricoh Company, Ltd. Thin film semiconductor and process for producing the same
US5006030A (en) * 1989-03-15 1991-04-09 Waste Management Of North America, Inc. Apparatus for transferring refuse from containers into refuse equipment
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5310446A (en) * 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
US5060030A (en) 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
US5081513A (en) * 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5371399A (en) * 1991-06-14 1994-12-06 International Business Machines Corporation Compound semiconductor having metallic inclusions and devices fabricated therefrom
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US6008126A (en) * 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5679965A (en) * 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5557122A (en) * 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
KR100213196B1 (ko) * 1996-03-15 1999-08-02 윤종용 트렌치 소자분리
US6403975B1 (en) * 1996-04-09 2002-06-11 Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates
US5880040A (en) * 1996-04-15 1999-03-09 Macronix International Co., Ltd. Gate dielectric based on oxynitride grown in N2 O and annealed in NO
US5861651A (en) * 1997-02-28 1999-01-19 Lucent Technologies Inc. Field effect devices and capacitors with improved thin film dielectrics and method for making same
US5940736A (en) * 1997-03-11 1999-08-17 Lucent Technologies Inc. Method for forming a high quality ultrathin gate oxide layer
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US6025280A (en) * 1997-04-28 2000-02-15 Lucent Technologies Inc. Use of SiD4 for deposition of ultra thin and controllable oxides
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
JP3139426B2 (ja) * 1997-10-15 2001-02-26 日本電気株式会社 半導体装置
US6066545A (en) * 1997-12-09 2000-05-23 Texas Instruments Incorporated Birdsbeak encroachment using combination of wet and dry etch for isolation nitride
US6274421B1 (en) 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
KR100275908B1 (ko) * 1998-03-02 2000-12-15 윤종용 집적 회로에 트렌치 아이솔레이션을 형성하는방법
US6165383A (en) * 1998-04-10 2000-12-26 Organic Display Technology Useful precursors for organic electroluminescent materials and devices made from such materials
US6361885B1 (en) * 1998-04-10 2002-03-26 Organic Display Technology Organic electroluminescent materials and device made from such materials
US5989978A (en) * 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
JP4592837B2 (ja) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6319794B1 (en) * 1998-10-14 2001-11-20 International Business Machines Corporation Structure and method for producing low leakage isolation devices
US6235598B1 (en) * 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
US6117722A (en) * 1999-02-18 2000-09-12 Taiwan Semiconductor Manufacturing Company SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
US6255169B1 (en) * 1999-02-22 2001-07-03 Advanced Micro Devices, Inc. Process for fabricating a high-endurance non-volatile memory device
US6284626B1 (en) * 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6656822B2 (en) 1999-06-28 2003-12-02 Intel Corporation Method for reduced capacitance interconnect system using gaseous implants into the ILD
US6281532B1 (en) * 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
KR100332108B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 및 그 제조 방법
TW426940B (en) * 1999-07-30 2001-03-21 United Microelectronics Corp Manufacturing method of MOS field effect transistor
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6284623B1 (en) * 1999-10-25 2001-09-04 Peng-Fei Zhang Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect
US6476462B2 (en) * 1999-12-28 2002-11-05 Texas Instruments Incorporated MOS-type semiconductor device and method for making same
US6221735B1 (en) * 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices
US6531369B1 (en) * 2000-03-01 2003-03-11 Applied Micro Circuits Corporation Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
US6368931B1 (en) * 2000-03-27 2002-04-09 Intel Corporation Thin tensile layers in shallow trench isolation and method of making same
US6493497B1 (en) * 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6501121B1 (en) * 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
US7312485B2 (en) 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US6563152B2 (en) 2000-12-29 2003-05-13 Intel Corporation Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
US20020086497A1 (en) 2000-12-30 2002-07-04 Kwok Siang Ping Beaker shape trench with nitride pull-back for STI
US6265317B1 (en) * 2001-01-09 2001-07-24 Taiwan Semiconductor Manufacturing Company Top corner rounding for shallow trench isolation
US6403486B1 (en) * 2001-04-30 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for forming a shallow trench isolation
US6531740B2 (en) * 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6498358B1 (en) * 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
US6908810B2 (en) 2001-08-08 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation
JP2003060076A (ja) 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
AU2002349881A1 (en) 2001-09-21 2003-04-01 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US20030057184A1 (en) 2001-09-22 2003-03-27 Shiuh-Sheng Yu Method for pull back SiN to increase rounding effect in a shallow trench isolation process
US6656798B2 (en) 2001-09-28 2003-12-02 Infineon Technologies, Ag Gate processing method with reduced gate oxide corner and edge thinning
US6635506B2 (en) * 2001-11-07 2003-10-21 International Business Machines Corporation Method of fabricating micro-electromechanical switches on CMOS compatible substrates
US6461936B1 (en) * 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
US6621392B1 (en) * 2002-04-25 2003-09-16 International Business Machines Corporation Micro electromechanical switch having self-aligned spacers
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6974981B2 (en) 2002-12-12 2005-12-13 International Business Machines Corporation Isolation structures for imposing stress patterns
US6825529B2 (en) 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US6717216B1 (en) 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US6844238B2 (en) * 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6838322B2 (en) * 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US6887798B2 (en) 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7279746B2 (en) 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US7119403B2 (en) 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US6977194B2 (en) 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US7015082B2 (en) 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101677085B (zh) * 2008-09-20 2011-08-31 台湾积体电路制造股份有限公司 在鳍式场效应晶体管器件中提高迁移率的金属栅应力膜
CN102117808B (zh) * 2009-12-31 2013-03-13 中国科学院微电子研究所 具有改善的载流子迁移率的场效应晶体管器件及制造方法
CN102157378A (zh) * 2010-02-11 2011-08-17 中国科学院微电子研究所 一种半导体器件的制造方法
CN102194756A (zh) * 2010-03-17 2011-09-21 台湾积体电路制造股份有限公司 鳍式场效晶体管及其制法
CN102194756B (zh) * 2010-03-17 2013-06-19 台湾积体电路制造股份有限公司 鳍式场效晶体管及其制法
CN102263131A (zh) * 2010-05-25 2011-11-30 中国科学院微电子研究所 一种半导体器件及其形成方法
US8598662B2 (en) 2010-07-01 2013-12-03 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device and method for forming the same
WO2012000302A1 (zh) * 2010-07-01 2012-01-05 中国科学院微电子研究所 一种半导体器件及其形成方法
CN102623405A (zh) * 2011-01-30 2012-08-01 中国科学院微电子研究所 一种形成半导体结构的方法
CN102623405B (zh) * 2011-01-30 2014-08-20 中国科学院微电子研究所 一种形成半导体结构的方法
CN102683192B (zh) * 2011-02-22 2015-01-07 格罗方德半导体公司 用后期鳍片蚀刻形成于图案化sti区上的鳍式管
CN102683192A (zh) * 2011-02-22 2012-09-19 格罗方德半导体公司 用后期鳍片蚀刻形成于图案化sti区上的鳍式管
CN103021827A (zh) * 2011-09-27 2013-04-03 中芯国际集成电路制造(上海)有限公司 鳍式场效应管、cmos鳍式场效应管的形成方法
US9812546B2 (en) 2011-09-30 2017-11-07 Intel Corporation Tungsten gates for non-planar transistors
US9490347B2 (en) 2011-09-30 2016-11-08 Intel Corporation Capping dielectric structures for transistor gates
CN103828057B (zh) * 2011-09-30 2016-11-30 英特尔公司 用于晶体管栅极的帽盖介电结构
US9580776B2 (en) 2011-09-30 2017-02-28 Intel Corporation Tungsten gates for non-planar transistors
US9637810B2 (en) 2011-09-30 2017-05-02 Intel Corporation Tungsten gates for non-planar transistors
CN103828057A (zh) * 2011-09-30 2014-05-28 英特尔公司 用于晶体管栅极的帽盖介电结构
US10020375B2 (en) 2011-09-30 2018-07-10 Intel Corporation Tungsten gates for non-planar transistors
US9425316B2 (en) 2011-10-01 2016-08-23 Intel Corporation Source/drain contacts for non-planar transistors
US10770591B2 (en) 2011-10-01 2020-09-08 Intel Corporation Source/drain contacts for non-planar transistors
US10283640B2 (en) 2011-10-01 2019-05-07 Intel Corporation Source/drain contacts for non-planar transistors
US9853156B2 (en) 2011-10-01 2017-12-26 Intel Corporation Source/drain contacts for non-planar transistors
CN103890905A (zh) * 2011-10-19 2014-06-25 国际商业机器公司 FinFET结构和用于调整FinFET结构中的阈值电压的方法
CN103890905B (zh) * 2011-10-19 2016-05-25 国际商业机器公司 FinFET结构和用于调整FinFET结构中的阈值电压的方法
US10056488B2 (en) 2011-12-06 2018-08-21 Intel Corporation Interlayer dielectric for non-planar transistors
US9634124B2 (en) 2011-12-06 2017-04-25 Intel Corporation Interlayer dielectric for non-planar transistors
CN106653609A (zh) * 2016-12-15 2017-05-10 东莞市联洲知识产权运营管理有限公司 一种新型鳍式场效应晶体管及其制作方法
CN106653609B (zh) * 2016-12-15 2019-11-29 温岭腾科电子有限公司 一种新型鳍式场效应晶体管及其制作方法

Also Published As

Publication number Publication date
US7314802B2 (en) 2008-01-01
US20060180866A1 (en) 2006-08-17
US7224033B2 (en) 2007-05-29
CN100452432C (zh) 2009-01-14
TW200636996A (en) 2006-10-16
US20070122984A1 (en) 2007-05-31

Similar Documents

Publication Publication Date Title
CN100452432C (zh) 鳍片场效应晶体管及制造鳍片场效应晶体管的方法
TWI733704B (zh) 半導體裝置及其製造方法
JP4493343B2 (ja) 歪みフィンｆｅｔ構造および方法
US7824969B2 (en) Finfet devices and methods for manufacturing the same
US7321155B2 (en) Offset spacer formation for strained channel CMOS transistor
US9412822B2 (en) Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
US8120073B2 (en) Trigate transistor having extended metal gate electrode
TW408424B (en) Semiconductor device with silicon replacing structure on the insulated layer and the manufacture method thereof
US7384850B2 (en) Methods of forming complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions therein
US7538351B2 (en) Method for forming an SOI structure with improved carrier mobility and ESD protection
JP5559201B2 (ja) メモリデバイス及びメモリデバイスの形成方法
US9142651B1 (en) Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device
US20140011330A1 (en) Method for manufacturing finfet with improved short channel effect and reduced parasitic capacitance
US20140001561A1 (en) Cmos devices having strain source/drain regions and low contact resistance
US20050035369A1 (en) Structure and method of forming integrated circuits utilizing strained channel transistors
TW200425519A (en) Self-aligned isolation double-gate FET
US9349840B2 (en) Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
US9236258B2 (en) Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
CN105826203A (zh) 形成FinFET晶体管器件的方法和FinFET晶体管器件
CN1523649A (zh) 双栅极场效应晶体管及其制造方法
JP2010258124A (ja) 半導体装置及び半導体装置の製造方法
US20050224880A1 (en) Multi-gate MOS transistor and method of manufacturing the same
US20130161642A1 (en) Semiconductor device and method for manufacturing the same
US7271448B2 (en) Multiple gate field effect transistor structure
CN1956214A (zh) 场效应晶体管及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20171106

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171106

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.