CN1886826A - Dynamic Schottky barrier MOSFET device and method of manufacture - Google Patents
Dynamic Schottky barrier MOSFET device and method of manufacture Download PDFInfo
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- CN1886826A CN1886826A CN 200480035196 CN200480035196A CN1886826A CN 1886826 A CN1886826 A CN 1886826A CN 200480035196 CN200480035196 CN 200480035196 CN 200480035196 A CN200480035196 A CN 200480035196A CN 1886826 A CN1886826 A CN 1886826A
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Abstract
A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.
Description
The cross reference of related application
The application requires the priority of the 60/513rd, No. 410 U.S. Provisional Patent Application of proposition on October 22nd, 2003, and this application has also required the priority of the 60/514th, No. 041 U.S. Provisional Patent Application of proposition on October 24th, 2003.In the above-mentioned temporary patent application each is quoted by integral body and is included in this.
(1) technical field
The present invention relates to be applicable to the device of adjusting current flow, and the manufacturing of these devices in integrated circuit (IC) category is had specific application.Especially, it relates to the transistor that is applicable to the adjustment current flow, and this transistor has metal source and/or the drain electrode that forms Schottky or class Schottky contacts with channel region.
(2) background technology
A kind of well-known transistor types is Schottky barrier metal oxide semiconductor field effect transistor (" Schottky-barrier MOSFET (Schottky-barrier MOSFET) " or SB-MOS) in this area.As shown in Figure 1, SB-MOS device 100 comprises Semiconductor substrate 110, has formed source electrode 120 and drain electrode 125 on this substrate, and the channel region 140 that both are had a channel dopants separately.Channel region 140 is electric current process zones of substrate 110.For the purposes of the present invention, the channel region in Semiconductor substrate 110 140 extends to the border of aiming at substantially with the bottom margin of the bottom margin of source electrode 120 and drain electrode 125 from the vertical lower of gate insulator 150.Channel dopant concentration profile distributes and generally all has maximum concentration of dopant 115, and therefore this be the outside at channel region 140 normally below source electrode 120 and drain electrode 125 electrodes.For purposes of the invention, channel dopants is not subject to and is provided at specially within the channel region 140, but can be found in the zone that fully is positioned at channel region 140 outsides yet.
For the SB-MOS device, source electrode 120 is with at least one some or all ofly is made of metal silicide during drain electrode 125 contacts.At least one is made of part metals in contacting because source electrode 120 is with drain electrode 125, so just formed contacting of Schottky or class Schottky with substrate 110 and channel region 140.Schottky contacts can be defined as the formed contact of tight contact between metal and semiconductor, and the class Schottky contacts can be defined as formed contact of close contact of semiconductor and metal.Schottky contacts or class Schottky contacts just can be provided or tie 130,135 with drain electrode 125 by form source electrode 120 by metal silicide.The length of raceway groove can be defined as touching drain electrode 125 contact, laterally cross over the distance of channel region 140 from source electrode 120.
Schottky contacts or class Schottky contacts 130,135 are in source electrode 120 and drain between 125 in formed channel region 140 adjacent areas.Insulating barrier 150 is in the top of channel region 140.Insulating barrier 150 is made of the material such as silicon dioxide.Channel region 140 extends perpendicularly to the bottom of source electrode 120 and drain electrode 125 electrodes from insulating barrier 150.Gate electrode 160 is positioned at the top of insulating barrier 150, and thin insulating barrier 170 is around gate electrode 160.Thin insulating barrier 170 is also referred to as spacer.Gate electrode 160 can be the polysilicon that mixes.Source electrode 120 and drain electrode 125 electrodes can be in insulation spacer 170 and 160 times horizontal expansions of gate electrode.Field oxide 190 can be with the mutual electrical property insulation of device.In the 6th, 303, No. 479 United States Patent (USP)s of Spinnaker, disclosed a kind of exemplary schottky barrier device.
In the prior art, another kind of known mosfet transistor is traditional doped source-leakage level transistor or traditional MOSFET.This device is similar to the SB-MOS device shown in Fig. 1.Crucial difference is that source metal-drain region 120,125 of SB-MOS is replaced by the doping in the Semiconductor substrate of conventional MOS FET.
An important performance characteristics of MOSFET device is drive current (I
d), it is the source voltage (V that is applying
s) ground connection and grid (V
g) and drain electrode (V
d) with supply voltage (V
Dd) when biasing flow to the electric current of drain electrode from source electrode.Drive current is an important parameter determining circuit performance.For example, transistorized switching speed and I
dProportional, thus drive current is high more, and devices switch is fast more, thereby more high performance integrated circuit is provided.
Fig. 2 shows for SB-MOS device and traditional MOSFET device drive current (I
d) grid voltage (V of 232 pairs of variations
g) and drain voltage (V
d) 231 relation.SB-MOS device I
d-V
dA feature of curve is for low V
d231 sublinear shape is shown in solid line 210,215,220,225,230.I
d-V
dIn the curve 210,215,220,225,230 each has different V
gI
d-V
dCurve is at low V
dThe place is called on state characteristic.Traditional mosfet transistor technology is at low V
dThe place has linear I
d-V
dOn state characteristic is shown in the dotted line among Fig. 2 235,240,245,250,255.I
d-V
dIn the curve 235,240,245,250,255 each has different V
gAlong with reducing of channel length, the sublinear I of SB-MOS device
d-V
dOn state characteristic strengthens, and can reduce transistor performance potentially, might for example reduce effective switching speed of device.The sublinear conducting has been seen in document and as why the SB-MOS device can not obtain actual use in integrated circuit the reason (people such as B.Winstead that is cited, IEEE electronic device journal (IEEE Transactions on Electron Devices), 2000, the 1241-1246 pages or leaves).The industry document is always instructed schottky barrier height Φ
bShould be reduced or make it less than zero, so that minimize sublinear conducting phenomenon and make the performance of SB-MOS device compete (people such as J.Kedzierski, IEDM, 2000, the 57-60 pages or leaves mutually with other MOSFET device technology thus; People such as E.Dubois, solidstate electronics (Solid State Electronics), 2002, the 997-1004 pages or leaves; People such as J.Guo, IEEE electronic device journal (IEEE Transact ions on Electron Devices), 2002, the 1897-1902 pages or leaves; People such as K.Ikeda, IEEE electronic device journal (IEEE Transactions onElectron Devices), 2002, the 670-672 pages or leaves; People such as M.Tao, Applied Physics communication (AppliedPhysics Letters), 2003, the 2593-2595 pages or leaves).
In industry, need to teach SB-MOS device and manufacture method thereof, thereby this can be provided for improving the means that on state characteristic provides improved performance.
(3) summary of the invention
On the one hand, the invention provides the method for a kind of manufacturing Schottky-barrier MOSFET (" SB-MOS ") device, wherein, at least one is made of metal source electrode in contacting with drain electrode, and, wherein the SB-MOS device comprises the boundary layer between at least one and the Semiconductor substrate in metal source or drain electrode, thereby forms Schottky or class Schottky contacts.In one embodiment of the invention, boundary layer is made of conductor material, semi-conducting material or insulating material,
Though disclosed a plurality of embodiment, for those skilled in the art, illustrate the detailed description of embodiment from following demonstration and description the present invention, other embodiments of the invention will become apparent.As recognizing, under the situation that does not deviate from the spirit and scope of the present invention, the present invention can improve aspect tangible many.Therefore, accompanying drawing and detailed description can think only just unrestricted from describing in essence.
(4) description of drawings
Fig. 1 shows the cutaway view of the Schottky barrier metal oxide semiconductor field effect transistor (" MOSFET ") of prior art;
Fig. 2 shows the transistor curves of SB-MOS device and doped source-drain MOS FET device;
Fig. 3 shows the exemplary embodiment of the source electrode-drain electrode SB-MOS device of metal-insulator semiconductor of the present invention (MIS);
Fig. 4 shows the exemplary embodiment of the technology of the present invention of using the injection of Semiconductor substrate ion;
Fig. 5 shows the exemplary embodiment of the technology of the present invention of the patterned silicon film of use on thin gate insulator;
Fig. 6 shows and uses the exemplary embodiment that forms thin insulator sidewall and be exposed to the technology of the present invention of the silicon in grid, source electrode and the drain region;
Fig. 7 shows the exemplary embodiment of the technology of the present invention of the local at least isotropic etching of use;
Fig. 8 shows the exemplary embodiment of using the technology of the present invention that forms thin boundary layer;
Fig. 9 shows the exemplary embodiment of the technology of the present invention of using anisotropic etching;
Figure 10 shows the exemplary embodiment of using metal deposition, silicidation anneal and removing the technology of the present invention of unreacted metal;
Figure 11 shows the energy band diagram that is used for exemplary zero electric field two ends MIS diode component;
Figure 12 shows the energy band diagram that is used for exemplary biased two ends MIS diode component;
Figure 13 shows the energy band diagram of the different gate bias conditions of source electrode-channel junction that do not have the SB-MOS device of interface insulating barrier for having only metal in source electrode-drain region; And
Figure 14 shows the energy band diagram for the different gate bias conditions of the source electrode of MIS source electrode of the present invention-drain electrode SB-MOS device example embodiment-channel junction.
Figure 15 shows the replacement exemplary embodiment of the technology of the present invention of using metal gates.
Figure 16 shows the cutaway view of another exemplary embodiment of the technology of the present invention of using metal-insulator semiconductor (MIS) source electrode-drain electrode SB-MOS device.
Figure 17 shows the cutaway view of another exemplary embodiment of the technology of the present invention of the source electrode-drain electrode SB-MOS device that uses metal-insulator semiconductor (MIS).
(5) embodiment
Generally speaking, the invention provides a kind of method of making the SB-MOS device.In one embodiment of the invention, this method comprises provides Semiconductor substrate and dope semiconductor substrates and channel region.This method also comprises provides the first electrical property insulating barrier that contacts with Semiconductor substrate.This method also comprises the gate electrode that is provided on first insulating barrier, provides around second insulating barrier of gate electrode that comprises gate electrode sidewalls, and substrate is exposed near the gate electrode one or more zones.In the present invention, be defined as being positioned at lateral separation near the term from about 500 of one or more described objects.For example, in the sentence in front, substrate is exposed near the gate electrode one or more zones, perhaps one or more zones are positioned at the lateral separation of leaving about 500 of gate electrode.This method also comprises uses local isotropic etching to be etched near the exposed region of gate electrode.This method also comprises at least provides boundary layer near the Semiconductor substrate that the zone exposed the gate electrode and first insulating barrier, this boundary layer can be made of conductor material, semi-conducting material or insulating material, but preferred insulative material.But this method also comprises uses anisotropic etching to expose nigh zone the Semiconductor substrate below gate electrode not, and provides insulating barrier in gate electrode sidewalls.This method also comprises the deposit film metal and metal and the substrate that is exposed is reacted, thereby form metal silicide on substrate.This method also comprises removes any unreacted metal.
One of advantage of the present invention is that metal source and drain electrode can significantly reduce parasitic series resistance (～10 Ω-μ m) and contact resistance (less than 10
-8Ω-cm
2).Embedded Schottky barrier on Schottky contacts can provide the good control to off-state leakage current.This device has been eliminated parasitic bipolar action basically, makes it can unconditionally exempt breech lock, boomerang effect in memory and logic and the soft error of multiple unit.Eliminate the generation that bipolar action has also reduced other adverse effect relevant with parasitic bipolar action significantly, such as the upset of single incident and the soft error of single unit.Device of the present invention is made easily, only needs to be used for the less mask of two covers that source/drain forms, and does not need shallow-layer diffusion or deep layer source/drain to inject, and only adopts the low temperature source/drain to form technology.Owing to adopt low temperature process, thus just can novel, the potential critical material of easier formation such as high-K gate insulator, strained silicon and metal gates integrated.
Fig. 3 shows the viewgraph of cross-section of preferred embodiment of the present invention, comes illustration by metal-insulator semiconductor (MIS) source electrode-drain electrode SB-MOS structure 300.This embodiment comprise source electrode 305 wherein or drain in 310 at least one constitute by metal so that the SB-MOS device that does not have in source electrode and/or the drain region to mix.In this embodiment, this device comprises boundary layer 315, boundary layer is made of electric conducting material, semi-conducting material or insulating material, be arranged on metal source 305 or 310 electrodes that drain at least one and Semiconductor substrate 301 between, boundary layer 315 contacts with channel region 320, thus first Schottky barrier or the class Schottky Barrier Contact 325 of formation and channel region 320.In a preferred embodiment, boundary layer 315 is insulating layer materials.Form second Schottky or class Schottky barrier 330 along the metal source 305 with direct contact between metal and Semiconductor substrate 301 and/or the part of 310 electrodes that drain.The present invention does not approve that any restriction of relevant what metalloid of use can influence religious doctrine of the present invention.Thereby especially the metal that is generally used for transistor level is used in expectation, such as titanium, cobalt etc. and multiple rare metal and other alloy.Also can adopt various metal silicides, such as platinum silicide, palladium silicide, silication iridium and/or rare earth silicide, all metal silicides should be considered within religious doctrine scope of the present invention.Also should indicate, in another embodiment, metal source/drain zone 305,310 can be made of multiple layer metal and/or metal silicide.
In a preferred embodiment, indium or arsenic layer 340 are used as the raceway groove and the substrate impurity layer of Schottky barrier N type MOSFET (SB-NMOS) or Schottky barrier P type MOSFET (SB-PMOS) device respectively.Use these atoms of dopant to be because they have the low relatively diffusivity of passing silicon crystal lattice (comparing with the phosphorus or the boron of two kinds of candidates in addition as raceway groove and substrate dopant).This allows to have bigger heat balance in the process of making device, thereby has statistics variations still less in the characteristic of finished product.With regard to the alloy what type the present invention can use, the present invention does not approve any restriction.
In a preferred embodiment, for P type and N type device, gate electrode 345 is respectively by the polysilicon film manufacturing of boron or phosphorus doping.In this case, using boron or phosphorus is because they have big solid solubility (comparing with arsenic and indium).Perhaps, can use metal gates.In the present embodiment, the width of gate electrode 345 (corresponding to channel length) can be less than 100nm.Gate electrode 345 has the sidewall 350 of electrical property insulation, and what this sidewall can be for oxide, nitride or different insulative material is multilayer laminated.
By such as working together with the alloy of raceway groove and substrate so that the device insulating barrier (not shown) the thermal growth oxide (so-called field oxide) of electrical property insulation each other device can be separated from each other.Can provide field oxide by the traditional handicraft such as LOCOS or STI technology.
A kind of illustrative processes of making MIS source/drain SB-MOS device is shown in Fig. 4-10.Though this processing is the exemplary of broad teachings of the present invention, it will be guiding to those skilled in the art, to instruct basic conception of the present invention.Should be noted in the discussion above that this illustrative processes is not restrictive, to those skilled in the art, other special technology of the present invention's expectation will be tangible.This exemplary process flow can be described below:
Fig. 4 shows to have and makes the transistor silicon substrate 410 of the mode of electrical property insulation each other.By discussion, as long as, will have a plurality of examples with reference to the Semiconductor substrate that forms the SB-MOS device in the above at this.The present invention is not limited to Semiconductor substrate any special type.Those skilled in the art will recognize at an easy rate that the many Semiconductor substrate that comprise silicon, SiGe, GaAs, indium phosphide, strain semiconductor substrate and silicon-on-insulator (SOI) can be used for such as＜110〉and＜100 the SB-MOS substrate in various crystal orientation.In another embodiment, silicon substrate 410 is strains.Use can cause the extra improvement of power and speed ability in conjunction with the strained silicon substrate of AB-MOS device.In another embodiment, substrate is SOI.The SOI substrate can be included in to embed and be approximately the semi-conducting material of 20nm to the silicon of 100nm such as thickness on the insulating material, and the embedding insulating material can be formed on the Semiconductor substrate, be approximately the silicon dioxide (SiO of 100nm such as thickness to 400nm
2).These backing materials and any other Semiconductor substrate can be used, and they are also all within teachings of the present invention.
As shown in Figure 4, can on substrate 410, grow thin screen oxide 420 to play the effect of injecting mask.In one embodiment, oxide growth is to the thickness of about 200 .Inject suitable channel dopants material 430 by the screen oxide ion then, so that maximum concentration of dopant 440 is set at the desired depth D1 (450) in the silicon.In one embodiment, for P type device, the channel dopants material is an arsenic, and is indium for N type device, and still, the present invention especially expects any other dopant substance that the transistor of P type or N type device is used always.In another embodiment, channel dopant concentration profile is distributed in the vertical direction marked change, but laterally is being generally constant.In another embodiment, the depth D 1450 of maximum dopant concentration is about 20 to 200nm.
As shown in Figure 5, remove screen oxide with chemical etching then, and the thin gate insulator 510 of growth one deck such as silicon dioxide.In one embodiment, the screen oxide etching can be undertaken by hydrofluoric acid.Yet also special expectation uses other to be usually used in the chemical method of etching oxide, comprises wet method and dry etching.In another embodiment, Bao gate insulator is made up of the silicon dioxide of about 6 to 50 thickness.In another embodiment, provide the have high-k material of (high K).The example of hafnium is the materials of those dielectric constants greater than the dielectric constant of silicon dioxide, comprises, for example, nitrided silicon dioxide (nitrided silicon dioxide), silicon nitride and such as TiO
2, Al
2O
3, La
2O
3, HfO
2, ZrO
2, CeO
2, Ta
2O
5, WO
3, Y
2O
3And LaAlO
3Metal oxide or the like.Behind the silicon thin film that provides original position (in-situ) to mix, gate insulator begins growth immediately.This film is heavy doping, for example, N type device is adopted phosphorus, and P type device is adopted boron.Using photoetching technique and silicon etching technology is good selection for gate insulator, gate electrode 520 is carried out graphically, shown in the processing step among Fig. 5 500.In another exemplary embodiment, can provide the gate electrode of metal.In another embodiment, after gate electrode is graphical, provide other channel dopant, make channel doping density be distributed on the vertical and horizontal both direction obvious variation all takes place.
As shown in Figure 6, on the upper surface 625 of silicon gate electrode 520 and sidewall 610, provide thin insulator.In one embodiment, Bao insulator is the thermal growth oxide that thickness is approximately 50 to 500 .In another embodiment, by adopting rapid thermal oxidation (RTO) technology, its have the duration be 0.0 to 60 second 900 degree Celsius to the maximum temperatures of 1200 degree, provide the heat growth thin oxide.Those skilled in the art recognize have many manufacture methods can be used to the insulating barrier that provides thin easily, for example, and deposition process.Those skilled in the art also will further recognize, can use other material as thin insulator, for example, and nitride, and insulating barrier can be made up of multiple insulating material.Subsequently, can use the insulating barrier (and expose silicon 620 and 625) of anisotropic etching removal on horizontal surface, thereby expose horizontal surface, be retained in the insulating barrier on the vertical surface simultaneously.Like this, just formed side wall insulator 610.Those skilled in the art will be understood that 610 pairs of isotropic etchings of gate electrode 520 and side wall insulator have the function of mask, make that opening and the gate electrode 520 in the insulating barrier that approaches on silicon substrate is approaching.In one embodiment, to be approximately 50 to 500 thick for Bao insulator.Opening in thin insulating barrier will be with approaching to gate electrode 520, and in the scope of about 50 to 500 of the lateral separation that departs from gate electrode 320.In one exemplary embodiment, the recessed 1nm that is approximately to the bottom of gate insulator of silicon face 620 is to the about depth D 2630 of 5nm.In one exemplary embodiment, adopt RTO technology, side wall insulator is provided, can when side wall insulator forms, activate by electrical property at device grids electrode and the alloy in channel region, just as shown in Figure 6 shown in the processing step 600.
As shown in Figure 7, the second etching technics step is carried out horizontal and vertical etching semiconductor substrate.This etching is referred to as local isotropic etching.In one embodiment, use lateral etching speed to be at least the local isotropic etching of vertical etch rate 10%.In another embodiment, use vertical etch rate to be at least the local isotropic etching of lateral etching speed 10%.The degree of depth of second etching is D3710.The vertical sidewall that lateral etching is exposed Semiconductor substrate 720 from the edge of side wall oxide 610 with the lower position of distance L 1730 transverse shifts to gate electrode 520.Because etching is local isotropic, so L1 can be less than or equal to ten times of D3, or D3 can be less than or equal to ten times of L1.In another embodiment, use lateral etching speed to approximate the etching of vertical etch rate greatly.In this embodiment, D3 can approximate L1 greatly.Lateral etching provides the means that channel length reduced the amount that approximately doubles L1.In one embodiment, shown in the processing step among Fig. 7 700, the vertical enough formation of etch rate laterally is positioned at the exposure vertical surface 720 of the Semiconductor substrate 410 under the gate electrode 520.In also having an embodiment, adopt SF
6Dry etching, HF:HNO
3Any or its combination in the wet etching or be applicable to that any wet method or dry etching that the etching semiconductor material is used always provide local isotropic etching.
As shown in Figure 8, boundary layer 810 is formed on the level and vertical surface of Semiconductor substrate 410 exposures.In one embodiment, shown in the processing step 800, boundary layer 810 is the hot grown silicon nitride (Si that have less than about 2nm thickness as shown in Figure 8
3N
4).In another embodiment, boundary layer 810 is made up of in metal, semiconductor or the insulating material any.
As shown in figure 10, next step comprises that the deposition proper metal is as the cover film on all exposed surfaces.Can adopt sputter or evaporation technology or other any film shaped technology commonly used that deposition is provided.In one embodiment, in the process of metal deposition, substrate heats, and the metallic atom that is clashed into to impel is diffused in institute's exposed silicon surface 810 under the gate insulator.In one embodiment, about 250 are thick for this metal, but it is thick to be typically about 50 to 1000 .By the discussion here, as long as just provide more example with the class Schottky barrier with contacting with reference to relevant Schottky in IC makes.The present invention does not approve that the schottky interface of relevant which kind of type can be used to influence any restriction of religious doctrine of the present invention.Thereby the present invention expects to adopt any type of electric conducting material or alloy to create the contact of these types especially.For example, for P type device, metal source and drain electrode 1010,1020 can be made of any or its combination in platinum silicide, palladium silicide or the silication iridium.For N type device, metal source and drain electrode 1010,1020 can be made by being selected from the rare earth silicide family material that comprises such as silication erbium, silication dysprosium or ytterbium silicide or its combination.Expectation is especially, any other metal that uses transistor level to use always, and such as titanium, cobalt etc., and other multiple rare metal and other alloy.In another embodiment, silicided source/drain electrode can adopt the multiple layer metal silicide to make, and in this case, for example can use other the typical silicide such as titanium silicide or tungsten silicide.
Subsequently, wafer is continued special time anneal under specific temperature, make that metal all directly contacts with silicon on all positions, produce chemical reaction metallic transition is become metal silicide 1010,1020 and 1030.In one embodiment, for example, wafer can continue about 45 minutes annealing under 400 degree approximately Celsius, perhaps continue about 1 to 120 minute annealing usually under 300 to 700 degree Celsius.Still keep unreacted with the metal that non-silicon face such as gate lateral wall spacer 610 directly contacts, and therefore and not influence.
Subsequently, use wet chemical etch,, keep untouchable metal silicide simultaneously to remove unreacted metal.In one embodiment, use chloroazotic acid to remove platinum, use HNO
3Remove erbium.The present invention expects especially to use and is applicable to any etch chemistries method that other is suitable for that etching platinum or erbium use always or is applicable to and form Schottky or employed any other suitable metal series of class Schottky contacts.Now, just finished the SB-MOS device of MIS source electrode-drain electrode, and prepare to have realized grid 520, source electrode 1010 and 1020 the electrical property of draining is connected, shown in the processing step among Figure 10 1000.
As the result of this illustrative processes, channel region 1040 and substrate 410 have been formed Schottky or class Schottky contacts respectively, wherein, Schottky contacts is positioned on the position that local isotropic etching technology controlled.In one embodiment, source electrode 1010 and drain electrode 1020 electrodes laterally are positioned at the below of spacer 610 with the interface 810 of channel region 1040 and aim at the edge on gate electrode 1040 each limit.In another embodiment, the interface 810 of source electrode 1010 and drain electrode 1020 electrodes and channel region 1040 laterally is positioned at the below of spacer 610 and part below gate electrode 520.In also having an embodiment, between each edge, limit of the interface 810 of source electrode 1010 and drain 1020 electrodes and channel region 1040 and gate electrode 520, formed the gap.
Though the traditional schottky contact is precipitous, the present invention has used boundary layer between silicon substrate and metal.This boundary layer can be ultra-thin, and the thickness that is had is approximately 10nm or littler.So the present invention is desirably in especially and realizes in the process of the present invention that class Schottky contacts and equivalent thereof are very useful.In addition, boundary layer can be made of the material with conduction, semiconductive or class insulation characterisitic.For example, wherein, can use oxide or nitride insulator ultra-thin interfacial layer, can use by the formed ultra-thin alloy layer of alloy isolation technology or can use semi-conductive ultra-thin interfacial layer to form the class Schottky contacts such as germanium.
The technology of the application of the invention can produce the benefit of several respects.At first, metal-insulator semiconductor (MIS) structure provides the means of the effective schottky barrier height that is used for dynamically controlling the SB-MOS device.With reference to Figure 11, show the energy band diagram that is used for exemplary MIS diode component.Its basic functional principle and technical terms have been made description in the doctorate paper of Mark Sobol ewski 1989, Stanford University.
In Figure 11, show N type MIS diode energy band diagram with desirable zero electric field status.In fact, can there be limited fields inside in interfacial insulator layer.Metal work function Φ
m(1105) and semiconductor electronic affinity χ
s(1110) be used to conduction band (1115) with reference to insulating barrier.E
Fm(1120) and E
Fs(1125) be respectively metal and semiconductor fermi, and E
c(1130) be conduction band.V
d(1135) and V
i(1140) be respectively potential drop in semiconductor substrate depletion region and insulator, and ζ (1145) is the interval between Fermi level and the conduction band deep in the semiconductor volume.Insulation thickness is t
i(1150) and effectively schottky barrier height Φ
B, 1(1155) be defined in silicon-on-insulator E at the interface
Fm(1120) and E
c(1130) interval between.In desirable zero electric field status, by Φ
m(1105) and χ
s(1110) determine Φ
D, 1(1155), these two all is the physical characteristic of this system.
φ
B1=φ
m-χ
s. equation 1
In Figure 12, positive bias is imposed on metal with respect to the Semiconductor substrate of ground connection, thereby with respect to E
Fs(1125) moved E
Fm(1120) up to-V (1205).This is at interfacial insulator layer ε
s(1210) induced electric field, thereby set up potential drop V at the insulator two ends
i(1215).At this state, give the effective schottky barrier height Φ that makes new advances by equation 2
B, 2(1220).
φ
b，2＝φ
m-χ
s-V
i
=φ
B, 1-V
iEquation 2
Therefore, at the potential drop V of insulator interfacial layer
i(1215) provide volume value V
i(1215) come the effective schottky barrier height Φ of dynamic control break between metal and Semiconductor substrate
B.2(1215) means.Potential drop in insulator layer will be the insulator layer thickness t
i(1150), metal biasing 1205 and at the electric field strength ε at insulator place
s(1210) and the function of insulator dielectric constant.
These principles can be applicable to have the SB-MOS device that the MIS source electrode contacts with drain electrode.When considering the operating characteristic of MOSFET, contact with channel region and just the MIS source electrode below gate insulator partly determined device performance, especially under the situation of conducting state.In addition, because three end MOSFET structures, the electric field in the MOSFET channel region has the feature of two dimension.For this reason, the Schottky barrier that induces along the interface of source electrode and channel region is regulated and is changed, has maximum at source electrode and raceway groove and the crossing place of gate insulator.Following discussion relates to " active " source electrode MIS zone.This is the source electrode MIS structure below gate insulator just, has extended about 5-20nm along source electrode-channel junction below gate electrode.It is that the grid induction electric field provides forceful electric power potential drop and takes place from the zone that source electrode sends about electric current more than 90% in conducting state in the MIS insulator.
In cut-off state, grid contacts ground connection with source electrode, and drain electrode is with V
DdBiasing will provide first electric field at the insulator of source electrode MIS structure, at insulator V
I, dTwo ends produce first potential drop and first effective schottky barrier height Φ
BdBut the important difference between three end MIS source electrode-drain MOS FET devices of the present invention and two ends MIS diode is, in three ends, gate electrode tightly be positioned at source electrode the MIS structure near.Depend on the MOSFET geometry, in 10 nanometers of source electrode displacement, gate electrode about 1nm that can be shifted.In conducting state, at source electrode and grid all with V
DdDuring biasing, the source electrode contact keeps ground connection.Because grid and source electrode is closely approaching, formed abundant second electric field greater than first electric field in active source electrode MIS zone, thereby at insulator V
IdgTwo ends induce second potential drop and the second effective barrier height Φ
BdgAlong the vertical direction part of the source electrode adjacent with channel region, when gate insulator moved down, the electric field of grid induction can reduce, thereby made V
IdgReduce, and as the Φ of position function
BdgIncrease.Schottky barrier height has greatly influenced the current emission characteristic from source electrode.
For the SB-MOS technology, provide current emission from source electrode with the tunnelling mechanism of conducting state.Figure 13 shows for the three kind different gate bias (Vs of the traditional n type SB-MOS device that does not have the MIS structure at source electrode-channel interface place
g) energy band diagram.As shown in the figure, in the zone near source electrode, conduction band forms subtriangular potential barrier 1310,1320,1330.Tunnelling current by this Schottky barrier with exponential relationship to barrier height Φ
b1340 and Schottky Barrier Contact ε
s1350,1351,1352 sensitivities.Importantly, note for this device, barrier height Φ
bThe 1340th, fix, and grid is regulated ε
s1350,1351,1352, thus tunnelling current increases with the increase of gate bias.
Figure 14 shows for the three kind different gate bias Vs of the N type SB-MOS device with MIS source at source electrode-channel interface place
gEnergy band diagram.Only show the energy band portion of MIS insulator layer.In the zone near source electrode, conduction band forms subtriangular potential barrier 1410,1420,1430 again.For the MIS device, regulate effective barrier height Φ with grid
b1440,1441,1442, regulate ε simultaneously
s1450,1451,1452, thus two kinds of mechanism that increase tunnelling current are provided, and be a kind of mechanism (ε unlike traditional SB-MOS device
sRegulate).As long as biasing V
gFor any V
dThis effect will take place, thereby to low V
dTo provide the drive current of improvement, reduced at low V
dThe sublinear on state characteristic and improved the conduction property of SB-MOS device, and provide higher drive current.
Importantly, insulator can not be too thick, this be because the tunnelling possibility of electric charge carrier gradually the insulated body potential barrier forbid, thereby reduced Schottky barrier is adjusted to benefit than low-lying level.
MIS source electrode-other benefit of drain electrode SB-MOS device architecture is enough thick insulator interfacial layer, it will stop the infiltration of metallic state, and the infiltration of metallic state can cause the obstruction (for example " new development (A New Route to Zero-Barrier MetalSource-Drain MOSFETs) of zero barrier metal source electrode-drain MOS FET " delivered referring to people such as D.Connelly in 2003) in the silicon in capital of a country VLSI seminar in 2003.This provides the means that influenced initial barrier height before any gate bias, and can allow to introduce other metal or metal alloy that will be used as metal source-drain electrode contact.
In a word, the boundary layer that is provided with between the Semiconductor substrate of metal source-drain electrode contact and MIS source/drain SB-MOS device provides the initial effectively means of schottky barrier height that are used to influence not biasing, and the means by changing grid, secondly dynamically regulating schottky barrier height for drain bias also are provided.This makes can introduce the preferred embodiment that many metals, metal silicide and/or metal alloy are used to influence religious doctrine of the present invention, and not have the simple metal-semiconductor schottky barrier junction of boundary layer will be impossible and adopt.It also makes can have the low V that substantially improves
dThe drive current of closing characteristics and Geng Gao.
Figure 15 shows the viewgraph of cross-section of another preferable examples of the present invention embodiment, is specially the source electrode-drain electrode SB-MOS structure 1500 of metal-insulator semiconductor (MIS).This embodiment comprises at least one the SB-MOS device that is made of the one 1506 and the 2 1507 metal in source electrode wherein 1505 and the drain electrode 1510, so that do not mix at source electrode and/or drain region.In this embodiment, device comprises boundary layer 1515, this boundary layer can be conduction, semiconductive or insulation, be placed between first metal 1506 and the Semiconductor substrate 1501, boundary layer 1515 contacts with channel region 1520, thereby forms first Schottky barrier or class Schottky contacts 1525 with channel region 1520.This boundary layer 1515 also can be placed between second metal 1506 and the Semiconductor substrate, thereby can form second Schottky or class Schottky contacts 1526 with Semiconductor substrate 1501.
Illustrative processes can provide first and second metals below using.After the processing step 800 shown in Figure 8, isotropically deposit first metal, be included in any zone of gate electrode below.Etching first metal anisotropically subsequently.Directionally deposit second metal then, being minimized in the deposition on the gate electrode sidewalls, and use brief isotropic etching to be deposited on any metal on gate electrode sidewalls or other vertical surface with removal.Transistor is masked and isotropic more completely etching is provided.In one exemplary embodiment, select mainly to be positioned at the altitude response of the Schottky barrier of first metal of gate electrode below and channel region, so that the leakage current of the driving of optimised devices and/or optimised devices.In another exemplary embodiment, fill second metal of the volume of source electrode-drain region and can select according to its conductivity, preferably have the metal of high conductivity.In addition, also can be designed to the stacked of alloy or metal, so that simultaneously SB-NMOS and the two control cut-off state of SB-PMOS are leaked so that for example it presents the volume of regions and source and the potential barrier of the mid-gap between the Semiconductor substrate.Also can adopt alloy or metal stacking to be used to optimize conductivity or be used for the integrated characteristic of its technology second metal of (such as the ability of etching stopping is provided) in the contact hole that is formed for metallisation and transistor device lead-in wire.The aforesaid selection criterion that is used for first and second metals can be applicable to this and all other embodiment of disclosing before or subsequently.
With regard to first and second metals of which kind of type can influence religious doctrine of the present invention, the present invention did not approve any restriction.Thereby especially the metal that transistor level is used always is used in expectation, such as titanium, cobalt etc., and provides suitable first and second Schottky barriers multiple rare metal and other alloy with optimized device performance.Also can adopt various metal silicides, such as platinum silicide, palladium silicide, silication iridium and/or rare earth silicide, all metal silicides should be considered within religious doctrine scope of the present invention.In another embodiment, first and second metals are identical, and available identical processing step or two kinds of different processing steps provide.
Indium or arsenic layer 1540 are used as the raceway groove of NMOS or PMOS device and the alloy of substrate respectively.Boron can be used as the raceway groove and the substrate dopant of nmos device.The gate electrode 1545 of P type and N type device is respectively by the polysilicon film manufacturing of boron or phosphorus doping.Gate electrode 1545 has gate insulator 1550 and electrical property insulative sidewall 1551, and they can be the multilayer laminated of oxide, nitride or different insulative material, shown in the device 1500 of Figure 15.
Figure 16 shows the viewgraph of cross-section of another preferred embodiment of the present invention, is specially the source electrode-drain electrode SB-MOS structure 1600 of metal-insulator semiconductor (MIS).This embodiment comprises at least one the SB-MOS device that is made of the one 1606 and the 2 1607 metal in the wherein source electrode 1605 and drain region 1610, so that do not mix at source electrode and/or drain region.In this embodiment, device comprises first boundary layer 1615, this boundary layer can be conduction, semiconductive or insulation, be placed between first metal 1606 and the Semiconductor substrate 1601, first boundary layer 1615 contacts with channel region 1620, thereby contacts 1625 with channel region 1620 formation first Schottky barriers or " class Schottky ".In addition, between second metal 1607 and Semiconductor substrate 1601, placed the second thick boundary layer 1617.Available deposition angled, rotation provides second contact surface layer 1617.Do not need to constitute second contact surface layer 1617 with the material of the identical materials or first boundary layer 1615.The second contact surface layer is provided with big potential barrier to the electric current that is sent to Semiconductor substrate from second metal.In a further exemplary embodiment, first and second metals are identical, and available identical processing step or two kinds of different processing steps provide.
The second contact surface layer can-LOCOS technology little by being called in addition the LOCOS technology of source electrode-drain electrode location provide.After the processing step shown in Fig. 7 700, the liner oxide of deposition of thin, the next thicker nitride layer of deposition.Available anisotropic etching etching is passed nitride and the pad oxide in source electrode-drain region, exposes Semiconductor substrate.The oxide of hot grow thick on the Semiconductor substrate that has exposed, and the phosphorus nitride layer of taking and having exposed except any.The hydrofluoric acid of short time has been removed the pad oxide on the channel region vertical sidewall, forms thin hot grown nitride layer thereafter.An advantage of present embodiment is to have avoided thick insulator is placed on the top of gate electrode, and thick insulator can be the result of the insulator of direct deposit.Any zone that first metal is included in gate electrode below is by deposition isotropically and by etching anisotropically.Directionally deposit second metal, being minimized in the deposition on the gate electrode sidewalls, and use brief isotropic etching to be deposited on any metal on gate electrode sidewalls or other vertical surface with removal.Transistor is masked and provide the isotropic more completely etching of second metal.With regard to first or second metal of which kind of type can influence religious doctrine of the present invention, the present invention did not approve any restriction.Thereby especially the metal that transistor level is used always is used in expectation, such as titanium, cobalt etc., and provides suitable first Schottky barrier multiple rare metal and other alloy with optimized device performance.Also can adopt various metal silicides, such as platinum silicide, palladium silicide, silication iridium and/or rare earth silicide, all metal silicides should be considered within religious doctrine scope of the present invention.
Indium or arsenic layer 1640 are used as the raceway groove and the substrate dopant of NMOS or PMOS device respectively.Boron can be used as the raceway groove of nmos device and the alloy of substrate.The gate electrode 1645 of P type and N type device is respectively by the polysilicon film manufacturing of boron or phosphorus doping.Perhaps, can use metal gates.Gate electrode 1645 has gate insulator 1650 and electrical property insulative sidewall 1660, and they can be the multilayer laminated of oxide, nitride or different insulative material, shown in the device 1600 of Figure 16.
With reference to Figure 16, in another exemplary embodiment, can use metal-semiconductor (MIS) source electrode-drain electrode SB-MOS structure.In this structure, can not provide first boundary layer 1615, so that first metal 1606 directly contacts with channel region 1620.Emphasize do not have boundary layer to be arranged between first metal 1606 and the channel region 1620.In this embodiment, the first metal layer 1606 can be metal, alloy or silicide.In addition, can use above-mentioned same procedure that second metal level 1607 is set, comprise for example craft of orientated deposition techniques.
Figure 17 shows the viewgraph of cross-section of another preferred embodiment of the present invention, is specially the source electrode-drain electrode SB-MOS structure 1700 of metal-insulator semiconductor (MIS).This embodiment comprises that in source electrode wherein 1705 and drain electrode 1710 zones at least one is by the one 1706 and the SB-MOS device that constitutes of optional the 2 1707 metal, so that do not mix at source electrode and/or drain region.In this embodiment, device comprises boundary layer 1715, this boundary layer can be conduction, semiconductive or insulation, be placed between first metal 1706 and the Semiconductor substrate 1701, boundary layer 1715 contacts with channel region 1720, thereby contacts 1725 with channel region 1720 formation first Schottky barriers or " class Schottky ".Source electrode 1705 contacts with drain electrode 1710 regional and embedded oxides 1717, such as the embed oxide of SOI substrate.The oxide 1717 of this embedding provides being sent to the big potential barrier of the electric current of Semiconductor substrate 1701 from second metal 1707, thereby has reduced source electrode-drain leakage.In a further exemplary embodiment, first and second metals 1706,1707 are identical, and available identical processing step or two kinds of different processing steps provide.
Illustrative processes can provide first and second metals below using.After the processing step 800 shown in Figure 8, isotropically deposit first metal, be included in any zone of gate electrode 1745 belows.Subsequently, etching first metal 1706 anisotropically.Then, directionally deposit second metal,, and use brief isotropic etching to be deposited on any metal on gate electrode sidewalls 1760 or other vertical surface with removal with the deposition on the sidewall 1760 that is minimized in gate electrode 1745.Transistor is masked and provide the isotropic more completely etching of second metal 1707.Select first and second metals 1706,1707 based on aforesaid criterion.In another exemplary embodiment, first and second metals 1706,1707 are identical, and available identical processing step or two kinds of different processing steps provide.
Indium or arsenic layer are used as the channel dopants of NMOS or PMOS device respectively.Boron can be used as the raceway groove of nmos device and the alloy of substrate.The gate electrode 1745 of P type and N type device is respectively by the polysilicon film manufacturing of boron or phosphorus doping.Perhaps, can use metal gates.Gate electrode 1745 has gate insulator 1750 and electrical property insulative sidewall 1760, and they can be the multilayer laminated of oxide, nitride or different insulative material, shown in the device 1700 of Figure 17.
With reference to Figure 17, in another exemplary embodiment, can use the source electrode-drain electrode SB-MOS structure of metal-semiconductor (MIS).In this structure, can not provide boundary layer 1715, so that first metal 1706 directly contacts with channel region 1720.Emphasize do not have boundary layer to be arranged between first metal 1706 and the channel region 1720.In this embodiment, the first metal layer 1706 can be metal, alloy or silicide.In addition, can use above-mentioned same procedure that second metal level 1707 is set, comprise for example craft of orientated deposition techniques.
The present invention is particularly useful for using under the situation of MOSFET that will the production short channel length, and particularly channel length is in the scope less than 100nm.But, in religious doctrine of the present invention, religious doctrine of the present invention is applied to these short channel length devices without any restriction.The favourable use that the channel length of employing virtually any size all can have religious doctrine of the present invention.The present invention also expects to use more raceway groove, substrate and well region ion to inject distribution.For example, it can be simple distribution that channel ion injects, and it is distributed in obviously difference of vertical direction, and laterally is being generally constant.Perhaps, for example inject to distribute roughly to be symmetrical to channel ion, and laterally Cmax is greatly about the center of channel region.Perhaps, can use laterally and vertical uneven dopant profiles.
Although described the present invention with reference to preferred embodiment, those skilled in the art will recognize that, can carry out various variations under the conditions without departing from the spirit and scope of the present invention in form and details.Raceway groove, substrate and well region ion that the present invention can be applied to any amount inject distribution.The present invention is applicable to any use of metal source drain technology, no matter is to adopt SOI substrate, strained silicon substrate, SiGe substrate, FinFET technology, high-K gate insulator and metal gates.This enumerates not restriction.Any device that flows that adopts metal source-drain electrode contact to adjust electric current all will have the benefit that this paper teaches.
Yet the present invention is specially adapted to the SB-MOS semiconductor device and uses, and it also can be used for other semiconductor device.Therefore, although this specification has been described the employed manufacturing process of SB-MOS, these contents also should be broadly understood comprise be used to adjust have the contact of 2 or multiple spot electrical property and wherein at least one electrical property contact be any device that the conducting channel electric current of Schottky or class Schottky contacts flows.
Claims (23)
1. MOSFET device comprises:
Gate electrode on the Semiconductor substrate;
Source electrode on the Semiconductor substrate and drain electrode, at least one in wherein said source electrode and the described drain electrode is metal; And
Boundary layer between at least one electrode in described substrate and described metal source and drain electrode.
2. device as claimed in claim 1 is characterized in that, described boundary layer is arranged in the zone of contiguous at least described gate electrode.
3. device as claimed in claim 1 is characterized in that, whole Schottky or class schottky junction between at least one electrode in described substrate and described metal source and the drain electrode comprise described boundary layer.
4. device as claimed in claim 1 is characterized in that, in the zone of contiguous described gate electrode, Schottky or class schottky junction between at least one electrode in described substrate and described metal source and the drain electrode comprise described boundary layer at least.
5. device as claimed in claim 1 is characterized in that, has described metal source and at least one electrode in the drain electrode and the described substrate formation Schottky or the class schottky junction of described boundary layer.
6. device as claimed in claim 1 is characterized in that described boundary layer comprises insulator.
7. a manufacturing is used to regulate the method for the MOSFET device that electric current flows, and this method comprises:
On Semiconductor substrate, prepare gate electrode;
Be exposed to the interior described Semiconductor substrate in zone of contiguous described gate electrode;
Use local at least isotropic etching to be etched in Semiconductor substrate on the described zone of exposure;
Depositing metal films in the described etch areas of described Semiconductor substrate; And
Make the reaction of described metal and described Semiconductor substrate, so that form in Schottky or class schottky source electrode and the drain electrode at least one.
8. method as claimed in claim 7 is characterized in that, it approximately is that 1/10 to 10 times etching of vertical etch rate is carried out that described etch step is to use lateral etching speed.
9. method as claimed in claim 7 is characterized in that, described etch step be to use have roughly the same laterally and the etching of vertical etch rate carry out.
10. method as claimed in claim 7 is characterized in that, described gate electrode can adopt the following step preparation:
The thin insulating barrier of preparation on described Semiconductor substrate;
The conducting film of deposition of thin on described thin insulating barrier;
Described thin conductive film is carried out graphical and etching, to form gate electrode; And,
On at least one sidewall of described gate electrode, form the thin insulating barrier of one deck at least.
11. method as claimed in claim 7 is characterized in that, after forming described Schottky or class schottky source and drain electrode, removes unreacted metal from the MOSFET device.
12. method as claimed in claim 7 is characterized in that, described reactions steps is undertaken by thermal annealing.
13. method as claimed in claim 7, it is characterized in that, composition in the group that described source electrode and drain electrode are made of platinum silicide, palladium silicide, silication iridium forms, and the channel dopants in the described Semiconductor substrate is selected from the group that arsenic, phosphorus and antimony constitute.
14. method as claimed in claim 7 is characterized in that, the composition in the group that described source electrode and drain electrode are made of the rare earth silicon Chemistry and Physics Institute forms, and the channel dopants in the described Semiconductor substrate is selected from the group that boron, indium and gallium constitute.
15. method as claimed in claim 7 is characterized in that, forms Schottky or class Schottky contacts in the zone of the raceway groove between contiguous source electrode and drain electrode at least.
16. method as claimed in claim 7 is characterized in that, whole surface of at least one in described source electrode and the described drain electrode and described Semiconductor substrate form Schottky or class Schottky contacts.
17. method as claimed in claim 7 is characterized in that, before the described gate electrode step of preparation, described Semiconductor substrate is introduced alloy.
18. method as claimed in claim 7 is characterized in that, described Semiconductor substrate has marked change in vertical direction and in the substantially invariable channel dopant concentration profile of horizontal direction.
19. a manufacturing is used to regulate the method for the device that flows of electric current, this method comprises:
Be exposed to the Semiconductor substrate in the zone of approaching gate electrode; The local at least isotropic etching of use is etched in the described Semiconductor substrate on the exposed region; And deposition and thermal annealing film metal and described Semiconductor substrate are to form the source electrode or the drain electrode of Schottky or class Schottky.
20. method as claimed in claim 19 is characterized in that, it approximately is that 1/10 to 10 times etching of vertical etch rate is carried out that described etch step is to use lateral etching speed.
21. method as claimed in claim 19 is characterized in that, described etch step be to use have roughly the same laterally and the etching of vertical etch rate carry out.
22. method as claimed in claim 19 is characterized in that, described etch step is to use has that horizontal and the etching of vertical etch rate carry out, so that the channel width of device reduces one of about percentage to 50 percent.
23. method as claimed in claim 19 is characterized in that, described Semiconductor substrate is heated in the process of described deposition step, to promote that metallic atom carries out diffusion into the surface along the surface of described Semiconductor substrate.
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| US51341003P | 2003-10-22 | 2003-10-22 | |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100466264C (en) * | 2004-12-15 | 2009-03-04 | 台湾积体电路制造股份有限公司 | Storage unit and method for forming a storage unit |
| CN102222687A (en) * | 2011-06-23 | 2011-10-19 | 北京大学 | Germanium-based NMOS (N-metal-oxide-semiconductor) device and preparation method thereof |
| CN102227001A (en) * | 2011-06-23 | 2011-10-26 | 北京大学 | Germanium-based NMOS (N-channel metal oxide semiconductor) device and manufacturing method thereof |
| CN108292687A (en) * | 2015-12-24 | 2018-07-17 | 英特尔公司 | Low schottky barrier contact structure for ge nmos |
| CN112397508A (en) * | 2019-08-15 | 2021-02-23 | 长鑫存储技术有限公司 | Memory device, semiconductor structure and manufacturing method thereof |
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2004
- 2004-10-21 CN CN 200480035196 patent/CN1886826A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100466264C (en) * | 2004-12-15 | 2009-03-04 | 台湾积体电路制造股份有限公司 | Storage unit and method for forming a storage unit |
| CN102222687A (en) * | 2011-06-23 | 2011-10-19 | 北京大学 | Germanium-based NMOS (N-metal-oxide-semiconductor) device and preparation method thereof |
| CN102227001A (en) * | 2011-06-23 | 2011-10-26 | 北京大学 | Germanium-based NMOS (N-channel metal oxide semiconductor) device and manufacturing method thereof |
| CN102222687B (en) * | 2011-06-23 | 2012-12-19 | 北京大学 | Germanium-based NMOS (N-metal-oxide-semiconductor) device and preparation method thereof |
| US8865543B2 (en) | 2011-06-23 | 2014-10-21 | Peking University | Ge-based NMOS device and method for fabricating the same |
| CN108292687A (en) * | 2015-12-24 | 2018-07-17 | 英特尔公司 | Low schottky barrier contact structure for ge nmos |
| CN112397508A (en) * | 2019-08-15 | 2021-02-23 | 长鑫存储技术有限公司 | Memory device, semiconductor structure and manufacturing method thereof |
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