CN1889251A - Production of multi-thin film device - Google Patents
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- CN1889251A CN1889251A CN 200510084775 CN200510084775A CN1889251A CN 1889251 A CN1889251 A CN 1889251A CN 200510084775 CN200510084775 CN 200510084775 CN 200510084775 A CN200510084775 A CN 200510084775A CN 1889251 A CN1889251 A CN 1889251A
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Abstract
The present invention refers to method for making plurality of thin-film device. Said method includes roughly making graphics to at least one thin-film material [720-740] on flexibility substrate [710] and forming plurality of thin-film component on flexibility substrate using self-alignment impression lithography (SAIL) technology.
Description
Technical field
Present invention generally relates to field of semiconductor devices, relate to the method and system that is used for making a plurality of thin-film devices more precisely.
Background technology
In semiconductor machining industry, exist scaled existing structure at present and make the more strong trend of minor structure.This process quilt is commonly referred to as little manufacturing.The field that little manufacturing has had great impulsive force is a microelectronic.Exactly, microelectronic structure scaled just making these structures can be cheap more, have higher performance, present that power consumption is fallen and comprise more element in given size.Though littlely be manufactured in the electronics industry very actively, little manufacturing also has been applied to other purposes such as biotechnology, optics, mechanical system, senser element and reactor.
Little manufacturing can be used to make the firm memory of permanent cheapness (PIRM) array.PIRM is a kind of extremely low file store solid-state memory of cost that is used for digital photograph, digital audio and other application.From the viewpoint of making, PIRM comprises a series of semiconductors and other film that is clipped between patterned metal layer at top and the patterned bottom metal layers.Wherein, the infall of these metal levels forms two port devices.Imprint lithography is a kind of manufacture method that is used for making these arrays.
Imprint lithography usually utilizes master with architectural feature to be made and treats contacting between will patterned backing material, with high-resolution the film on the backing material is carried out graphically.Graphical film can be dielectric, semiconductor, metal or organic substance, and can be patterned to film or independently the layer.Imprint lithography is particularly useful in drum-type (roll-to-roll) processing because the optics flatness that has higher productive rate, can handle wide substrate and do not rely on substrate provides high resolution.But the restriction of this method relates to such fact, promptly in order to produce the record (lexicon) of two port devices in the PIRM structure, needs a kind of nearly embossing mask of 7 discontinuous height that has.Therefore, the embossing mask with this height number has applied bigger burden for control, etching and the impression processing of mask.
Therefore, need a kind of method and system that is used for making a plurality of thin-film devices that overcome the above-mentioned problem relevant with the PIRM manufacturing process.The method and system should be simply, cheap, and can be adapted to prior art easily.The invention solves these demands.
Summary of the invention
An aspect of of the present present invention is a kind of method that is used for forming a plurality of thin-film devices.The method comprises with at least a material on the rough mode patterned flex, and forms a plurality of thin-film components with autoregistration imprint lithography (SAIL) technology on flexible substrate.
From in conjunction with following accompanying drawing, illustrate that with method for example in the following detailed description of the principle of the invention, it is obvious that other aspects and advantages of the present invention will become.
Description of drawings
Fig. 1 is the high level flow chart of methods of making semiconductor devices according to an embodiment of the invention.
Fig. 2 shows the plane graph of the patterned main film roughly of determining 3 zones according to an embodiment of the invention.
Fig. 3 shows chip shares that 3 zones consume and aims at and the graphical functional relation of tolerance.
The curve chart of Fig. 4 shows chip upper curtate number, alignment tolerance and can be used for relation between the chip amount of memory.
Fig. 5 is the more detailed flow chart of step 120 of the flow chart of Fig. 1 according to an embodiment of the invention.
Fig. 6 is the explanation of crosspoint element according to an embodiment of the invention.
Fig. 7 shows the perspective view of structure according to an embodiment of the invention.
Fig. 8 shows the technology that is used for making a plurality of thin-film devices according to an embodiment of the invention.
Fig. 8 (a)-8 (g) realizes the structure that obtains in Fig. 8 technical process according to an embodiment of the invention.
Fig. 9 shows the perspective view of structure according to another embodiment of the invention.
Figure 10 shows the technology that is used for making a plurality of thin-film devices according to another embodiment of the invention.
Figure 10 (a)-10 (e) realizes the structure that obtains in Figure 10 technical process according to an embodiment of the invention.
Embodiment
The present invention relates to the method and system that is used for making a plurality of thin-film components.Propose following description,, and provide with the form of patent application and requirement thereof so that a those of ordinary skill in present technique field can utilize the present invention.For those skilled in the art, be conspicuous to the various modifications of each embodiment and General Principle and characteristics described herein.So, the embodiment shown in the present invention is not regarded as being limited to, but with principle described herein and characteristics the most wide consistent scope.
Shown in exemplary drawings, a kind of methods of making semiconductor devices and system of being used for disclosed.The various embodiment of the method and system provides treats the rough graphical step that will use in conjunction with autoregistration imprint lithography (SAIL) technology, so that form a plurality of thin-film components on flexible substrate.Therefore, the complete electricity that has obtained each thin-film component isolate and no matter its structure how.In addition,, can reduce the number of the discontinuous height of relevant embossing mask use significantly, thereby in whole technology, reduce the number of mask control and etching step by means of rough graphical step is provided in conjunction with SAIL technology.
Conventional technology has two major defects that solved by disclosed embodiment.At first, conventional SAIL technology depends on and adopts intrinsic amorphous silicon layer to provide in the PIRM array electricity between the adjacent elements to isolate in diode.If memory cell comprises the metallicity barrier layer, this has just become problem.Adopt disclosed embodiment, the complete electricity that the crosspoint element is provided isolate and no matter the structure of crosspoint element how.
Second shortcoming of common process is that this technological requirement is used plasma enhanced CVD (PECVD) silicon layer on the top of embossing polymer mask.The temperature of this deposit is 250 ℃.Because this high temperature, the mask material that can be used in SAIL technology just is restricted.Utilize disclosed embodiment, can before any embossing lithography is handled, carry out all pecvd processes.Only the top metal deposit of ambient operation is applied to the embossing polymer mask.This makes it possible to use the mask material with low temperature upper limit, and makes it possible to all key stratums of deposit successively and be not exposed to ambient temperature.
Fig. 1 is the high level flow chart of manufacturing method of semiconductor device.First step 110 comprises in rough mode at least a material on the flexible substrate is carried out graphically.In one embodiment, this step comprises graphical several thin layer.Last step 120 comprises uses SAIL technology to form a plurality of thin-film components on flexible substrate.
Though above-mentioned notion disclosed herein is used in conjunction with flexible substrate, should be noted that, also can realize this technology in conjunction with the inflexibility substrate.
Because the layout of PIRM circuit is repetition, so disclosed embodiment is possible.Therefore, in one embodiment, the PIRM circuit can be divided into the repetitive pattern in 3 zones: a zone that only comprises the switching diode memory cell, only have a zone of diode and transit line (crossover), and a zone that only has passage and insulation transit line.If substrate is carried out roughly in advance graphically, thereby figure has then reduced the execution complexity of follow-up SAIL technology significantly corresponding to 3 above-mentioned zones.
Fig. 2 has shown the profile of the structure of the repetitive pattern that shows 3 zones.Structure 200 comprises memory cell areas 210, diode region 220 and channel region 230.Also show bottom metal 240.Channel region 230 only comprises bottom metal 240.Diode region 220 comprises the diode layer on bottom metal 240 tops.In one embodiment, diode layer is a PIN thin film silicon structure.Memory cell areas 210 comprises by the bottom metal 240 of diode layer and switching layer covering.In one embodiment, switching layer is anti-fuse of a kind of amorphous silicon (antifuse) or polymer fuse materials.
Yes should be noted that for Performance And Reliability, each PIRM layer is subdivided into 10-1000 the section that comprises 3 zones 210,220,230.The minimum widith of diode in each section and passage area 220,230 is subjected to rough patterned area and the aiming at and the graphically restriction of tolerance between the polymer mask on these regional tops of embossing subsequently.Fig. 3 shows chip share that these zones consume and aims at and the functional relation of graphical tolerance.As in Fig. 3, seeing, borderline tolerance is ± S/2 between in 3 zones 210,220,230 each, wherein S is total alignment error that all sources cause: the distortion of misalignment, substrate, cross etching/owe etching, overexposure/under-exposure etc., and determined the minimum widith that each is regional.Therefore, if there is any narrowing down in each zone, then passage may become diode, or diode may become memory cell.
In addition, the curve chart of Fig. 4 shows section number, the alignment tolerance on the chip and can be used for relation between the number of chips of memory.Usually, to cause can be used for the chip area of memory littler for bigger section number and worse aligning.For example, if adopt 100 sections (10 row and 10 row), alignment tolerance is ± 50 μ, and then about 30% of 25 * 25mm chip can't be used for memory.For the purpose of present patent application, " patterned roughly " is between the 10-50 micron, and wherein, 25 μ represent to be lost in the active area and the reasonable compromise that provides between the desired technology cost of aiming at of this precision of alignment tolerance.
In one embodiment, step 110 is used and is finished such as the additive process of blocking macking technique (shadowmasking technology) (additive process).Macking technique is blocked in utilization, and the physical mask (block masks) by the flexible membrane such as thin metal foil or plastic sheet is made is directly placed on the substrate.This mask has with material treats to be deposited on the corresponding opening in position on the substrate.In other the zone, block masks has stopped deposition materials physically at all.After using a period of time, must remove the material that accumulates on the mask or mask is abandoned.
In another embodiment, step 110 uses minimizing method (subtractiveprocess) to finish.In the present embodiment, be deposited into continuous cover layer until all device layers of metal layer at top, wherein, finish that with etch process continuous film is patterned into each zone shown in Figure 2.Because each regional size is big relatively, can be used to silk screen printing or drum-type lithography so be used for the mask of etch process.
Though described in conjunction with above-mentioned embodiment and to have added and to reduce technology, person skilled in the art can easily be understood that, the various technology such as ink jet printing also can be used to thin layer is carried out rough graphical.
As mentioned above, autoregistration imprint lithography (SAIL) be a kind of by means of use flexible die (stamp) with 3D polymer mask mold to coated substrate and the film on the backing material is carried out patterned technology with high-resolution.Graphical film can be dielectric, semiconductor, metal or organic substance, and can be patterned to pellicular cascade or discrete layer.Imprint lithography is owing to the substrate that has higher productive rate, can dispose wide substrate and tolerate non-flat forms, so particularly useful in drum-type processing.
Fig. 5 is the more detailed flow chart of the step 120 of Fig. 1 flow chart.First step 121 comprises one or more material layers is deposited on the flexible substrate.In one embodiment, these material layers comprise bottom metal, diode layer and switching layer.Second step 122 is included in and forms three-dimensional (3D) structure on the described material layer.In one embodiment, this three-dimensional structure is the impression polymer, and utilizes impression tool to produce usually.Be called in name in the patent application 10/184587 of " AMethod and System for Forming a Semiconductor Device (be used for methods of making semiconductor devices and system) ", described the method for utilizing impression tool to produce 3-D graphic in material layer, its full content is incorporated herein by reference.Last step 123 comprises that the desired characteristic according to a plurality of thin-film devices carries out graphically at least a material.
In case in the impression polymer, formed 3-D graphic, just can in the making of various semiconductor device, realize the structure that obtains.Therefore, this structure is particularly useful in the formation of cross point memory array.
Crosspoint array
Cross point memory array comprises the quadrature group of two layers of parallel conductor that separates that are arranged with semiconductor layer therebetween.These two groups of conductors form the column electrode and the row electrode of crossovers, make in the column electrode each with the row electrode in each just in time intersect a position.
In order to understand crosspoint array in more detail, referring now to Fig. 6.Fig. 6 is the explanation of an element of crossover point array 600.At each infall, be connected forming between column electrode 610 and the row electrode 620 by semiconductor layer 630, semiconductor layer 630 works in the mode of diode in series and fuse.Diode in the array all is oriented to if apply common potential between all column electrodes and all row electrode, and then all diodes all are biased by identical direction.Fuse element may be implemented as discrete element, and when critical current passes through wherein, fuse element will be opened a way, and maybe can be bonded in the performance of diode.
Those skilled in the art can be understood that easily that above-mentioned crosspoint array can be applied in the formation of the various semiconductor device of resistor, capacitor, diode, fuse, anti-fuse etc.
Fig. 7 shows the perspective view according to the structure of an embodiment.Structure 700 comprises two parts of flexible substrate 710, bottom metal layers 720, diode layer 730, switching layer 740 and embossing three-dimensional polymer mask 750 and 760.Each embossing polymer mask part 750 and 760 combines to produce forming all features that the desired structure of PIRM array needs: the transit line, top metal that does not have the zone of film, patterned bottom metal lines, patterned top metal lines, an insulation is connected (passage), cross-point diode and cross point memory cell to the bottom metal.In addition, can see 5 discrete shoulder heights 761,762,763,764,765.Approach (～100nm) polymer residues 755 may form bridge in the space between two embossing polymer mask parts 750 and 760.And the vertical interval between the adjacent mask aspect is about the 0.5-1.0 micron.
In one embodiment, flexible substrate 710 is polyimide materials.Bottom metal layers 720 can be one or more metal levels or comprise conductive oxide or other conductive material layer of organic material.Diode layer 730 can be the thin film silicon PIN diode.Switching layer 740 can be the anti-fuse of amorphous silicon layer, wherein metal barrier the anti-fuse of amorphous silicon layer and below between the diode.Perhaps, switching layer can be the organic polymer fuse.Embossing polymer mask part 750 and 760 is made by polymeric material of light curable and so on.
Fig. 8 shows the technology according to a plurality of thin-film devices of making of an embodiment.For illustrative purposes, Fig. 8 (a)-8 (g) shows the structure that obtains in realization Fig. 8 technical process.
First step 801 relates to the first that removes three-dimensional structure.This step comprises that any polymer residues of etching and all film are up to substrate.Can adopt wet etching or dry etching herein, as long as film is with significantly etched greater than the speed of polymer mask.Fig. 8 (a) shows the structure that obtains after the execution in step 801.As can be seen, the first of flexible substrate 710 is exposed.
Second step 802 relates to first leveling polymer-coated to three-dimensional structure.The example of leveling polymer is photoresist, UV curable polymer and spin-coating glass.Importantly, the three-dimensional structure and the first leveling polymeric material are selected such that to exist and a kind ofly can keep the impregnable basically etch process of another kind of material simultaneously by every kind of material of etching.In one embodiment, utilize the method such as gravure coating in the drum-type environment, to flatten once more.Gravure coating is widely used in the commercial printing field, and its use has the material layer of the good control that veined cylinder will approach to transfer to flexible fabric.
Third step 803 comprises removes the part first leveling polymer.Fig. 8 (b) shows the structure that comprises the first leveling polymer remainder 770.In one embodiment, use the dry method etch technology such as reactive ion etching (RIE) or ion grinding (ion-milling) to remove the first leveling polymer, thereby this etching is optionally with respect to the three-dimensional polymer structure.
In RIE technology, substrate is placed in the reactor of wherein introducing several gases.In admixture of gas, clash into plasma with the RF power supply, gas molecule is divided into ion and active particle.Ion and active particle and etched material surface react, and form another kind of gaseous material.Here it is the etched chemical part of RIE.Also exist one in nature similar in appearance to the physical piece of sputtering deposit technology.
If ion has sufficiently high energy, then they can hit atom and wait to want etched material and do not have chemical reaction.Owing to exist many parameters that need adjustment, be a very complicated task so want the dry method etch technology of balance expansion chemistry and physical etch.Because chemical part is isotropic and physical piece is highly anisotropic, so, might influence etched anisotropy by means of this balance of change.Therefore, RIE can carry out very directive etching.
It is a kind of physical dry etching technique that ion grinds, and wherein, sample is exposed to the collimatied beam of inert ion of the single energy of acceleration, thereby by the ionic cleaning material.The ion grinding system is usually in conjunction with about 200V is provided the Kaufman type double grid ion source to the 1.5kV accelerating voltage.Usually the argon gas of (p～2E-4 Torr) is as working gas.Sample is installed on the rotation water-cooled platform that can tilt with respect to the incident argon ion.
Ion grinds and is used to make submicron grating and is used for constructing the sample that combines such as the very different material of metal/insulator/semiconductor-combination, this is because the etch-rate of these materials (for example has analogous magnitude, for the 500eV-Ar ion, GaAs is 80nm/min, Au is 75nm/min, silicon nitride is 25nm/min, and photoresist is about 20nm/min).Therefore, a kind of instrument very flexibly that is used for carrying out directional etch that provides is provided ion.
Grind and RI E etch process though described ion in conjunction with above-mentioned embodiment, those skilled in the art can easily be understood that, can adopt various etch process in essence of the present invention and scope.
The 4th step 804 comprises the second portion of removing three-dimensional structure.Remove a shoulder height from three-dimensional structure herein.Fig. 8 (C) shows the structure after three- dimensional structure 750 and 760 is removed another shoulder height.The surface that exposes can be bottom metal layers, diode layer or switching layer, and this depends on the rough graphical of three-dimensional structure below.In one embodiment, this etching step has the selectivity of removing the embossing polymer but not removing the first leveling polymer.
Should be noted that, be under the situation of conducting polymer fuse at switching layer, and switching layer may need to protect with non-organic barrier layer, so that prevent in the switching layer etch process formerly etched.In the case, in technology this of non-organic barrier layer is constantly etched.If metal barrier is used in combination with the switching layer that amorphous silicon is made, then this step is optional.
The 5th step 805 comprises the remainder that metal layer at top is coated to structure.Fig. 8 (d) shows the structure after the coating metal layer at top 780.Similar to bottom metal layers, metal layer at top 880 is one or more metal levels, organic matter layer, dielectric layer or semiconductor layer.
Next step 806 comprises second leveling polymer-coated to metal layer at top.The type of this polymer can be same with the first leveling polymer phase, maybe can adopt different polymer.Next step 807 comprises the first that removes the second leveling polymer, thus the first of exposed tops metal level.Fig. 8 (e) shows the structure of the expose portion that comprises the second leveling remainder of polymer 790 and metal layer at top 780.In one embodiment, use the dry process such as RIE or ion grinding to remove the second leveling polymer, thereby this etching is optionally with respect to metal layer at top.
Next step 808 comprises the second portion of removing the second leveling polymer, thus another part of exposed tops metal.Fig. 8 (f) shows the structure of another expose portion that comprises the second leveling remainder of polymer 790 and metal layer at top 780.As can seeing among Fig. 8 (f), the part of switching layer 720 also is exposed.
Next step 809 comprises from the sidewall of the second leveling polymer removes any metal.In one embodiment, this etching step has the selectivity of removing metal layer at top but not removing the second leveling polymer or substrate.
Last step 810 comprises the remainder of removing the second leveling polymer.Fig. 8 (g) shows the structure of the complete documentation that comprises the thin-film component that is used for making the PIRM array: only top metal, passage, cross-point diode, cross point memory cell, transit line (being isolated by the electrical connection that the embossing polymer provides), only bottom metal and the substrate that exposes.Should be noted that though transit line is shown on the zone with memory cell, transit line also can just in time be deposited on the zone that diode is only arranged or only have on the zone of bottom metal.
Fig. 9 shows the perspective view according to the structure of another embodiment.Structure 900 comprises two parts 950 and 960 of flexible substrate 910, bottom metal layers 920, diode layer 930, switching layer 940 and embossing three-dimensional polymer mask.Each embossing polymer mask part 950 and 960 combines all features that to form the desired structure of PIRM array and need in order to produce: the transit line, top metal that does not have the zone of film, patterned bottom metal lines, patterned top metal lines, an insulation is connected (passage), cross-point diode and cross point memory cell to the bottom metal.
In addition, can see 7 discontinuous shoulder heights 961,962,963,964,965,966,967.Approach (～100nm) polymer residues 955 may form bridge in the space between two embossing polymer mask parts 950 and 960.And the vertical interval between the adjacent mask aspect is about the 0.5-1.0 micron.
Similar in appearance to above-mentioned embodiment, flexible substrate 910 is polyimide materials.Bottom metal layers 920 can be one or more metal levels or comprise conductive oxide or other conductive material layer of organic material.Diode layer 930 can be the thin film silicon PIN diode.Switching layer 940 can be the anti-fuse of amorphous silicon layer, wherein metal barrier the anti-fuse of amorphous silicon layer and below between the diode.Perhaps, switching layer can be the organic polymer fuse.Embossing polymer mask part 950 and 960 is made by the polymeric material or the similar material of light curable.
Figure 10 shows the technology according to a plurality of thin-film devices of making of an embodiment.For illustrative purposes, Figure 10 (a)-10 (e) shows the structure that obtains in realization Figure 10 technical process.
The 4th step 1004 comprises the third part of removing three-dimensional structure.Removed another shoulder height from three-dimensional structure herein.Figure 10 (d) shows the structure after three- dimensional structure 950 and 960 has been removed another shoulder height.The surface that exposes is a diode layer 930.In one embodiment, this etching step is anisotropic, and has the selectivity of removing the embossing polymer but not removing the first leveling polymer.
The 5th step 1005 comprises the 4th part of removing three-dimensional structure.Removed another shoulder height from three-dimensional structure herein.Figure 10 (e) shows the structure after three- dimensional structure 950 and 960 has been removed another shoulder height.The surface of Bao Luing is a switching layer 940 herein.In one embodiment, this etching step is anisotropic, and has the selectivity of removing the embossing polymer but not removing the first leveling polymer.Remaining step has been used for reference processing step 805-810 shown in Figure 8 in this technology.
The various embodiments of the method and system provide will be in conjunction with the rough graphical step of autoregistration imprint lithography (SAIL) technology use, so that form a plurality of thin-film components on flexible substrate.Therefore, the complete electricity that has obtained thin-film component isolate and no matter its structure how.In addition,, the number of the discontinuous height that relevant embossing mask uses be can reduce significantly, thereby the mask control in the whole technology and the number of etching step reduced by rough graphical step is provided in conjunction with SAIL technology.
Need not further analyze, the front has manifested purport of the present invention so fully, to such an extent as to viewpoint from prior art, other people can utilize existing knowledge easily to be applied to various uses and not ignore these characteristics, constitute the key property of ordinary circumstance of the present invention or concrete condition well.Therefore, these application should and intention be contemplated as falling with in the implication and scope of equivalent of following claim.Though with regard to some embodiment, described the present invention, are conspicuous other embodiments for present technique field those skilled in the art, also in scope of the present invention defined by the following claims.
Claims (10)
1. method that is used for forming a plurality of thin-film components, it comprises:
At least a thin-film material [720-740] on the flexible substrate [710] is carried out graphically roughly; And
Go up a plurality of thin-film components of formation with autoregistration imprint lithography (SAIL) technology in flexible substrate [710].
2. the process of claim 1 wherein that [720-740] graphically comprises roughly at least a thin-film material:
With additive process at least a thin-film material [720-740] is carried out graphically.
3. the process of claim 1 wherein that [720-740] graphically comprises roughly at least a thin-film material:
With the minimizing method at least a thin-film material [720-740] is carried out graphically.
4. the process of claim 1 wherein, go up a plurality of thin-film components of formation with autoregistration imprint lithography (SAIL) technology in flexible substrate [710] and comprise:
Go up at least a material of deposit [720-740] in flexible substrate [710];
Go up formation three-dimensional structure [750] at described at least a material [720-740]; And
According to the desired characteristic of a plurality of thin-film components, at least a material is carried out graphically.
5. the process of claim 1 wherein, go up a plurality of thin-film components of formation with autoregistration imprint lithography (SAIL) technology in flexible substrate [710] and comprise:
Deposit leveling material [770].
6. system that is used for forming a plurality of thin-film components, it comprises:
Be used at least a film [720-740] on the flexible substrate [710] is carried out patterned device roughly;
Form the device of a plurality of thin-film components with SAIL technology.
7. the system of claim 6, wherein, described a plurality of thin-film components comprise the PIRM array.
8. the system of claim 7 wherein, is used for that at least a film [720-740] is carried out patterned device roughly and relates to:
With blocking macking technique, at least a film [720-740] is carried out patterned device in rough mode.
9. the system of claim 7 wherein, is used for that at least a film [720-740] is carried out patterned device roughly and comprises:
Use photoetching technique, at least a film [720-740] is carried out patterned device in rough mode.
10. the system of claim 7, wherein, the device that forms a plurality of thin-film components with SAIL technology comprises:
Be used for going up the device of at least a material of deposit [720-740] in flexible substrate [710];
Be used for going up the device that forms three-dimensional structure [750] at least a material [720-740]; And
Be used for desired characteristic according to a plurality of thin-film components, [720-740] carries out patterned device at least a material.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102336394A (en) * | 2011-10-26 | 2012-02-01 | 清华大学 | Method for manufacturing flexible micro electro mechanical system (MEMS) resistance reducing covering |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102336394A (en) * | 2011-10-26 | 2012-02-01 | 清华大学 | Method for manufacturing flexible micro electro mechanical system (MEMS) resistance reducing covering |
| CN102336394B (en) * | 2011-10-26 | 2014-05-28 | 清华大学 | Method for manufacturing flexible micro electro mechanical system (MEMS) resistance reducing covering |
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