CN1890784B - 应变半导体衬底及其制法 - Google Patents

应变半导体衬底及其制法 Download PDF

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CN1890784B
CN1890784B CN2004800358158A CN200480035815A CN1890784B CN 1890784 B CN1890784 B CN 1890784B CN 2004800358158 A CN2004800358158 A CN 2004800358158A CN 200480035815 A CN200480035815 A CN 200480035815A CN 1890784 B CN1890784 B CN 1890784B
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silicon
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M·M·佩莱拉
S·S·千
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GlobalFoundries Inc
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Abstract

一种利用应变硅(SMOS)衬底(20)的集成电路制造方法。该衬底(20)利用于基层中的沟槽(36)以诱发层中的应力。该衬底可包括硅。该沟槽(36)于主要衬底之后侧或绝缘层上覆半导体晶圆上形成有多个柱状体(35)。

Description

应变半导体衬底及其制法
技术领域
本发明系有关于集成电路衬底或晶圆以及制造该集成电路衬底或晶圆的制法。更具体而言，本发明系有关于一种在衬底上形成应变半导体结构(strained semiconductor structure)的方法以及一种应变半导体结构或层。
背景技术
利用应变金属氧化物半导体(Strained metal oxide semiconductor；SMOS)制法以透过增加硅的载子移动率(carrier mobility)而增加晶体管(MOSFET)的效能，从而降低电阻与功率的消耗并提高驱动电流、频率响应(frequency response)以及工作速度。应变硅(strained silicon)典型的透过于硅锗(silicon germanium)衬底或层上成长硅层予以形成。
与该硅锗衬底相结合的硅锗栅(silicon germanium lattice)格通常较纯硅栅格之间隔为宽，随着锗所占的百分比愈高该栅格间隔愈宽。由于该硅栅格系与该间隔较大的硅锗栅格排列成一直线，因此会于该硅层产生张力应变(tensile strain)。实质上该硅原子相互间会被扯断。
舒松硅具有包含六个等价能带(equal valence bands)的导电能带。施加至该硅的张力应变导致其中四个电子价能带的能量(energy)会提高而另二个电子价能带的能量会降低。由于量子效应(quantum effects)，当通过该较低能量的能带时电子的有效估量的电子会减少百分的三十。因此，该较低能量的能带提供电子流较低的电阻。此外，电子遇到来自该硅原子的原子核的较低的振动能时，会导致电子以较舒松的硅低500至1000倍的速率扩散。据此，于应变硅中的载子移动率会相较于舒松的硅中更急剧的提高，使电子移动率提高百分的八十或更高，而使电洞提高百分的二十或更高的移动率。移动率的提高已发现会将电场持续提升至1.5百万伏特/公分。且相信这些因素会致使装置速度在未进一步减少装置的尺寸的情况下提高百分的三十五，或于不降低效能的情况下降低百分的二十五的功率消耗。
习知的绝缘层上覆半导体(semiconductor-on-insulator，SOI)衬底已包括应变硅层，该应变硅层系形成于掩埋氧化物层(buried oxide layer)的上，而该掩埋氧化物层则形成于基层上。该掩埋氧化物层可透过包括沉积氧于该基层上或于该基层掺杂氧等不同的制程予以形成。该应变半导体层可透过提供具有组成物(Si(1-x)Gex)的硅锗层，其中该x大约为0.2，更广泛而言系在0.1至0.3的范围内。该硅锗层可利用硅烷(silane)与锗烷(germane)透过化学气相沉积方式予以沉积。当沉积开始时可降低锗烷的浓度致使该硅锗层的最上层主要部份大部分或全部均为硅。
于SMOS制程中使用锗会导致该集成电路衬底、层以及设备产生锗污染的问题。尤其是锗的放气作用(outgassing)或向外扩散作用(outdiffusion)会污染与该制造设备相关联的多种组件以及与该加工晶圆相关联的集成电路结构。再且，锗的放气作用会对于薄膜的形成产生不利的影响。再者，锗的向外扩散会导致于衬里(liner)的界面产生锗累积或堆积，进而导致该浅沟槽绝缘(shallow trench isolation)结构的信赖性问题。
锗的放气作用的问题于非常高温以及与该浅沟槽绝缘结构的衬里相关联的HCI(盐酸)周围环境中特别显著。举例而言，习知的浅沟槽绝缘衬里氧化物制程系利用大约摄氏1000度的温度因而增加锗的放气作用。
因此，需要一种无需利用锗即可形成的应变半导体结构。其次，亦需要一种用以形成高品质SMOS衬底的制法。再者，复需要一种不要求应变层沉积的SMOS晶圆形成制法。此外，需要一种不易受锗的放气作用影响的衬底。另外，复需要一种形成应变半导体层的新颖制法。再者，尚需要一种增强及/或增加层应变特性的寿命的晶圆制法。
发明内容
以下之一实施例系有关于一种制造集成电路衬底的方法。该集成电路衬底包括应变层。该方法包括提供基层，于该基层上提供绝缘层以及于该绝缘层上提供半导体层。该方法复包括于该基层内形成多个柱状体(pillars)。
另一实施例系有关于一种于该基层上形成应变半导体层的方法。该方法包括于该基层蚀刻沟槽以及于该沟槽中提供具有压缩力的材料。
又一实施例系有关于一种衬底。该衬底包括应变层以及形成于该应变层下的基层。该基层于相对该应变层的丨侧具有沟槽。该沟槽降低该应变层中的应力。
附图说明
透过前述伴随所附图式的详细说明将能够更完全的了解该些实施例，其中相同的组件符号系表示相同的组件，该些图式包括：
图1系为依据一实施例的包括应变半导体层、氧化物层与基层的衬底的部份的断面示意图；
图2系为图1中所示的部分的断面图，用以显示蚀刻步骤；
图3系为图2中所示的部分的断面图，用以显示沉积步骤；
图4系为图1中所示的部分的底面图；
图5系为依据本发明的另一实施例的衬底的另一部分的底面示意图；
图6系为依据本发明的另一实施例的衬底的又一部分的底面示意图；
图7系为用以制造图1中所示的部分的治法的基本流程图；以及
图8系为图1中所示的部分的断面图，用以显示附属于该衬底的机械压缩系统。
具体实施方式
图1至图8显示衬底以及用以提供如应变硅层的应变半导体层的制法。该结构与制法可在不需要锗掺杂或伴随着锗掺杂的情况下予以利用。
请参阅图1，集成电路的部分20可为晶圆或如绝缘层上覆半导体衬底等衬底的部分，该部分20可于制法100(图7)中予以形成且其较佳的用于应变金属氧化物半导体(SMOS)的应用。
部分20包括由应变层50、掩埋氧化物层40以及基层30所组成的衬底。层50可包括锗或设在包括锗在内的多层结构。此外，于该层30下可提供支撑衬底。
于一实施例中，基层30系为单晶硅层。层30的厚度可为400至1000微米(μm)间。掩埋氧化物层40可为二氧化硅层。层40的厚度可为500至2000埃()间。应变层50较佳的为硅或硅/锗(其中锗可占百分的十至三十)化。层50的厚度可为500埃。
层50较佳为由于沟槽36的集合32(显示于图2中)包括具有压缩力的材料34而低于张应力(tensile stress)者。于一实施例中，沟槽36的集合32可为挖空结构(empty)且因为与该沟槽相关联的材料的缺少而导致张应力较于层50中的张应力为小。较佳者，沟槽36的集合32可用具有压缩力的材料34填充，该材料34可例如为等离子体增强化学气相沉积(plasma enhanced CVD，PECVD)氮化硅(SiN)材料、金属、或其它于沉积在沟槽36的集合32时或沉积在沟槽36的集合32后变成被压缩的材料。若于沟槽36中需要张应力，则可利用热成型氮化硅材料或低应力化学气相沉积(LPCVD)氮化硅材料以取代会导致压缩应力的等离子增强化学气相沉积氮化硅材料。
于层30上的压缩应力透过层40转换为层50的张应力。部份20的压缩层30拉伸层40与50。于可替换的实施例中，层40并不存在而层50则直接形成于层30的上。于另一实施例中，层30可作为整个主要衬底，且该主要衬底的上表面系用作为作用区(active region)。由于与沟槽36的集合32相关联的下表面所形成的压缩张力的故因此该上表面系承受张应力。
于一实施例中，沟槽36的集合32系相应于层50中作用区的尺寸。于一实施例中，用于定义于层50上的作用区的相同屏蔽可用以定义沟槽36的集合32。部份的沟槽36可大于其它的沟槽。举例而言，于特定位置的小沟槽是保持该整体晶圆的完整性所必要。
具有压缩力的材料34较佳的自该层30的下表面向层40方向延伸大约700埃。于一实施例中，沟槽36的集合32一直延伸至层40(亦即沟槽36达到层40的下表面)。于另一实施例中，沟槽36延伸至该层30的百分的七十五的深度。较佳的，沟槽36具有500至700微米的深度。较佳的，层40、层50以及层30于沟槽36的集合32形成之前已存在于部份20。
较佳的，沟槽36具有500至2000埃的宽度以及数微米(μm)的长度。沟槽36的集合32得具有锥状外形。举例而言，沟槽36具有梯形断面外形且较窄的部分则系接近层40。柱状体35的集合33系形成于沟槽32间，柱状体35较佳的可具有略大于该沟槽36的宽度的宽度。该柱状体35复可具有略长于或等于该沟槽36的长度的长度。
请一并参阅图7与图1至图3，部分20的形成系揭露于下。于图2中，沟槽36的集合32以光微影(photolithographic)程序予以蚀刻。垫氧化物层(pad oxide)以及氮化硅硬屏蔽可用以形成该沟槽36。
可利用作用层(active layer)光微影屏蔽定义出沟槽36。对应于层50上的隔离沟槽的该作用层光微影屏蔽的区域系对应于该集成电路晶圆后侧上的沟槽36的部分。
沟槽36较佳为于干式蚀刻程序中选择性的蚀刻与该层40的材料(二氧化硅)相关的层30(硅)。沟槽36的集合32系于该集成电路晶圆的层30之后侧中予以蚀刻。此外，该蚀刻程序可达到层40并停止于层40。亦可利用其它可替代的沟槽形成程序以形成沟槽36。
沟槽36的集合32的形成于层30中留下柱状体35的集合33。柱状结构35系于层50与40形成于层30上后予以形成。柱状结构35的材料较佳的与层30(亦即硅)的材料相同。
请参阅图3，于制法100中的步骤104中具有压缩力的材料38填充于沟槽36中(显示于图2)。较佳的，具有压缩力的材料，如包括氮化硅(silicon nitride)的具有压缩力的材料填充于沟槽36中接着收缩以拉出与该沟槽36对向相连结的柱状体35。该具有压缩力的材料于层40中产生压缩应力并提供张应力于其上的层40与50。
材料38可为具有压缩力的材料或氮化物材料。于一实施例中，材料38系为等离子体增强化学气相沉积氮化硅材料。
材料38可于如等离子体增强化学气相沉积或喷溅(sputter)沉积等保形层沉积的程序中予以形成。材料38较佳为具有大于或等于该沟槽36的丨半或250至1000埃，或于一较佳实施例中具有更厚的厚度。于氮化硅的情况中，材料38的沉积参数系为利用10至1000毫托耳(milliTorr)的压力、10至1000的射频功率以及摄氏100至500度的温度的硅甲烷(SiH4)+氨(NH3)+氮(N2)。较佳的，该材料38于沉积后自然的压缩。
请参阅图1，材料38(显示于图3中)于制法100的步骤106中予以平整化以留下介于与该沟槽36的集合32相连结的柱状结构35的集合33间的材料34。材料38可于化学机械研磨程序或其它蚀刻程序中予以平整化。
请参阅图4，沟槽36的集合32可具有长方形之外形。依据于图5中的另一实施例，包括材料34的沟槽36具有纵横比(aspect ratio)相对接近于一的正方形或长方形之外形。于另一实施例中，如图6中所提供的该材料34的图案系随着该层30的侧面与顶面形成一角度。
于一实施例中，包括材料34的沟槽36的集合系呈现格子饼(Waffle)图案。如前述伴随图1的说明，沟槽36的集合32可包括不同尺寸的沟槽。于层30中的部份沟槽与柱状结构可依据设计标准小于或大于其它的沟槽与柱状结构。举例而言，集成电路晶圆为了完整性而于晶圆的某些部份会要求较高的强度并于特定的区域具有较小的沟槽。此外，于图4至图6中所示为沟槽36(材料34)所保留的位置的图案将依据柱状体35的位置而改变。
请参阅图8，针对额外的压缩应力提供机械系统予部分20。于此实施例中，沟槽36可形成净空或填充有材料34。系统38可为弹簧或弹夹。于一实施例中，所提供的系统58系作为集成电路封装建之一部分并用以包覆部分20。
于另一实施例中，材料38可为低热阻力的材料以增加由该部分20所产生的热对流。低热阻力材料可包括硅及/或金属。
应了解者系用以说明本发明的实施例所揭露的详细图标、特定实施例以及具体的数值仅系作为说明的用。该沟槽与柱状结构的图案、形状以及尺寸并不限定于特定的态样。本发明的方法以及装置并不限定于所揭露的精确细节与条件。在不脱离后续本发明的权利要求书的精神之前提下可就所揭露的细节予以变化。

Claims (8)

1.一种制造包含应变层的集成电路衬底的方法，该应变层包含硅或硅/锗，该方法包括：
提供基层，其为单晶硅层；
于该基层上提供半导体层；以及
于该基层的底部形成多个柱状体以诱发该半导体层的作用区中的应变，其中，该半导体层为该应变层，该多个柱状体的间距为500至2000埃，以及该多个柱状体的各者均具有2000-3000埃的宽度和500-700微米的长度。
2.如权利要求1所述的方法，进一步包括于与该柱状体相关联的孔洞中提供具有压缩力的材料。
3.如权利要求2所述的方法，进一步包括平整化该具有压缩力的材料直至到达该基层为止。
4.如权利要求2或3所述的方法，其中该具有压缩力的材料包括由等离子体增强化学气相沉积所沉积的氮化物。
5.一种衬底，包含：
应变层，其包含硅或硅/锗；以及
于该应变层下且于相对形成该应变层的第一侧的第二侧具有沟槽的单晶硅层，该沟槽于该应变层的作用区中诱发应力，并具有2000-3000埃的间距，且该沟槽具有500-2000埃的宽度和500-700微米的深度。
6.如权利要求5所述的衬底，进一步包含配置于该沟槽中的具有压缩力的材料。
7.如权利要求5或6所述的衬底，进一步包含介于该单晶硅层与应变层间的掩埋氧化物层。
8.一种包含于单晶硅层上的应变半导体层的衬底，该应变层包含硅或硅/锗，该衬底由包括下述的方法制造：
于该单晶硅层中蚀刻多个沟槽，该多个沟槽的间距为2000-3000埃，且该多个沟槽的各者均具有500-2000埃的宽度和500-700微米的深度；以及
于该沟槽中提供具有压缩力的材料以诱发该应变半导体层的作用区中的应变。
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