CN1930554A - 具有可编程巷宽的存储器集线器结构 - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G06F13/14—Handling requests for interconnection or transfer
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1678—Details of memory controller using bus width
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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Abstract
一种基于处理器的系统,该系统包括通过处理器总线连接到系统控制器的处理器。该系统控制器用于将至少一个输入设备、至少一个输出设备和至少一个数据存储设备连接到处理器上。连接到至少一个存储器模块上的存储器集线器控制器也连接在处理器总线上,所述至少一个存储器模块具有多个连接到存储器集线器的存储设备。存储器集线器通过下游总线和上游总线连接到存储器集线器控制器。下游总线的宽度为M比特,上游总线的宽度为N比特。虽然M与N的和是固定的,但在基于处理器的系统的运行期间可调节M和N的初始值,以调节下游总线和上游总线的带宽。
Description
相关申请的交叉引用
本申请要求了2004年3月8日提交的,题为“具有可编程巷宽的存储器集线器结构”的美国专利申请No.10/797,727的优先权,并在引入该申请作为参考。
发明领域
本发明涉及具有系统存储器的基于处理器的系统,更具体地,涉及具有包含存储器集线器的存储器模块的基于处理器的系统,其中的存储器集线器通过存储器集线器控制器经由下游总线和上游总线连接到处理器上。
背景技术
诸如计算机系统之类的基于处理器的系统采用存储器设备,例如动态随机存取存储器(“DRAM”)器件,作为系统存储器来存储处理器所访问的指令和数据。在典型的计算机系统中,处理器通过处理器总线和存储器控制器与系统存储器进行通信。处理器发出包括存储器命令(例如读出命令)在内的存储器请求和指明数据或指令将要写入或读出的地址。存储器控制器使用该命令和地址来产生应用于系统存储器的适当的命令信号以及行和列地址。响应该命令和地址,将数据在系统存储器和处理器之间进行传送。存储器控制器通常是系统控制器的一部分,其也包括用于将处理器总线连接到扩展总线的总线桥电路,例如PCI总线。
尽管存储器设备的运行速度已连续增长,但运行速度的增长并没有跟上处理器运行速度的增长。更慢的是存储器命令、地址和数据可耦合在处理器与存储器设备之间的速度的增长。存储器控制器和存储器设备的相对慢的速度限制了处理器与存储器设备之间的数据带宽。
一种增加来往于存储器设备的数据带宽的方法是使用如图1所示的通过存储器集线器连接到处理器的多存储器设备。采用存储器集线器结构的计算机系统100包括用于执行各种计算功能的处理器104,例如执行专用软件来进行专用计算或任务。处理器104包括处理器总线106,处理器总线106通常包括地址总线、控制总线和数据总线。处理器总线106典型地连接到高速缓冲存储器108,高速缓冲存储器108通常为静态随机存取器(“SRAM”)。最后,处理器总线106连接到系统控制器110,有时系统控制器110也称作总线桥。
系统控制器110包含连接到处理器104的存储器集线器控制器128。存储器集线器控制器128还通过总线系统134连接到几个存储器模块130a-n上。存储器模块130a-n中的每一个都包括通过命令、地址和数据总线连接到几个存储器设备148上的存储器集线器140,这些总线共同示为总线150。存储器集线器140有效地在控制器128和存储器设备148之间发送存储器请求和响应。由于处理器104可以访问存储器模块130a-n中的一个,而同时存储器模块130a-n中的另一个正在响应在前的存储器访问,因此采用上述结构的计算机系统可具有更高的带宽。例如,处理器104可将写入数据输出给系统中存储器模块130a-n中的一个,而同时系统中存储器模块130a-n中的另一个正准备将读出数据提供给处理器140。采用存储器集线器结构的计算机系统的运行效率可更实际地大幅度增加存储器系统的数据带宽。存储器集线器结构还可以大大提高计算机系统的存储容量。
系统控制器110还用作各种其他部件通往处理器104的通信路径。更具体地,系统控制器110包括典型地连接到图形控制器112的图形端口,图形控制器112再连接到视频终端114上。系统控制器110还连接到一个或多个诸如键盘或鼠标之类的输入设备118,从而允许操作者与计算机系统100进行交互。典型地,计算机系统100还包括通过系统控制器110连接到处理器104的一个或多个输出设备120,例如打印机。典型地,还将一个或多个数据存储设备124通过系统控制器110连接到处理器104上,从而允许处理器104从内部或外部存储介质(未示出)存储数据或检索数据。典型的存储设备124的示例包括硬盘和软盘、盒式磁带以及光盘只读存储器(CD-ROM)。
由于总线系统134的点到点特性允许更快的电信号发送,以及由于DRAM的隔离特性允许在几个模块中并行或重叠作业,因此存储器集线器结构可大大增加从存储器存储或检索数据的速率。实际上,使用几个存储器模块的存储器系统可以共同以如此高的速度发送和接收数据,从而使总线系统134可以成为限制存储器系统数据带宽的“瓶颈”,其中存储器模块的每一个都包含存储器集线器。
使得采用存储器集线器结构的存储器系统的数据带宽最大化的一种技术是使用高速“下游”总线154以及与下游总线154分开的“上游”总线156实现总线系统134。下游总线154和上游总线具有相同宽度,即导线数量。高速下游总线154将包含存储器命令、地址和写入数据的数据包从存储器集线器控制器128耦合到存储器模块130,并从存储器模块130耦合到更加远离存储器集线器控制器128的存储器模块130上。高速上游总线156将包含读出数据和标识符的数据包从存储器模块130耦合到存储器集线器控制器128,并从存储器模块130耦合到更接近存储器集线器控制器128的存储器模块130。使用两种不同的单方向总线的优点在于消除了周转延迟,并允许存储器集线器控制器同时传送和接收数据。
也可以使用不同类型的存储器信令协议来最大化采用存储器集线器结构的存储器系统的数据带宽。除了使用传统的地址、数据和控制总线,每个存储器请求或“事务”的地址、数据和控制位在单独的数据包中一起发送。该数据包包括命令头,命令头之后跟随着读出或写入数据。命令头包括对应于诸如写入或读出命令之类的存储器命令的位、指定该请求所指向的存储器模块的识别位、以及指定该请求所访问的特定存储器模块中的存储器设备148的地址的地址位。命令头还指定了跟随在命令头之后的读出或写入数据的数量。分组存储器系统的使用允许存储器集线器控制器128通过简单地发送数据包来发出存储器请求,替代了发送由命令、地址以及在写入请求情况下的写入数据信号组成的序列。因此,存储器集线控制器128以更快的速度发出存储器请求。此外,分组存储器系统使存储器集线器控制器128不必留意每个存储器请求的处理细节。取而代之的是,存储器集线器控制器128只需要传送数据包。存储器请求所指向的存储器模块130中的存储器集线器则直接处理存储器请求,而无需进一步与存储器集线器控制器128相互作用。在读出请求的情况下,存储器集线器140将数据包直接或通过介于其间的存储器模块130传回存储器集线器控制器128,该数据包中含有读出数据以及命令头中用来识别读出数据的标识位。存储器集线器控制器128使用标识位将读出数据与特定的存储器请求联系起来。
尽管图1所示的存储器集线器结构可以使处理器104与存储器设备148之间的数据带宽具有显著的增长,但它仍然不能提供最佳性能。特别是,下游总线154或上游总线156的容量会限制数据包进入或输出存储器模块130的速率,从而限制数据带宽。通常,变得超负荷的特定总线154、156取决于存储器访问的性质。由此使得,通过下游总线154的存储器写入的流量要比通过上游总线156的流量多很多。存储器读出仍需要通过下游总线154来耦合包含命令和地址的数据包,但存储器读出通常会导致通过上游总线156的更多的流量。因此,主要由写入构成的存储器访问趋向于使下游总线154超负荷,而主要由读出构成的存储器访问趋向于使上游总线156超负荷。在任何一种情况下,结果都是在处理器104和存储器设备148之间降低数据带宽。
因此,需要一种存储器集线器结构可以进一步避免连接在存储器集线器控制器与一个或多个存储器集线器之间的下游总线或上游总线超负荷。
发明内容
一种可在基于处理器的系统中使用的存储器系统,其包括连接到至少一个具有存储器集线器的存储器模块的存储器集线器控制器,以及连接到所述存储器集线器的多个存储设备。命令、地址和数据信号通过具有第一容量的通信通道从所述存储器集线器控制器耦合到所述存储器集线器,数据信号通过具有第二容量的通信通道从所述存储器集线器耦合到所述存储器集线器控制器。尽管所述第一容量与所述第二容量之和是固定值,但在所述存储器系统的运行过程中可改变所述第一和第二容量各自的值,例如当初始化所述存储器系统时,取决于通过所述通信通道的实际的或预期的信号流量。如果从存储器集线器控制器到存储器集线器的实际或预期的信号流量的量增加,可增加第一容量,并减少第二容量。如果从存储器集线器到存储器集线器控制器的实际或预期的信号流量的量增加,可增加第二容量,并减少第一容量。
附图简述
图1是具有采用传统存储器集线器结构的系统存储器的基于处理器的系统的结构图;
图2是具有采用根据本发明实施例的存储器集线器结构的系统存储器的基于处理器的系统的结构图。
具体实施方式
图2示出了根据本发明一个实施例的基于处理器的系统200。系统200使用与图1中的系统100所使用部件的大部分相同部件,并且它们以相同的方式运行。因此,为了简洁,使用相同的参考数字来表示这些部件并不再对它们的运行进行重复解释。基于处理器的系统200不同于图1所示的系统100之处在于下游总线154和上游总线156的宽度不是固定的,它们也不需要彼此相等。取而代之的是,下游总线154的宽度为M比特,上游总线156的宽度为N比特,其中M与N的和等于固定值。M和N的值是动态的,优选地取决于实际或预期的存储器访问的性质。如果发生或将要进行不相称的大量数据的写入,则增大M的值以增加下游总线154的容量,并相应减小N的值以减少上游总线156的容量。如果发生或将要进行不相称的大量数据的读出,则减小M的值以减少下游总线154的容量,并相应增大N的值以增加上游总线156的容量。
相对于上游总线156的容量N的下游总线154的容量M可以使用各种技术来确定。通过手动操作硬件跳线等选择M和N的值,能够以半永久的方式手动地配置系统200。在这种情况下,可在系统设计期间根据系统200预期的使用来确定M和N的值。然而,除了是静态的之外,M和N的值优选的是动态的,即其在系统200的运行期间是可变的。M和N的值可根据流经总线154、156的实际流量或者将要流经总线154、156的预期流量而动态地改变。可选择地,M和N值可在存储器系统运行期间的其他时间进行改变,例如在对存储器系统进行初始化的时候。
如果将实际的流量用作调节M和N的基准,可通过存储器集线器控制器128和存储器集线器140来确定流经总线154、156的流量,存储器集线器控制器128和存储器集线器140随后可通过将连接到总线154、156中的信号线的内部缓冲器配置为输入缓冲器或输出缓冲器来调整M和N。作为可选的,可以仅仅通过存储器集线器控制器128来确定流经总线154、156的流量,存储器集线器控制器128能够将配置数据耦合到存储器集线器140。在该情况下,M和N的缺省值用于将该配置转送给存储器集线器140。然后存储器集线器140能够使用该配置数据,将连接到总线154、156中的信号线的内部缓冲器配置为输入缓冲器或输出缓冲器。作为替换,可使用硬件来分析流经总线154、156的流量,并通过例如操作系统或运行时间代理之类的软件来确定实际的流量。也可以使用其它方式来确定流经总线154、156的实际流量。
如果将将要流经总线154、156的预期流量用作调整M和N的基准,可由用户来确定预期的流量,然后通过适当的方式将流量耦合到存储器集线器控制器128和存储器集线器140。例如,可通过适当的接口来耦合预期使用的信息,例如JTAG接口(未示出)或/和I2C接口(未示出)。在任意一种情形下,存储集线控制器128和存储器集线器140可随后相应地配置连接到总线154、156中的信号线上的内部缓冲器。
将要流经总线154、156的预期流量可如上所述地由用户直接确定,也可以通过其它信息来推断。将要流经总线154、156的预期流量可以根据包括在系统200中的硬件类型或处理器104所执行的软件来确定。例如,处理器104可根据其所执行的应用程序的类型,为M和N确定适当的值,并将这些值耦合到存储器集线器控制器128和存储器集线器140。在正在执行安装程序时,通常有大量的写入访问。在这种情况下,处理器104将增加M的值并减小N的值。另一方面,图形密集的应用程序通常需要不相称的读出访问量,因此,将减小M的值并增加N的值。通信程序通常具有大约相同的读出和写入量,因此将把M的值设定成与N的值相等。也可可替换地使用其它的硬件或软件方式来确定流经总线154、156的流量。
尽管总线154、156中的所有信号线都可配置成双向的,从而使它们能够或者是下游总线154的一部分或者是上游总线156的一部分,但总线154、156中在数量上对应于M和N的最小值的部分线路可以是单向的,并专用于下游总线154或者上游总线156。将连接到每条线路的输入缓冲器的输入也连接到输出缓冲器的输出的这种需求在一些情况下可能会有超出线路负荷的倾向。然而,可通过均衡化技术,或者通过当例如不使用时,将输入缓冲器从总线154、156的线路上断开,来缓和该潜在问题。因此,将输入和输出缓冲器连接到总线154、156的方式,以及能够用于确定M和N的值的特定硬件和软件对本领域的技术人员来说是显而易见的。
通过以上的描述将意识到,虽然在此为了说明的目的,描述了本发明的特定实施方式,但本领域的技术人员能够理解在不脱离本发明的精神和范围下可进行各种修改。例如,尽管示出的存储器模块与存储器集线器控制器是物理隔离的,但应该理解,它们不需要物理隔离。取而代之的是,可以将存储器集线器控制器和存储器模块安置在共同的基片上,例如主板。因此,除了权利要求所限定的以外,本发明不受到任何限制。
Claims (57)
1、在具有存储器集线器控制器和至少一个存储器模块的存储器系统中,所述至少一个存储器模块具有存储器集线器以及连接到所述存储器集线器的多个存储器设备,一种用于在所述存储器集线器控制器与在所述至少一个存储器模块中的存储器集线器之间耦合命令、地址和数据信号的方法,所述方法包括:
使用具有第一容量的通信通道,将命令、地址和数据信号从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器;
使用具有第二容量的通信通道,将数据信号从所述至少一个存储器模块中的存储器集线器耦合到所述存储器集线器控制器,其中第一容量与第二容量之和为固定值;以及
在所述存储器系统运行期间改变第一容量和第二容量。
2、如权利要求1所述的方法,其中改变第一容量和第二容量的动作包括根据所述信号从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器的速率,以及所述信号从所述至少一个存储器模块中的存储器集线器耦合到所述存储器集线器控制器的速率来改变第一容量和第二容量。
3、如权利要求2所述的方法,其中改变第一容量和第二容量的动作包括:
在所述存储器集线器控制器上,确定在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合所述信号的速率;以及
根据所确定的在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合所述信号的速率来改变第一容量和第二容量。
4、如权利要求2所述的方法,其中改变第一容量和第二容量的动作包括:
在所述至少一个存储器模块的存储器集线器上,确定在所述存储器集线器控制器与所述存储器集线器之间耦合所述信号的速率;以及
根据所确定的在所述存储器集线器控制器与所述存储器集线器之间耦合所述信号的速率来改变第一容量和第二容量。
5、如权利要求2所述的方法,其中改变第一容量和第二容量的动作包括:
使用软件来确定在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合所述信号的速率;以及
根据所述软件所确定的速率改变第一容量和第二容量。
6、如权利要求5所述的方法,其中使用所述软件来确定在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合所述信号的速率的动作包括:使用操作系统软件来确定在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合所述信号的速率。
7、如权利要求2所述的方法,其中改变第一容量和第二容量的动作包括:
在不同于所述至少一个存储器模块中的所述存储器集线器的位置处确定在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合所述信号的速率;
将表示所确定的速率的信息传送给所述至少一个存储器模块的存储器集线器;以及
根据所传送的信息改变第一容量和第二容量。
8、如权利要求2所述的方法,其中改变第一容量和第二容量的动作包括:
在不同于所述存储器集线器控制器的位置处确定在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合所述信号的速率;
将表示所确定的速率的信息传送给所述存储器集线器控制器;以及
根据所传送的信息改变第一容量和第二容量。
9、如权利要求1所述的方法,其中在所述存储器系统运行期间改变第一容量和第二容量的动作包括:将所述存储器集线器控制器与所述至少一个存储器模块的存储器集线器中的缓冲器配置为输入缓冲器或输出缓冲器。
10、如权利要求1所述的方法,其中改变第一容量和第二容量的动作包括:根据预期所述信号将要从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器的速率,以及根据预期所述信号将要从所述至少一个存储器模块中的存储器集线器耦合到所述存储器集线器控制器的速率来改变第一容量和第二容量。
11、如权利要求10所述的方法,其中改变第一容量和第二容量的动作包括:
根据包含在所述存储器系统相关联的系统中的硬件类型,确定预期所述信号将要在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合的速率;以及
根据所确定的预期将要在所述存储器集线器控制器与所述至少一个存储器模块中的存储器集线器之间耦合所述信号的速率来改变第一容量和第二容量。
12、如权利要求1所述的方法,其中在存储器系统运行期间改变第一容量和第二容量的动作包括在第一容量和第二容量的最小值和最大值之间改变第一容量和第二容量。
13、如权利要求1所述的方法,其中改变第一容量和第二容量的动作包括手动改变第一容量和第二容量。
14、如权利要求13所述的方法,其中手动改变第一容量和第二容量的动作包括手动调整至少一个电连接。
15、如权利要求1所述的方法,其中将命令、地址和数据信号从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器的动作包括:将含有命令、地址和数据信号的数据包从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器。
16、如权利要求1所述的方法,其中在所述存储器系统运行期间改变第一容量和第二容量的动作包括在所述存储器系统初始化期间改变第一容量和第二容量。
17、在具有存储器集线器控制器、至少一个存储器模块以及总线的存储器系统中,所述至少一个存储器模块具有存储器集线器以及连接到所述存储器集线器的多个存储器设备,所述总线具有M条连接在所述存储器集线器控制器与所述至少一个存储器模块的存储器集线器之间的信号线,一种用于在所述存储器集线器控制器与所述至少一个存储器模块的存储器集线器之间经由所述总线耦合命令、地址和数据信号的方法,所述方法包括:
使用所述总线的M条信号线中的N条线,将命令、地址和数据信号从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器;
使用所述总线的M条信号线中的P条线,将数据信号从所述至少一个存储器模块中的存储器集线器耦合到所述存储器集线器控制器,其中N+P=M;以及
在所述存储器系统运行期间改变N和P的值。
18、如权利要求17所述的方法,其中改变信号线的第一数量和信号线的第二数量的动作包括根据信号通过所述总线进行耦合的速率来改变N和P的值。
19、如权利要求18所述的方法,其中改变N和P的值的动作包括:
在所述存储器集线器控制器上,确定通过所述总线耦合所述信号的速率;以及
根据所确定的通过所述总线耦合所述信号的速率来改变N和P的值。
20、如权利要求18所述的方法,其中改变N和P的值的动作包括:
在所述至少一个存储器模块的存储器集线器上,确定通过所述总线耦合所述信号的速率;以及
根据所确定的通过所述总线耦合所述信号的速率来改变N和P的值。
21、如权利要求18所述的方法,其中改变N和P的值的动作包括:
使用软件来确定通过所述总线耦合所述信号的速率;以及
根据所述软件所确定的速率改变N和P的值。
22、如权利要求21所述的方法,其中使用所述软件来确定通过所述总线耦合所述信号的速率的动作包括使用操作系统软件来确定通过所述总线耦合所述信号的速率。
23、如权利要求18所述的方法,其中根据通过所述总线耦合所述信号的速率来改变N和P的值的动作包括:根据通过所述总线从所述存储器集线器控制器向所述至少一个存储器模块中的存储器集线器耦合所述信号的速率来改变N和P的值。
24、如权利要求18所述的方法,其中根据通过所述总线耦合所述信号的速率来改变N和P的值的动作包括:根据通过所述总线从所述至少一个存储器模块中的存储器集线器向所述存储器集线器控制器耦合所述信号的速率来改变N和P的值。
25、如权利要求18所述的方法,其中改变N和P的值的动作包括:
在不同于所述至少一个存储器模块中的所述存储器集线器的位置上确定通过所述总线耦合所述信号的速率;
将表示所确定的速率的信息传送给所述至少一个存储器模块的存储器集线器;以及
根据所传送的信息改变N和P的值。
26、如权利要求18所述的方法,其中改变N和P的值的动作包括:
在不同于所述存储器集线器控制器的位置上确定通过所述总线耦合所述信号的速率;
将表示所确定的速率的信息传送给所述存储器集线器控制器;以及
根据所传送的信息改变N和P的值。
27、如权利要求17所述的方法,其中在所述存储器系统运行期间改变N和P的值的动作包括:将所述存储器集线器控制器与所述至少一个存储器模块的存储器集线器中的缓冲器配置为输入缓冲器或输出缓冲器。
28、如权利要求18所述的方法,其中改变N和P的值的动作包括根据预期将要通过所述总线耦合所述信号的速率来改变N和P的值。
29、如权利要求28所述的方法,其中改变N和P的值的动作包括:
确定预期将要通过所述总线耦合所述信号的速率;以及
根据所确定的预期将要通过所述总线耦合所述信号的速率来改变N和P的值。
30、如权利要求17所述的方法,其中在所述存储器系统运行的期间改变N和P的值的动作包括在N和P的最小值和最大值之间改变N和P的值。
31、如权利要求17所述的方法,其中改变N和P的值的动作包括手动改变N和P的值。
32、如权利要求31所述的方法,其中手动改变N和P的值的动作包括手动调整至少一个电连接。
33、如权利要求17所述的方法,其中使用所述总线的M条信号线中的N条线将命令、地址和数据信号从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器的动作包括:使用所述总线的M条信号线中的N条线将含有命令、地址和数据信号的数据包从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器。
34、如权利要求17所述的方法,其中使用所述总线的M条信号线中的N条线将命令、地址和数据信号从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器的动作包括:使用具有N条信号线的单向下游总线将命令、地址和数据信号从所述存储器集线器控制器耦合到所述至少一个存储器模块中的存储器集线器,并且其中使用所述总线的M条信号线中的P条线将数据信号从所述至少一个存储器模块中的存储器集线器耦合到所述存储器集线器控制器的动作包括:使用具有P条信号线的单向上游总线将数据信号从所述至少一个存储器模块中的存储器集线器耦合到所述存储器集线器控制器。
35、如权利要求17所述的方法,其中在所述存储器系统运行期间改变N和P的值的动作包括在所述存储器系统初始化期间改变N和P的值。
36、一种存储器系统,包括:
具有M个缓冲器的存储器集线器控制器,其中所述M个缓冲器中的N个配置为输出缓冲器,所述M个缓冲器中的P个配置为输入缓冲器,在所述存储器系统运行期间N和P的值是可改变的;
至少一个存储器模块,其包括:
具有多个缓冲器的存储器集线器,其中的N个缓冲器配置为输入缓冲器,其中的P个缓冲器配置为输出缓冲器;以及
连接到存储器集线器的多个存储器设备;以及
具有M条信号线的总线,其中每条信号线连接在所述存储器集线器控制器的各个缓冲器与所述存储器集线器的各个缓冲器之间,M的值等于N和P的和。
37、如权利要求36所述的存储器系统,其中根据所述信号通过所述总线进行耦合的速率,为所述存储器集线器控制器和所述存储器集线器中的缓冲器改变M和N的值。
38、如权利要求37所述的存储器系统,其中所述存储器集线器控制器用于确定所述信号通过所述总线进行耦合的速率,并且其中,根据所确定的所述信号通过所述总线进行耦合的速率,为所述存储器集线器控制器和所述存储器集线器中的缓冲器改变M和N的值。
39、如权利要求37所述的存储器系统,其中所述存储器集线器用于确定所述信号通过所述总线进行耦合的速率,并且其中,根据所确定的所述信号通过所述总线进行耦合的速率,为所述存储器集线器控制器和所述存储器集线器中的缓冲器改变M和N的值。
40、如权利要求37所述的存储器系统,其中根据所述信号通过所述总线从所述存储器集线器控制器耦合到所述存储器集线器的速率,为所述存储器集线器控制器和所述存储器集线器中的缓冲器改变M和N的值。
41、如权利要求37所述的存储器系统,其中根据所述信号通过所述总线从所述存储器集线器耦合到所述存储器集线器控制器的速率,为所述存储器集线器控制器和所述存储器集线器中的缓冲器改变M和N的值。
42、如权利要求36所述的存储器系统,其中根据预期所述信号将要通过所述总线进行耦合的速率为所述存储器集线器控制器和所述存储器集线器中的缓冲器改变M和N的值。
43、如权利要求42所述的存储器系统,其中所述存储器集线器控制器用于确定预期所述信号将要通过所述总线进行耦合的速率,并且其中,根据所确定的预期所述信号将要通过所述总线进行耦合的速率,为所述存储器集线器控制器和所述存储器集线器中的缓冲器改变M和N的值。
44、如权利要求42所述的存储器系统,其中所述存储器集线器用于确定预期所述信号将要通过所述总线进行耦合的速率,并且其中,根据所确定的预期所述信号将要通过所述总线进行耦合的速率为所述存储器集线器控制器和所述存储器集线器中的缓冲器改变M和N的值。
45、如权利要求36所述的存储器系统,其中N和P的值在N和P的最小值和最大值之间改变。
46、如权利要求36所述的存储器系统,其中所述存储器集线器控制器可在所述存储器系统初始化期间改变N和P的值。
47、一种基于处理器的系统,包括:
具有处理器总线的处理器;
连接到所述处理器总线的系统控制器,所述系统控制器具有外围设备端口;
连接到所述处理器总线的存储器集线器控制器,所述存储器集线器控制器具有输出端口和输入端口;
至少一个连接到所述系统控制器的外围设备端口的输入设备;
至少一个连接到所述系统控制器的外围设备端口的输出设备;
至少一个连接到所述系统控制器的外围设备端口的数据存储设备;
至少一个具有存储器集线器以及多个连接到所述存储器集线器的存储器设备的存储器模块;
连接在所述存储器控制器的输出端口与所述至少一个存储器模块的存储器集线器之间的下游总线,所述下游总线的宽度为M比特,M的值是可变的,从而可调整所述下游总线的带宽;以及
连接在所述存储器控制器的输入端口与所述至少一个存储器模块的存储器集线器之间的上游总线,所述上游总线的宽度为N比特,其中N等于一个固定值减去M,N的值是可变的,从而可调整所述上游总线的带宽。
48、如权利要求47所述的基于处理器的系统,其中根据所述信号通过所述下游总线和所述上游总线中的至少一条进行耦合的速率来改变M和N的值。
49、如权利要求48所述的基于处理器的系统,其中所述存储器集线器控制器用于确定所述信号通过所述下游总线和所述上游总线中的至少一条进行耦合的速率,并且根据所确定的所述信号通过所述下游总线和所述上游总线中至少一条进行耦合的速率来改变M和N的值。
50、如权利要求48所述的基于处理器的系统,其中所述存储器集线器用于确定所述信号通过所述下游总线和所述上游总线中的至少一条进行耦合的速率,并且根据所确定的所述信号通过所述下游总线和所述上游总线中的至少一条进行耦合的速率来改变M和N的值。
51、如权利要求48所述的基于处理器的系统,其中根据所述信号通过所述下游总线从所述存储器集线器控制器耦合到所述存储器集线器的速率来改变M和N的值。
52、如权利要求48所述的基于处理器的系统,其中根据所述信号通过所述上游总线从所述存储器集线器耦合到所述存储器集线器控制器的速率为来改变M和N的值。
53、如权利要求47所述的基于处理器的系统,其中根据预期所述信号将要通过所述下游总线和所述上游总线中的至少一条进行耦合的速率来改变M和N的值。
54、如权利要求53所述的基于处理器的系统,其中所述存储器集线器控制器用于确定预期所述信号将要通过所述下游总线和所述上游总线中的至少一条进行耦合的速率,并且根据所确定的预期所述信号将要通过所述下游总线和所述上游总线中的至少一条进行耦合的速率来改变M和N的值。
55、如权利要求53所述的基于处理器的系统,其中所述存储器集线器用于确定预期所述信号将要通过所述下游总线和所述上游总线中的至少一条进行耦合的速率,并且根据所确定的预期所述信号将要通过所述下游总线和所述上游总线中的至少一条进行耦合的速率来改变M和N的值。
56、如权利要求47所述的基于处理器的系统,其中N和P的值在N和P的最小值和最大值之间改变。
57、如权利要求47所述的基于处理器的系统,其中在所述基于处理器的系统初始化期间改变N和P的值。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104541256A (zh) * | 2012-09-29 | 2015-04-22 | 英特尔公司 | 智能远存储器带宽缩放 |
US9384818B2 (en) | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7836252B2 (en) | 2002-08-29 | 2010-11-16 | Micron Technology, Inc. | System and method for optimizing interconnections of memory devices in a multichip module |
US7016213B2 (en) * | 2003-05-13 | 2006-03-21 | Advanced Micro Devices, Inc. | Method for initializing a system including a host and plurality of memory modules connected via a serial memory interconnect |
US7245145B2 (en) | 2003-06-11 | 2007-07-17 | Micron Technology, Inc. | Memory module and method having improved signal routing topology |
US7133991B2 (en) * | 2003-08-20 | 2006-11-07 | Micron Technology, Inc. | Method and system for capturing and bypassing memory transactions in a hub-based memory system |
US7120743B2 (en) | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
US7366864B2 (en) | 2004-03-08 | 2008-04-29 | Micron Technology, Inc. | Memory hub architecture having programmable lane widths |
US7120723B2 (en) | 2004-03-25 | 2006-10-10 | Micron Technology, Inc. | System and method for memory hub-based expansion bus |
US7590797B2 (en) | 2004-04-08 | 2009-09-15 | Micron Technology, Inc. | System and method for optimizing interconnections of components in a multichip memory module |
US7222224B2 (en) * | 2004-05-21 | 2007-05-22 | Rambus Inc. | System and method for improving performance in computer memory systems supporting multiple memory access latencies |
US7392331B2 (en) | 2004-08-31 | 2008-06-24 | Micron Technology, Inc. | System and method for transmitting data packets in a computer system having a memory hub architecture |
US7447831B2 (en) * | 2006-05-18 | 2008-11-04 | International Business Machines Corporation | Memory systems for automated computing machinery |
US7620763B2 (en) * | 2006-07-26 | 2009-11-17 | International Business Machines Corporation | Memory chip having an apportionable data bus |
US7546410B2 (en) * | 2006-07-26 | 2009-06-09 | International Business Machines Corporation | Self timed memory chip having an apportionable data bus |
US7844769B2 (en) * | 2006-07-26 | 2010-11-30 | International Business Machines Corporation | Computer system having an apportionable data bus and daisy chained memory chips |
US7490186B2 (en) * | 2006-07-26 | 2009-02-10 | International Business Machines Corporation | Memory system having an apportionable data bus and daisy chained memory chips |
US8037272B2 (en) * | 2007-06-27 | 2011-10-11 | International Business Machines Corporation | Structure for memory chip for high capacity memory subsystem supporting multiple speed bus |
US8037258B2 (en) * | 2007-06-27 | 2011-10-11 | International Business Machines Corporation | Structure for dual-mode memory chip for high capacity memory subsystem |
US7818512B2 (en) * | 2007-06-27 | 2010-10-19 | International Business Machines Corporation | High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules |
US7921264B2 (en) * | 2007-06-27 | 2011-04-05 | International Business Machines Corporation | Dual-mode memory chip for high capacity memory subsystem |
US7822936B2 (en) * | 2007-06-27 | 2010-10-26 | International Business Machines Corporation | Memory chip for high capacity memory subsystem supporting replication of command data |
US20090006774A1 (en) * | 2007-06-27 | 2009-01-01 | Gerald Keith Bartley | High Capacity Memory Subsystem Architecture Employing Multiple-Speed Bus |
US7809913B2 (en) * | 2007-06-27 | 2010-10-05 | International Business Machines Corporation | Memory chip for high capacity memory subsystem supporting multiple speed bus |
US7921271B2 (en) * | 2007-06-27 | 2011-04-05 | International Business Machines Corporation | Hub for supporting high capacity memory subsystem |
US7996641B2 (en) * | 2007-06-27 | 2011-08-09 | International Business Machines Corporation | Structure for hub for supporting high capacity memory subsystem |
US8037270B2 (en) * | 2007-06-27 | 2011-10-11 | International Business Machines Corporation | Structure for memory chip for high capacity memory subsystem supporting replication of command data |
US8019949B2 (en) * | 2007-06-27 | 2011-09-13 | International Business Machines Corporation | High capacity memory subsystem architecture storing interleaved data for reduced bus speed |
ATE535870T1 (de) * | 2008-03-03 | 2011-12-15 | Nec Corp | Steuervorrichtung für schnellen datenaustausch zwischen verarbeitungseinheiten in einer prozessorarchitektur mit verarbeitungseinheiten verschiedener bandbreitenverbindung mit einem pipeline-ring-bus |
US8656082B2 (en) * | 2008-08-05 | 2014-02-18 | Micron Technology, Inc. | Flexible and expandable memory architectures |
US8412880B2 (en) * | 2009-01-08 | 2013-04-02 | Micron Technology, Inc. | Memory system controller to manage wear leveling across a plurality of storage nodes |
US8463948B1 (en) * | 2011-07-01 | 2013-06-11 | Intel Corporation | Method, apparatus and system for determining an identifier of a volume of memory |
WO2013048508A1 (en) * | 2011-09-30 | 2013-04-04 | Intel Corporation | Bandwidth configurable io connector |
US10402348B2 (en) * | 2013-04-12 | 2019-09-03 | Texas Instruments Incorporated | Method and system for using feedback information for selecting a routing bus for a memory transaction |
US9141541B2 (en) | 2013-09-20 | 2015-09-22 | Advanced Micro Devices, Inc. | Nested channel address interleaving |
US10445025B2 (en) * | 2014-03-18 | 2019-10-15 | Micron Technology, Inc. | Apparatuses and methods having memory tier structure and recursively searching between tiers for address in a translation table where information is only directly transferred between controllers |
CN104123249B (zh) * | 2014-07-22 | 2018-03-09 | 山西达鑫核科技有限公司 | 一种串行访问的新型动态存储器sddr架构阵列 |
US10339072B2 (en) * | 2016-04-01 | 2019-07-02 | Intel Corporation | Read delivery for memory subsystem with narrow bandwidth repeater channel |
JP7006166B2 (ja) * | 2017-11-17 | 2022-01-24 | 富士通株式会社 | データ転送装置およびデータ転送方法 |
US11262949B2 (en) * | 2020-05-28 | 2022-03-01 | Advanced Micro Devices, Inc. | Command throughput in PIM-enabled memory using available data bus bandwidth |
US11726659B2 (en) | 2021-03-10 | 2023-08-15 | Samsung Electronics Co., Ltd. | Systems, methods, and devices for data storage with specified data transfer rate |
TWI773517B (zh) | 2021-09-06 | 2022-08-01 | 宏正自動科技股份有限公司 | 集線器系統控制方法 |
Family Cites Families (332)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US444384A (en) * | 1891-01-06 | Tennis-court marker | ||
US630163A (en) * | 1898-08-17 | 1899-08-01 | Charles C Ball | Heater. |
US3777154A (en) | 1972-02-07 | 1973-12-04 | R Lindsey | Optical data processing system |
US4045781A (en) | 1976-02-13 | 1977-08-30 | Digital Equipment Corporation | Memory module with selectable byte addressing for digital data processing system |
US4253144A (en) | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Multi-processor communication network |
US4253146A (en) | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Module for coupling computer-processors |
US4245306A (en) | 1978-12-21 | 1981-01-13 | Burroughs Corporation | Selection of addressed processor in a multi-processor network |
US4240143A (en) | 1978-12-22 | 1980-12-16 | Burroughs Corporation | Hierarchical multi-processor network for memory sharing |
US4443845A (en) * | 1980-06-26 | 1984-04-17 | Texas Instruments Incorporated | Memory system having a common interface |
KR900007564B1 (ko) * | 1984-06-26 | 1990-10-15 | 모토로라 인코포레이티드 | 동적 버스를 갖는 데이터 처리기 |
US4608702A (en) | 1984-12-21 | 1986-08-26 | Advanced Micro Devices, Inc. | Method for digital clock recovery from Manchester-encoded signals |
US4724520A (en) | 1985-07-01 | 1988-02-09 | United Technologies Corporation | Modular multiport data hub |
DE3614062A1 (de) | 1986-04-23 | 1987-10-29 | Siemens Ag | Verfahren zur flusssteuerung von daten innerhalb eines vermaschten datennetzes |
US4707823A (en) | 1986-07-21 | 1987-11-17 | Chrysler Motors Corporation | Fiber optic multiplexed data acquisition system |
US4809232A (en) | 1986-12-16 | 1989-02-28 | The United States Of America As Represented By The United States Department Of Energy | High speed, very large (8 megabyte) first in/first out buffer memory (FIFO) |
US4823403A (en) | 1987-03-26 | 1989-04-18 | Switch Tech, Inc. | System for optically transmitting data between circuit packs, such as printed circuit boards |
JPH07117863B2 (ja) | 1987-06-26 | 1995-12-18 | 株式会社日立製作所 | オンラインシステムの再立上げ方式 |
US4813772A (en) | 1987-09-08 | 1989-03-21 | The Regents Of The University Of California | Electro-optical interface |
US4891808A (en) | 1987-12-24 | 1990-01-02 | Coherent Communication Systems Corp. | Self-synchronizing multiplexer |
US5125084A (en) * | 1988-05-26 | 1992-06-23 | Ibm Corporation | Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller |
US5251303A (en) | 1989-01-13 | 1993-10-05 | International Business Machines Corporation | System for DMA block data transfer based on linked control blocks |
US5442770A (en) | 1989-01-24 | 1995-08-15 | Nec Electronics, Inc. | Triple port cache memory |
US4953930A (en) | 1989-03-15 | 1990-09-04 | Ramtech, Inc. | CPU socket supporting socket-to-socket optical communications |
JPH0359753A (ja) * | 1989-07-28 | 1991-03-14 | Seiko Epson Corp | 双方向バスバッファ |
JPH03156795A (ja) | 1989-11-15 | 1991-07-04 | Toshiba Micro Electron Kk | 半導体メモリ回路装置 |
US5317752A (en) | 1989-12-22 | 1994-05-31 | Tandem Computers Incorporated | Fault-tolerant computer system with auto-restart after power-fall |
US5327553A (en) | 1989-12-22 | 1994-07-05 | Tandem Computers Incorporated | Fault-tolerant computer system with /CONFIG filesystem |
JP2772103B2 (ja) | 1990-03-28 | 1998-07-02 | 株式会社東芝 | 計算機システム立上げ方式 |
US5243703A (en) | 1990-04-18 | 1993-09-07 | Rambus, Inc. | Apparatus for synchronously generating clock signals in a data processing system |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
GB9108599D0 (en) | 1991-04-22 | 1991-06-05 | Pilkington Micro Electronics | Peripheral controller |
JP2836321B2 (ja) * | 1991-11-05 | 1998-12-14 | 三菱電機株式会社 | データ処理装置 |
US5831467A (en) | 1991-11-05 | 1998-11-03 | Monolithic System Technology, Inc. | Termination circuit with power-down mode for use in circuit module architecture |
US5461627A (en) | 1991-12-24 | 1995-10-24 | Rypinski; Chandos A. | Access protocol for a common channel wireless network |
US5307381A (en) | 1991-12-27 | 1994-04-26 | Intel Corporation | Skew-free clock signal distribution network in a microprocessor |
JP2554816B2 (ja) | 1992-02-20 | 1996-11-20 | 株式会社東芝 | 半導体記憶装置 |
US5355391A (en) | 1992-03-06 | 1994-10-11 | Rambus, Inc. | High speed bus system |
DE4345604B3 (de) | 1992-03-06 | 2012-07-12 | Rambus Inc. | Vorrichtung zur Kommunikation mit einem DRAM |
ES2170066T3 (es) | 1992-03-25 | 2002-08-01 | Sun Microsystems Inc | Sistema de acoplamiento de memoria de fibra optica. |
US5432907A (en) | 1992-05-12 | 1995-07-11 | Network Resources Corporation | Network hub with integrated bridge |
US5270964A (en) | 1992-05-19 | 1993-12-14 | Sun Microsystems, Inc. | Single in-line memory module |
US5787475A (en) * | 1992-07-21 | 1998-07-28 | Digital Equipment Corporation | Controlled prefetching of data requested by a peripheral |
US5369550A (en) | 1992-09-02 | 1994-11-29 | Vlsi Technology, Inc. | Method and apparatus for cooling a molded-plastic integrated-circuit package |
GB2270780A (en) | 1992-09-21 | 1994-03-23 | Ibm | Scatter-gather in data processing systems. |
JP3369227B2 (ja) * | 1992-11-09 | 2003-01-20 | 株式会社東芝 | プロセッサ |
US5414819A (en) | 1992-12-18 | 1995-05-09 | Nec Research Institute, Inc. | Optical interconnection network |
US5423009A (en) * | 1993-02-18 | 1995-06-06 | Sierra Semiconductor Corporation | Dynamic sizing bus controller that allows unrestricted byte enable patterns |
JP3608804B2 (ja) * | 1993-05-14 | 2005-01-12 | 株式会社ソニー・コンピュータエンタテインメント | バス制御装置 |
JPH0713945A (ja) | 1993-06-16 | 1995-01-17 | Nippon Sheet Glass Co Ltd | 演算処理部および制御・記憶部分離型マルチプロセッサ ・システムのバス構造 |
US5497494A (en) | 1993-07-23 | 1996-03-05 | International Business Machines Corporation | Method for saving and restoring the state of a CPU executing code in protected mode |
US5493437A (en) | 1993-09-13 | 1996-02-20 | Motorola | External communication link for a credit card pager |
US5544345A (en) | 1993-11-08 | 1996-08-06 | International Business Machines Corporation | Coherence controls for store-multiple shared data coordinated by cache directory entries in a shared electronic storage |
US5729709A (en) | 1993-11-12 | 1998-03-17 | Intel Corporation | Memory controller with burst addressing circuit |
US5502621A (en) | 1994-03-31 | 1996-03-26 | Hewlett-Packard Company | Mirrored pin assignment for two sided multi-chip layout |
US5532856A (en) | 1994-06-30 | 1996-07-02 | Nec Research Institute, Inc. | Planar optical mesh-connected tree interconnect network |
US5566325A (en) | 1994-06-30 | 1996-10-15 | Digital Equipment Corporation | Method and apparatus for adaptive memory access |
US6175571B1 (en) | 1994-07-22 | 2001-01-16 | Network Peripherals, Inc. | Distributed memory switching hub |
US5978567A (en) | 1994-07-27 | 1999-11-02 | Instant Video Technologies Inc. | System for distribution of interactive multimedia and linear programs by enabling program webs which include control scripts to define presentation by client transceiver |
US6217234B1 (en) | 1994-07-29 | 2001-04-17 | Discovision Associates | Apparatus and method for processing data with an arithmetic unit |
US5553070A (en) | 1994-09-13 | 1996-09-03 | Riley; Robert E. | Data link module for time division multiplexing control systems |
US6804760B2 (en) | 1994-12-23 | 2004-10-12 | Micron Technology, Inc. | Method for determining a type of memory present in a system |
US5715456A (en) | 1995-02-13 | 1998-02-03 | International Business Machines Corporation | Method and apparatus for booting a computer system without pre-installing an operating system |
US5623534A (en) | 1995-04-07 | 1997-04-22 | Lucent Technologies Inc. | Method and apparatus for exchanging administrative information between local area networks |
US5608264A (en) | 1995-06-05 | 1997-03-04 | Harris Corporation | Surface mountable integrated circuit with conductive vias |
US5568574A (en) | 1995-06-12 | 1996-10-22 | University Of Southern California | Modulator-based photonic chip-to-chip interconnections for dense three-dimensional multichip module integration |
US5875352A (en) | 1995-11-03 | 1999-02-23 | Sun Microsystems, Inc. | Method and apparatus for multiple channel direct memory access control |
US5834956A (en) | 1995-12-29 | 1998-11-10 | Intel Corporation | Core clock correction in a 2/N mode clocking scheme |
US7681005B1 (en) | 1996-01-11 | 2010-03-16 | Micron Technology, Inc. | Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation |
US5966724A (en) | 1996-01-11 | 1999-10-12 | Micron Technology, Inc. | Synchronous memory device with dual page and burst mode operations |
US5832250A (en) | 1996-01-26 | 1998-11-03 | Unisys Corporation | Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits |
US5819304A (en) | 1996-01-29 | 1998-10-06 | Iowa State University Research Foundation, Inc. | Random access memory assembly |
US5659798A (en) | 1996-02-02 | 1997-08-19 | Blumrich; Matthias Augustin | Method and system for initiating and loading DMA controller registers by using user-level programs |
US5808897A (en) * | 1996-03-05 | 1998-09-15 | Micron Technology, Inc. | Integrated circuit device having interchangeable terminal connection |
JPH09319693A (ja) * | 1996-05-28 | 1997-12-12 | Hitachi Ltd | データ転送装置および並列コンピュータシステム |
US5818844A (en) | 1996-06-06 | 1998-10-06 | Advanced Micro Devices, Inc. | Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets |
US5875454A (en) | 1996-07-24 | 1999-02-23 | International Business Machiness Corporation | Compressed data cache storage system |
JPH1049511A (ja) | 1996-08-02 | 1998-02-20 | Oki Electric Ind Co Ltd | 1チップマイクロコンピュータ |
JP4070255B2 (ja) | 1996-08-13 | 2008-04-02 | 富士通株式会社 | 半導体集積回路 |
US6144327A (en) | 1996-08-15 | 2000-11-07 | Intellectual Property Development Associates Of Connecticut, Inc. | Programmably interconnected programmable devices |
TW304288B (en) | 1996-08-16 | 1997-05-01 | United Microelectronics Corp | Manufacturing method of semiconductor memory device with capacitor |
DE19636381C1 (de) * | 1996-09-09 | 1998-03-12 | Ibm | Bus mit anforderungsabhängiger Anpassung der in beiden Richtungen zur Verfügung stehenden Bandbreite |
JP3731949B2 (ja) | 1996-09-17 | 2006-01-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 記録媒体の読み出し装置 |
US6088774A (en) | 1996-09-20 | 2000-07-11 | Advanced Memory International, Inc. | Read/write timing for maximum utilization of bidirectional read/write bus |
US5706224A (en) | 1996-10-10 | 1998-01-06 | Quality Semiconductor, Inc. | Content addressable memory and random access memory partition circuit |
US6102964A (en) * | 1996-10-28 | 2000-08-15 | Altera Corporation | Fitting for incremental compilation of electronic designs |
US5818984A (en) | 1996-11-18 | 1998-10-06 | International Business Machines Corporation | Optoelectronic interconnection of integrated circuits |
US6167486A (en) | 1996-11-18 | 2000-12-26 | Nec Electronics, Inc. | Parallel access virtual channel memory system with cacheable channels |
KR19980064365A (ko) | 1996-12-19 | 1998-10-07 | 윌리엄비.켐플러 | 메모리 모듈로의 어드레스 및 데이타 분산용 장치 및 방법 |
US6308248B1 (en) | 1996-12-31 | 2001-10-23 | Compaq Computer Corporation | Method and system for allocating memory space using mapping controller, page table and frame numbers |
US6031241A (en) | 1997-03-11 | 2000-02-29 | University Of Central Florida | Capillary discharge extreme ultraviolet lamp source for EUV microlithography and other related applications |
JPH10262020A (ja) | 1997-03-18 | 1998-09-29 | Fujitsu Ltd | 回線多重化方式 |
US6271582B1 (en) | 1997-04-07 | 2001-08-07 | Micron Technology, Inc. | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die |
US5946712A (en) | 1997-06-04 | 1999-08-31 | Oak Technology, Inc. | Apparatus and method for reading data from synchronous memory |
US6243769B1 (en) | 1997-07-18 | 2001-06-05 | Micron Technology, Inc. | Dynamic buffer allocation for a computer system |
US6073190A (en) * | 1997-07-18 | 2000-06-06 | Micron Electronics, Inc. | System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair |
US6760833B1 (en) | 1997-08-01 | 2004-07-06 | Micron Technology, Inc. | Split embedded DRAM processor |
US6105075A (en) | 1997-08-05 | 2000-08-15 | Adaptec, Inc. | Scatter gather memory system for a hardware accelerated command interpreter engine |
JP4014708B2 (ja) | 1997-08-21 | 2007-11-28 | 株式会社ルネサステクノロジ | 半導体集積回路装置の設計方法 |
US6249802B1 (en) | 1997-09-19 | 2001-06-19 | Silicon Graphics, Inc. | Method, system, and computer program product for allocating physical memory in a distributed shared memory network |
US6067594A (en) | 1997-09-26 | 2000-05-23 | Rambus, Inc. | High frequency bus system |
JPH11120120A (ja) | 1997-10-13 | 1999-04-30 | Fujitsu Ltd | カードバス用インターフェース回路及びそれを有するカードバス用pcカード |
US6122719A (en) | 1997-10-31 | 2000-09-19 | Silicon Spice | Method and apparatus for retiming in a network of multiple context processing elements |
US5915123A (en) | 1997-10-31 | 1999-06-22 | Silicon Spice | Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements |
US5987196A (en) | 1997-11-06 | 1999-11-16 | Micron Technology, Inc. | Semiconductor structure having an optical signal path in a substrate and method for forming the same |
JP3724215B2 (ja) | 1997-11-10 | 2005-12-07 | 富士ゼロックス株式会社 | 光信号伝送装置および信号処理装置 |
US6098158A (en) | 1997-12-18 | 2000-08-01 | International Business Machines Corporation | Software-enabled fast boot |
US6111757A (en) | 1998-01-16 | 2000-08-29 | International Business Machines Corp. | SIMM/DIMM memory module |
US6023726A (en) | 1998-01-20 | 2000-02-08 | Netscape Communications Corporation | User configurable prefetch control system for enabling client to prefetch documents from a network server |
GB2333896B (en) | 1998-01-31 | 2003-04-09 | Mitel Semiconductor Ab | Vertical cavity surface emitting laser |
US7024518B2 (en) * | 1998-02-13 | 2006-04-04 | Intel Corporation | Dual-port buffer-to-memory interface |
US6186400B1 (en) | 1998-03-20 | 2001-02-13 | Symbol Technologies, Inc. | Bar code reader with an integrated scanning component module mountable on printed circuit board |
US6079008A (en) | 1998-04-03 | 2000-06-20 | Patton Electronics Co. | Multiple thread multiple data predictive coded parallel processing system and method |
US6247107B1 (en) | 1998-04-06 | 2001-06-12 | Advanced Micro Devices, Inc. | Chipset configured to perform data-directed prefetching |
US6084688A (en) * | 1998-04-30 | 2000-07-04 | Xerox Corporation | Network print server with page-parallel decomposing |
JPH11316617A (ja) | 1998-05-01 | 1999-11-16 | Mitsubishi Electric Corp | 半導体回路装置 |
KR100283243B1 (ko) | 1998-05-11 | 2001-03-02 | 구자홍 | 운영체제의 부팅방법 |
US6167465A (en) | 1998-05-20 | 2000-12-26 | Aureal Semiconductor, Inc. | System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection |
JPH11327357A (ja) | 1998-05-20 | 1999-11-26 | Fujitsu Ltd | 熱定着器の温度制御方法および装置並びに画像形成装置 |
SG75958A1 (en) | 1998-06-01 | 2000-10-24 | Hitachi Ulsi Sys Co Ltd | Semiconductor device and a method of producing semiconductor device |
US6405280B1 (en) | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
US6301637B1 (en) * | 1998-06-08 | 2001-10-09 | Storage Technology Corporation | High performance data paths |
US6134624A (en) | 1998-06-08 | 2000-10-17 | Storage Technology Corporation | High bandwidth cache system |
JP2000003589A (ja) | 1998-06-12 | 2000-01-07 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
US6453377B1 (en) * | 1998-06-16 | 2002-09-17 | Micron Technology, Inc. | Computer including optical interconnect, memory unit, and method of assembling a computer |
JP2000011640A (ja) | 1998-06-23 | 2000-01-14 | Nec Corp | 半導体記憶装置 |
FR2780535B1 (fr) | 1998-06-25 | 2000-08-25 | Inst Nat Rech Inf Automat | Dispositif de traitement de donnees d'acquisition, notamment de donnees d'image |
JP3178423B2 (ja) | 1998-07-03 | 2001-06-18 | 日本電気株式会社 | バーチャルチャネルsdram |
US6735679B1 (en) | 1998-07-08 | 2004-05-11 | Broadcom Corporation | Apparatus and method for optimizing access to memory |
US6286083B1 (en) | 1998-07-08 | 2001-09-04 | Compaq Computer Corporation | Computer system with adaptive memory arbitration scheme |
US6105088A (en) | 1998-07-10 | 2000-08-15 | Northrop Grumman Corporation | Backplane assembly for electronic circuit modules providing electronic reconfigurable connectivity of digital signals and manual reconfigurable connectivity power, optical and RF signals |
JP3248617B2 (ja) * | 1998-07-14 | 2002-01-21 | 日本電気株式会社 | 半導体記憶装置 |
US6272609B1 (en) | 1998-07-31 | 2001-08-07 | Micron Electronics, Inc. | Pipelined memory controller |
US6061296A (en) | 1998-08-17 | 2000-05-09 | Vanguard International Semiconductor Corporation | Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices |
US6219725B1 (en) | 1998-08-28 | 2001-04-17 | Hewlett-Packard Company | Method and apparatus for performing direct memory access transfers involving non-sequentially-addressable memory locations |
US6029250A (en) | 1998-09-09 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same |
US6229727B1 (en) | 1998-09-28 | 2001-05-08 | Cisco Technology, Inc. | Method and apparatus for support of multiple memory devices in a single memory socket architecture |
US6910109B2 (en) | 1998-09-30 | 2005-06-21 | Intel Corporation | Tracking memory page state |
US6587912B2 (en) | 1998-09-30 | 2003-07-01 | Intel Corporation | Method and apparatus for implementing multiple memory buses on a memory module |
US6343171B1 (en) | 1998-10-09 | 2002-01-29 | Fujitsu Limited | Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making |
US6243831B1 (en) | 1998-10-31 | 2001-06-05 | Compaq Computer Corporation | Computer system with power loss protection mechanism |
US6378056B2 (en) * | 1998-11-03 | 2002-04-23 | Intel Corporation | Method and apparatus for configuring a memory device and a memory channel using configuration space registers |
US6226729B1 (en) | 1998-11-03 | 2001-05-01 | Intel Corporation | Method and apparatus for configuring and initializing a memory device and a memory channel |
JP3248500B2 (ja) | 1998-11-12 | 2002-01-21 | 日本電気株式会社 | 半導体記憶装置およびそのデータ読み出し方法 |
US6434639B1 (en) | 1998-11-13 | 2002-08-13 | Intel Corporation | System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation |
US6405273B1 (en) | 1998-11-13 | 2002-06-11 | Infineon Technologies North America Corp. | Data processing device with memory coupling unit |
US6438622B1 (en) | 1998-11-17 | 2002-08-20 | Intel Corporation | Multiprocessor system including a docking system |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6463059B1 (en) | 1998-12-04 | 2002-10-08 | Koninklijke Philips Electronics N.V. | Direct memory access execution engine with indirect addressing of circular queues in addition to direct memory addressing |
US6349363B2 (en) | 1998-12-08 | 2002-02-19 | Intel Corporation | Multi-section cache with different attributes for each section |
US6067262A (en) | 1998-12-11 | 2000-05-23 | Lsi Logic Corporation | Redundancy analysis for embedded memories with built-in self test and built-in self repair |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6191663B1 (en) | 1998-12-22 | 2001-02-20 | Intel Corporation | Echo reduction on bit-serial, multi-drop bus |
JP3589058B2 (ja) | 1998-12-25 | 2004-11-17 | 富士ゼロックス株式会社 | 信号通信装置および多重バス制御装置 |
US6367074B1 (en) | 1998-12-28 | 2002-04-02 | Intel Corporation | Operation of a system |
US6598154B1 (en) | 1998-12-29 | 2003-07-22 | Intel Corporation | Precoding branch instructions to reduce branch-penalty in pipelined processors |
US6061263A (en) | 1998-12-29 | 2000-05-09 | Intel Corporation | Small outline rambus in-line memory module |
US6618777B1 (en) * | 1999-01-21 | 2003-09-09 | Analog Devices, Inc. | Method and apparatus for communicating between multiple functional units in a computer environment |
EP1703520B1 (en) | 1999-02-01 | 2011-07-27 | Renesas Electronics Corporation | Semiconductor integrated circuit and nonvolatile memory element |
US6285349B1 (en) | 1999-02-26 | 2001-09-04 | Intel Corporation | Correcting non-uniformity in displays |
JP2000268006A (ja) | 1999-03-15 | 2000-09-29 | Fuji Xerox Co Ltd | マルチプロセッサシステム |
US6564329B1 (en) | 1999-03-16 | 2003-05-13 | Linkup Systems Corporation | System and method for dynamic clock generation |
US6434654B1 (en) * | 1999-03-26 | 2002-08-13 | Koninklijke Philips Electronics N.V. | System bus with a variable width selectivity configurable at initialization |
US6229712B1 (en) | 1999-03-31 | 2001-05-08 | International Business Machines Corporation | Printed circuit board for coupling surface mounted optoelectric semiconductor devices |
US6496909B1 (en) | 1999-04-06 | 2002-12-17 | Silicon Graphics, Inc. | Method for managing concurrent access to virtual memory data structures |
US6381190B1 (en) | 1999-05-13 | 2002-04-30 | Nec Corporation | Semiconductor memory device in which use of cache can be selected |
US6233376B1 (en) | 1999-05-18 | 2001-05-15 | The United States Of America As Represented By The Secretary Of The Navy | Embedded fiber optic circuit boards and integrated circuits |
US6449308B1 (en) | 1999-05-25 | 2002-09-10 | Intel Corporation | High-speed digital distribution system |
US6294937B1 (en) | 1999-05-25 | 2001-09-25 | Lsi Logic Corporation | Method and apparatus for self correcting parallel I/O circuitry |
JP3721283B2 (ja) | 1999-06-03 | 2005-11-30 | 株式会社日立製作所 | 主記憶共有型マルチプロセッサシステム |
JP2001014840A (ja) | 1999-06-24 | 2001-01-19 | Nec Corp | 複数ラインバッファ型メモリlsi |
US6826160B1 (en) * | 1999-07-07 | 2004-11-30 | 3Com Corporation | Dynamic bandwidth allocation through multi-channel time slot assignment and migration for broadband access |
US6434736B1 (en) | 1999-07-08 | 2002-08-13 | Intel Corporation | Location based timing scheme in memory design |
US6401213B1 (en) | 1999-07-09 | 2002-06-04 | Micron Technology, Inc. | Timing circuit for high speed memory |
US6279072B1 (en) | 1999-07-22 | 2001-08-21 | Micron Technology, Inc. | Reconfigurable memory with selectable error correction storage |
US7827348B2 (en) | 2000-01-06 | 2010-11-02 | Super Talent Electronics, Inc. | High performance flash memory devices (FMD) |
US6477592B1 (en) | 1999-08-06 | 2002-11-05 | Integrated Memory Logic, Inc. | System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream |
US6629220B1 (en) | 1999-08-20 | 2003-09-30 | Intel Corporation | Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type |
US6493803B1 (en) | 1999-08-23 | 2002-12-10 | Advanced Micro Devices, Inc. | Direct memory access controller with channel width configurability support |
US6552564B1 (en) | 1999-08-30 | 2003-04-22 | Micron Technology, Inc. | Technique to reduce reflections and ringing on CMOS interconnections |
US6539490B1 (en) | 1999-08-30 | 2003-03-25 | Micron Technology, Inc. | Clock distribution without clock delay or skew |
US6307769B1 (en) | 1999-09-02 | 2001-10-23 | Micron Technology, Inc. | Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices |
US6594713B1 (en) * | 1999-09-10 | 2003-07-15 | Texas Instruments Incorporated | Hub interface unit and application unit interfaces for expanded direct memory access processor |
US6438668B1 (en) | 1999-09-30 | 2002-08-20 | Apple Computer, Inc. | Method and apparatus for reducing power consumption in a digital processing system |
US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
AU2119301A (en) | 1999-10-22 | 2001-05-08 | Teraconnect, Inc. | Wafer scale integration and remoted subsystems using opto-electronic transceivers |
US6421744B1 (en) | 1999-10-25 | 2002-07-16 | Motorola, Inc. | Direct memory access controller and method therefor |
US6681341B1 (en) | 1999-11-03 | 2004-01-20 | Cisco Technology, Inc. | Processor isolation method for integrated multi-processor systems |
JP2001154980A (ja) * | 1999-11-12 | 2001-06-08 | Geneticware Corp Ltd | データ/アドレスチャンネルを配置可能な情報処理システム |
KR100319292B1 (ko) | 1999-12-02 | 2002-01-05 | 윤종용 | 빠른 부팅 속도를 갖는 컴퓨터 시스템 및 그 방법 |
US6344664B1 (en) | 1999-12-02 | 2002-02-05 | Tera Connect Inc. | Electro-optical transceiver system with controlled lateral leakage and method of making it |
US6507899B1 (en) | 1999-12-13 | 2003-01-14 | Infineon Technologies North American Corp. | Interface for a memory unit |
US6501471B1 (en) | 1999-12-13 | 2002-12-31 | Intel Corporation | Volume rendering |
JP3546788B2 (ja) | 1999-12-20 | 2004-07-28 | 日本電気株式会社 | メモリ制御回路 |
JP3356747B2 (ja) | 1999-12-22 | 2002-12-16 | エヌイーシーマイクロシステム株式会社 | 半導体記憶装置 |
US20010034839A1 (en) | 1999-12-24 | 2001-10-25 | Guenter Karjoth | Method and apparatus for secure transmission of data and applications |
US6628294B1 (en) | 1999-12-31 | 2003-09-30 | Intel Corporation | Prefetching of virtual-to-physical address translation for display data |
KR100343383B1 (ko) | 2000-01-05 | 2002-07-15 | 윤종용 | 반도체 메모리 장치 및 이 장치의 데이터 샘플링 방법 |
US6502161B1 (en) | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
US7010642B2 (en) * | 2000-01-05 | 2006-03-07 | Rambus Inc. | System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices |
US6745275B2 (en) | 2000-01-25 | 2004-06-01 | Via Technologies, Inc. | Feedback system for accomodating different memory module loading |
US6785835B2 (en) | 2000-01-25 | 2004-08-31 | Hewlett-Packard Development Company, L.P. | Raid memory |
US6823023B1 (en) | 2000-01-31 | 2004-11-23 | Intel Corporation | Serial bus communication system |
US6256253B1 (en) | 2000-02-18 | 2001-07-03 | Infineon Technologies North America Corp. | Memory device with support for unaligned access |
US6185352B1 (en) | 2000-02-24 | 2001-02-06 | Siecor Operations, Llc | Optical fiber ribbon fan-out cables |
WO2001065735A1 (en) * | 2000-02-28 | 2001-09-07 | University Of Maryland Baltimore County | Error mitigation system using line coding for optical wdm communications |
JP2001265539A (ja) | 2000-03-16 | 2001-09-28 | Fuji Xerox Co Ltd | アレイ型記憶装置及び情報処理システム |
JP2001274323A (ja) | 2000-03-24 | 2001-10-05 | Hitachi Ltd | 半導体装置とそれを搭載した半導体モジュール、および半導体装置の製造方法 |
US6772261B1 (en) | 2000-04-27 | 2004-08-03 | International Business Machines Corporation | Interface that allows testing and using memory modules in computer systems not designed for the modules |
US6728800B1 (en) | 2000-06-28 | 2004-04-27 | Intel Corporation | Efficient performance based scheduling mechanism for handling multiple TLB operations |
US6594722B1 (en) | 2000-06-29 | 2003-07-15 | Intel Corporation | Mechanism for managing multiple out-of-order packet streams in a PCI host bridge |
JP2002014875A (ja) | 2000-06-30 | 2002-01-18 | Mitsubishi Electric Corp | 半導体集積回路、半導体集積回路のメモリリペア方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体 |
US6799268B1 (en) | 2000-06-30 | 2004-09-28 | Intel Corporation | Branch ordering buffer |
US6754812B1 (en) | 2000-07-06 | 2004-06-22 | Intel Corporation | Hardware predication for conditional instruction path branching |
US6816947B1 (en) | 2000-07-20 | 2004-11-09 | Silicon Graphics, Inc. | System and method for memory arbitration |
US6661940B2 (en) | 2000-07-21 | 2003-12-09 | Finisar Corporation | Apparatus and method for rebroadcasting signals in an optical backplane bus system |
US6845409B1 (en) | 2000-07-25 | 2005-01-18 | Sun Microsystems, Inc. | Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices |
JP2002063791A (ja) * | 2000-08-21 | 2002-02-28 | Mitsubishi Electric Corp | 半導体記憶装置およびメモリシステム |
US6366529B1 (en) | 2000-08-30 | 2002-04-02 | Texas Instruments Incorporated | Fast FiFo memory storage system |
US6453393B1 (en) | 2000-09-18 | 2002-09-17 | Intel Corporation | Method and apparatus for interfacing to a computer memory |
US6859208B1 (en) | 2000-09-29 | 2005-02-22 | Intel Corporation | Shared translation address caching |
US6523093B1 (en) | 2000-09-29 | 2003-02-18 | Intel Corporation | Prefetch buffer allocation and filtering system |
US6523092B1 (en) | 2000-09-29 | 2003-02-18 | Intel Corporation | Cache line replacement policy enhancement to avoid memory page thrashing |
US6658509B1 (en) | 2000-10-03 | 2003-12-02 | Intel Corporation | Multi-tier point-to-point ring memory interface |
US6570429B1 (en) | 2000-10-20 | 2003-05-27 | Cray Inc. | Method and apparatus for providing a clock signal to a semiconductor chip |
US6631440B2 (en) * | 2000-11-30 | 2003-10-07 | Hewlett-Packard Development Company | Method and apparatus for scheduling memory calibrations based on transactions |
US6792059B2 (en) | 2000-11-30 | 2004-09-14 | Trw Inc. | Early/on-time/late gate bit synchronizer |
US6807630B2 (en) | 2000-12-15 | 2004-10-19 | International Business Machines Corporation | Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory |
US6801994B2 (en) | 2000-12-20 | 2004-10-05 | Microsoft Corporation | Software management systems and methods for automotive computing devices |
WO2002052325A1 (en) | 2000-12-22 | 2002-07-04 | Nufern | Optoelectronic module with hermetically coated optical fiber |
US6751703B2 (en) | 2000-12-27 | 2004-06-15 | Emc Corporation | Data storage systems and methods which utilize an on-board cache |
US6622227B2 (en) * | 2000-12-27 | 2003-09-16 | Intel Corporation | Method and apparatus for utilizing write buffers in memory control/interface |
US7035212B1 (en) * | 2001-01-25 | 2006-04-25 | Optim Networks | Method and apparatus for end to end forwarding architecture |
JP2002259327A (ja) * | 2001-02-28 | 2002-09-13 | Hitachi Ltd | バス制御回路 |
US6889304B2 (en) | 2001-02-28 | 2005-05-03 | Rambus Inc. | Memory device supporting a dynamically configurable core organization |
DE10110469A1 (de) * | 2001-03-05 | 2002-09-26 | Infineon Technologies Ag | Integrierter Speicher und Verfahren zum Testen und Reparieren desselben |
US6721187B2 (en) * | 2001-03-16 | 2004-04-13 | International Business Machines Corporation | Multi-layered high density connections |
US6904499B2 (en) * | 2001-03-30 | 2005-06-07 | Intel Corporation | Controlling cache memory in external chipset using processor |
US7451335B2 (en) * | 2001-04-24 | 2008-11-11 | Broadcom Corporation | Selectively disabling a portion of ASF operations when ASF device is powered by auxiliary power |
US6910812B2 (en) | 2001-05-15 | 2005-06-28 | Peregrine Semiconductor Corporation | Small-scale optoelectronic package |
US6670959B2 (en) | 2001-05-18 | 2003-12-30 | Sun Microsystems, Inc. | Method and apparatus for reducing inefficiencies in shared memory devices |
US6697926B2 (en) | 2001-06-06 | 2004-02-24 | Micron Technology, Inc. | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device |
SE524110C2 (sv) | 2001-06-06 | 2004-06-29 | Kvaser Consultant Ab | Anordning och förfarande vid system med lokalt utplacerade modulenheter samt kontaktenhet för anslutning av sådan modulenhet |
US6711652B2 (en) * | 2001-06-21 | 2004-03-23 | International Business Machines Corporation | Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data |
US6920533B2 (en) * | 2001-06-27 | 2005-07-19 | Intel Corporation | System boot time reduction method |
US6623177B1 (en) * | 2001-07-09 | 2003-09-23 | Emc Corporation | Systems and methods for providing fiber optic communications between circuit boards |
US6721195B2 (en) | 2001-07-12 | 2004-04-13 | Micron Technology, Inc. | Reversed memory module socket and motherboard incorporating same |
JP4812976B2 (ja) * | 2001-07-30 | 2011-11-09 | エルピーダメモリ株式会社 | レジスタ、メモリモジュール及びメモリシステム |
US6792496B2 (en) | 2001-08-02 | 2004-09-14 | Intel Corporation | Prefetching data for peripheral component interconnect devices |
EP1286194A3 (en) * | 2001-08-21 | 2004-05-19 | Canon Kabushiki Kaisha | Optical waveguide apparatus |
US6681292B2 (en) * | 2001-08-27 | 2004-01-20 | Intel Corporation | Distributed read and write caching implementation for optimized input/output applications |
EP1421588B1 (en) | 2001-08-29 | 2012-01-18 | MediaTek Inc. | Method and apparatus utilizing flash burst mode to improve processor performance |
US7941056B2 (en) * | 2001-08-30 | 2011-05-10 | Micron Technology, Inc. | Optical interconnect in high-speed memory systems |
US6980748B2 (en) | 2001-08-30 | 2005-12-27 | International Business Machines Corporation | SiGe or germanium flip chip optical receiver |
US6599031B2 (en) * | 2001-09-12 | 2003-07-29 | Intel Corporation | Optical/electrical interconnects and package for high speed signaling |
US6665202B2 (en) | 2001-09-25 | 2003-12-16 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same |
US6718440B2 (en) | 2001-09-28 | 2004-04-06 | Intel Corporation | Memory access latency hiding with hint buffer |
US6681301B1 (en) | 2001-10-02 | 2004-01-20 | Advanced Micro Devices, Inc. | System for controlling multiple memory types |
US6961834B2 (en) * | 2001-10-12 | 2005-11-01 | Sonics, Inc. | Method and apparatus for scheduling of requests to dynamic random access memory device |
DE10153657C2 (de) | 2001-10-31 | 2003-11-06 | Infineon Technologies Ag | Anordnung zur Datenübertragung in einem Halbleiterspeichersystem und Datenübertragungsverfahren dafür |
US6886048B2 (en) | 2001-11-15 | 2005-04-26 | Hewlett-Packard Development Company, L.P. | Techniques for processing out-of-order requests in a processor-based system |
US6646929B1 (en) | 2001-12-05 | 2003-11-11 | Lsi Logic Corporation | Methods and structure for read data synchronization with minimal latency |
KR100454123B1 (ko) | 2001-12-06 | 2004-10-26 | 삼성전자주식회사 | 반도체 집적 회로 장치 및 그것을 구비한 모듈 |
US7024547B2 (en) * | 2001-12-10 | 2006-04-04 | Intel Corporation | Method and system for initializing a hardware device |
US6775747B2 (en) | 2002-01-03 | 2004-08-10 | Intel Corporation | System and method for performing page table walks on speculative software prefetch operations |
US6804764B2 (en) | 2002-01-22 | 2004-10-12 | Mircron Technology, Inc. | Write clock and data window tuning based on rank select |
US6661943B2 (en) | 2002-01-30 | 2003-12-09 | Intel Corporation | Fiber-free optical interconnect system for chip-to-chip signaling |
US20040022094A1 (en) | 2002-02-25 | 2004-02-05 | Sivakumar Radhakrishnan | Cache usage for concurrent multiple streams |
US6751113B2 (en) * | 2002-03-07 | 2004-06-15 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
US6795899B2 (en) | 2002-03-22 | 2004-09-21 | Intel Corporation | Memory system with burst length shorter than prefetch length |
US6735682B2 (en) | 2002-03-28 | 2004-05-11 | Intel Corporation | Apparatus and method for address calculation |
TWI270786B (en) | 2002-04-10 | 2007-01-11 | Avision Inc | Scanner capable of being a universal serial bus host |
US7110400B2 (en) | 2002-04-10 | 2006-09-19 | Integrated Device Technology, Inc. | Random access memory architecture and serial interface with continuous packet handling capability |
US6754417B2 (en) | 2002-04-24 | 2004-06-22 | Agilent Technologies, Inc. | Optical fiber tap capable of random placement along an optical fiber |
US20030217223A1 (en) | 2002-05-14 | 2003-11-20 | Infineon Technologies North America Corp. | Combined command set |
US6920510B2 (en) | 2002-06-05 | 2005-07-19 | Lsi Logic Corporation | Time sharing a single port memory among a plurality of ports |
US7133972B2 (en) * | 2002-06-07 | 2006-11-07 | Micron Technology, Inc. | Memory hub with internal cache and/or memory access prediction |
US6731548B2 (en) | 2002-06-07 | 2004-05-04 | Micron Technology, Inc. | Reduced power registered memory module and method |
US6752539B2 (en) * | 2002-06-28 | 2004-06-22 | International Buisness Machines Corporation | Apparatus and system for providing optical bus interprocessor interconnection |
US7200024B2 (en) * | 2002-08-02 | 2007-04-03 | Micron Technology, Inc. | System and method for optically interconnecting memory devices |
US7254331B2 (en) * | 2002-08-09 | 2007-08-07 | Micron Technology, Inc. | System and method for multiple bit optical data transmission in memory systems |
US7106973B2 (en) | 2002-08-13 | 2006-09-12 | Lightpointe Communications, Inc. | Apparatus and method for use in free-space optical communication comprising optically aligned components integrated on circuit boards |
US6754117B2 (en) * | 2002-08-16 | 2004-06-22 | Micron Technology, Inc. | System and method for self-testing and repair of memory modules |
US7149874B2 (en) * | 2002-08-16 | 2006-12-12 | Micron Technology, Inc. | Memory hub bypass circuit and method |
KR100468761B1 (ko) * | 2002-08-23 | 2005-01-29 | 삼성전자주식회사 | 분할된 시스템 데이터 버스에 연결되는 메모리 모듈을구비하는 반도체 메모리 시스템 |
US6820181B2 (en) * | 2002-08-29 | 2004-11-16 | Micron Technology, Inc. | Method and system for controlling memory accesses to memory modules having a memory hub architecture |
US7836252B2 (en) * | 2002-08-29 | 2010-11-16 | Micron Technology, Inc. | System and method for optimizing interconnections of memory devices in a multichip module |
US7102907B2 (en) * | 2002-09-09 | 2006-09-05 | Micron Technology, Inc. | Wavelength division multiplexed memory module, memory system and method |
US6821029B1 (en) | 2002-09-10 | 2004-11-23 | Xilinx, Inc. | High speed serial I/O technology using an optical link |
JP2004164579A (ja) * | 2002-09-24 | 2004-06-10 | Sharp Corp | データバス幅変換装置およびデータ処理装置 |
US6811320B1 (en) | 2002-11-13 | 2004-11-02 | Russell Mistretta Abbott | System for connecting a fiber optic cable to an electronic device |
JP2004171411A (ja) * | 2002-11-21 | 2004-06-17 | Hitachi Global Storage Technologies Netherlands Bv | データ記憶装置及びバッファメモリの管理方法 |
US7093115B2 (en) * | 2002-12-19 | 2006-08-15 | Intel Corporation | Method and apparatus for detecting an interruption in memory initialization |
US20040128421A1 (en) * | 2002-12-30 | 2004-07-01 | Intel Corporation | Apparatus and method for providing upgraded system memory for mobile platforms using mobile docking stations |
US7366423B2 (en) * | 2002-12-31 | 2008-04-29 | Intel Corporation | System having multiple agents on optical and electrical bus |
US6793408B2 (en) | 2002-12-31 | 2004-09-21 | Intel Corporation | Module interface with optical and electrical interconnects |
US7308524B2 (en) * | 2003-01-13 | 2007-12-11 | Silicon Pipe, Inc | Memory chain |
US6961259B2 (en) * | 2003-01-23 | 2005-11-01 | Micron Technology, Inc. | Apparatus and methods for optically-coupled memory systems |
WO2004097933A2 (en) | 2003-04-24 | 2004-11-11 | Sun Microsystems, Inc. | Method and apparatus for optically aligning integrated circuit devices |
US7136953B1 (en) * | 2003-05-07 | 2006-11-14 | Nvidia Corporation | Apparatus, system, and method for bus link width optimization |
US7426597B1 (en) * | 2003-05-07 | 2008-09-16 | Nvidia Corporation | Apparatus, system, and method for bus link width optimization of a graphics system |
US6982892B2 (en) * | 2003-05-08 | 2006-01-03 | Micron Technology, Inc. | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules |
US7016213B2 (en) * | 2003-05-13 | 2006-03-21 | Advanced Micro Devices, Inc. | Method for initializing a system including a host and plurality of memory modules connected via a serial memory interconnect |
US20040243769A1 (en) | 2003-05-30 | 2004-12-02 | Frame David W. | Tree based memory structure |
KR100505689B1 (ko) | 2003-06-11 | 2005-08-03 | 삼성전자주식회사 | 송수신 흐름에 따라 공유 버퍼 메모리의 할당량을제어하는 송수신 네트워크 제어기 및 그 방법 |
US7245145B2 (en) * | 2003-06-11 | 2007-07-17 | Micron Technology, Inc. | Memory module and method having improved signal routing topology |
US7120727B2 (en) | 2003-06-19 | 2006-10-10 | Micron Technology, Inc. | Reconfigurable memory module and method |
US7174432B2 (en) | 2003-08-19 | 2007-02-06 | Nvidia Corporation | Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture |
US7133991B2 (en) | 2003-08-20 | 2006-11-07 | Micron Technology, Inc. | Method and system for capturing and bypassing memory transactions in a hub-based memory system |
US7120743B2 (en) | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
US7234070B2 (en) * | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
US7177211B2 (en) * | 2003-11-13 | 2007-02-13 | Intel Corporation | Memory channel test fixture and method |
US7216196B2 (en) | 2003-12-29 | 2007-05-08 | Micron Technology, Inc. | Memory hub and method for memory system performance monitoring |
US7330992B2 (en) | 2003-12-29 | 2008-02-12 | Micron Technology, Inc. | System and method for read synchronization of memory modules |
US7181584B2 (en) * | 2004-02-05 | 2007-02-20 | Micron Technology, Inc. | Dynamic command and/or address mirroring system and method for memory modules |
US7412574B2 (en) | 2004-02-05 | 2008-08-12 | Micron Technology, Inc. | System and method for arbitration of memory responses in a hub-based memory system |
US7788451B2 (en) | 2004-02-05 | 2010-08-31 | Micron Technology, Inc. | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system |
US7366864B2 (en) | 2004-03-08 | 2008-04-29 | Micron Technology, Inc. | Memory hub architecture having programmable lane widths |
US20050210185A1 (en) | 2004-03-18 | 2005-09-22 | Kirsten Renick | System and method for organizing data transfers with memory hub memory modules |
US7257683B2 (en) | 2004-03-24 | 2007-08-14 | Micron Technology, Inc. | Memory arbitration system and method having an arbitration packet protocol |
US7120723B2 (en) * | 2004-03-25 | 2006-10-10 | Micron Technology, Inc. | System and method for memory hub-based expansion bus |
US7213082B2 (en) | 2004-03-29 | 2007-05-01 | Micron Technology, Inc. | Memory hub and method for providing memory sequencing hints |
US6980042B2 (en) | 2004-04-05 | 2005-12-27 | Micron Technology, Inc. | Delay line synchronizer apparatus and method |
US7590797B2 (en) * | 2004-04-08 | 2009-09-15 | Micron Technology, Inc. | System and method for optimizing interconnections of components in a multichip memory module |
US7222213B2 (en) * | 2004-05-17 | 2007-05-22 | Micron Technology, Inc. | System and method for communicating the synchronization status of memory modules during initialization of the memory modules |
US7363419B2 (en) | 2004-05-28 | 2008-04-22 | Micron Technology, Inc. | Method and system for terminating write commands in a hub-based memory system |
US7480808B2 (en) * | 2004-07-16 | 2009-01-20 | Ati Technologies Ulc | Method and apparatus for managing power consumption relating to a differential serial communication link |
US7171508B2 (en) * | 2004-08-23 | 2007-01-30 | Micron Technology, Inc. | Dual port memory with asymmetric inputs and outputs, device, system and method |
US7392331B2 (en) * | 2004-08-31 | 2008-06-24 | Micron Technology, Inc. | System and method for transmitting data packets in a computer system having a memory hub architecture |
TWI269975B (en) * | 2005-08-25 | 2007-01-01 | Inventec Corp | Method and device for automatically adjusting bus width |
US7447824B2 (en) * | 2005-10-26 | 2008-11-04 | Hewlett-Packard Development Company, L.P. | Dynamic lane management system and method |
US7584336B2 (en) | 2006-06-08 | 2009-09-01 | International Business Machines Corporation | Systems and methods for providing data modification operations in memory subsystems |
US7793030B2 (en) * | 2007-10-22 | 2010-09-07 | International Business Machines Corporation | Association of multiple PCI express links with a single PCI express port |
-
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- 2014-06-10 US US14/300,903 patent/US9274991B2/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9384818B2 (en) | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
CN104541256A (zh) * | 2012-09-29 | 2015-04-22 | 英特尔公司 | 智能远存储器带宽缩放 |
CN104541256B (zh) * | 2012-09-29 | 2017-05-17 | 英特尔公司 | 智能远存储器带宽缩放 |
Also Published As
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US7366864B2 (en) | 2008-04-29 |
KR20060130724A (ko) | 2006-12-19 |
US20080162861A1 (en) | 2008-07-03 |
US9274991B2 (en) | 2016-03-01 |
EP1730640A2 (en) | 2006-12-13 |
US8015384B2 (en) | 2011-09-06 |
TW200613973A (en) | 2006-05-01 |
KR100872007B1 (ko) | 2008-12-05 |
US8775764B2 (en) | 2014-07-08 |
TWI340897B (en) | 2011-04-21 |
US20140297974A1 (en) | 2014-10-02 |
US20110296077A1 (en) | 2011-12-01 |
US20090319750A1 (en) | 2009-12-24 |
WO2005089126A3 (en) | 2006-07-27 |
TW201120644A (en) | 2011-06-16 |
US20050210216A1 (en) | 2005-09-22 |
WO2005089126A2 (en) | 2005-09-29 |
JP2007528077A (ja) | 2007-10-04 |
US7596675B2 (en) | 2009-09-29 |
EP1730640A4 (en) | 2009-12-09 |
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