CN1941387A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN1941387A
CN1941387A CNA2006101157388A CN200610115738A CN1941387A CN 1941387 A CN1941387 A CN 1941387A CN A2006101157388 A CNA2006101157388 A CN A2006101157388A CN 200610115738 A CN200610115738 A CN 200610115738A CN 1941387 A CN1941387 A CN 1941387A
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D·奇丹巴尔拉奥
W·K·汉森
K·里姆
W·C·威尔
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GlobalFoundries Inc
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Abstract

本发明提供了一种用于在不同导电率的MOS晶体管的沟道中，使用高应力氮化物膜结合选择性绝缘体上半导体(SOI)器件结构产生应力的方法。具体地，提供了一种在浅沟槽隔离(STI)工艺中使用压缩和拉伸氮化物膜的方法。当此方法应用于选择性SOI结构时，可获得高应力值。

Description

半导体结构及其制造方法
技术领域
本发明涉及半导体器件制造，更具体地说，涉及在不同导电率的金属氧化物半导体(MOS)器件的沟道区域中使用高应力氮化物膜结合选择性绝缘体上半导体(SOI)器件结构产生应力的方法。特别地，本发明方法使用压缩和拉伸氮化物膜作为在浅沟槽隔离(STI)工艺中的双衬垫氮化物，以在MOS晶体管的沟道区域中引入应力。当此方法应用于选择性SOI器件结构时，可得到高应力值。本发明还涉及利用本申请的方法制造的半导体结构。
背景技术
常规栅极长度和栅极介质按比例缩放的互补金属氧化物半导体(CMOS)技术不再产生器件性能的期望改进。寄生电阻和电容成为利用每个新技术节点提高器件性能的基本限制因素。因此要求新的材料和器件结构以克服降低器件性能的这些基本的缩放障碍。
克服这些影响的一个方法是通过增加在沟道中的载流子的迁移率增加金属氧化物半导体场效应晶体管(MOSFET)的驱动电流。已公知，应用机械应力可以充分提高或降低半导体中的电子或空穴的迁移率；然而，还已知，电子和空穴对相同类型的应力具有不同的响应。例如，在电流流动的纵向上施加压缩应力对空穴迁移率有利，但是对电子迁移率有害。在纵向上施加拉伸应力对电子迁移率有利，但是对空穴迁移率有害。
目前，现有技术的状态是使用在硅化后沉积的应力氮化物衬里，以向沟道施加纵向应力并且因此增加CMOS器件的驱动电流。然而，急需发展一种集成方案，允许在合适的器件(nFET或pFET)上施加期望的应力(压缩或拉伸)以使CMOS技术的性能最大化。不幸的是，应力衬里的使用已经接近可以施加到CMOS器件的沟道上的应力大小的极限。
鉴于上述原因，需要提供一种可选方法以在沟道中获得具有期望应力类型(对pFET是压缩而对nFET是拉伸)的更高的应力大小(并且从而获得更高的迁移率)。
发明内容
本发明提供了一种在不同导电率的MOS晶体管的沟道中使用高应力氮化物膜结合选择性绝缘体上半导体(SOI)器件结构产生应力的方法。更具体地说，本发明提供一种在浅沟槽隔离(STI)工艺中使用压缩和拉伸氮化物膜作为双衬垫氮化物的方法。当本发明的此方法应用于选择性SOI器件结构时，可得到高应力值。“高应力值”指利用本发明方法可以在沟道中获得的应力值在约500MPa的量级或更大。更具体地说，本发明方法在器件沟道中提供从约600到约700MPa的应力范围。本发明方法可以应用于包括至少一个nFET器件区域和至少一个pFET器件区域的选择性SOI器件结构。
根据本发明，利用本发明方法可以将高应力值引入到MOS器件的沟道区域中，其中与选择性SOI器件结构结合在MOS隔离工艺(例如，STI工艺)中使用双应力氮化物膜作为衬垫氮化物膜。双应力氮化物衬里指在晶片上沉积拉伸和压缩两种氮化物膜覆盖期望的器件区域(例如nFET区域或pFET区域)。在常规体硅晶片中使用高应力氮化物膜作为隔离工艺的衬垫氮化物膜没有引入大量应变，这是选择性SOI结构重要的原因。
这里使用的术语“选择性SOI结构”，指包括顶含Si半导体层和底含Si半导体层的SOI衬底，其中部分顶含Si半导体层通过分离掩埋氧化物区域与含Si半导体层分开。根据本发明，仅在最终存在MOS器件的源极/漏极结的区域下面存在分离掩埋氧化物；在MOS器件的沟道区域下面不存在分离掩埋氧化物区域。
通过下面的步骤形成选择性SOI结构，首先在器件的结下面提供横向空隙，其将保持在其上引起的应力并且最终用形成结构的掩埋氧化物区域的氧化物填充。下面的横向空隙在器件的边缘处形成自由表面。自由表面围绕器件的边缘，当施加机械应力时允许表面处的含硅材料弯曲。拉伸氮化物膜提供将含Si材料的边缘向中心拉的横向力。作为来自氮化物衬垫的拉伸力的结果，含Si材料在边缘处向上弯曲，在含Si沟道的中心产生压缩应变。当压缩氮化物用作衬垫氮化物时，压缩氮化物膜在拉伸膜的相反方向提供力，并且作为结果，含Si材料在边缘处向下弯曲，在含Si沟道的中心产生拉伸应变。因此，为了在nFET和pFET上获得期望类型的应力，压缩衬垫氮化物用于nFET器件并且拉伸衬垫氮化物用于pFET器件。另外，为了获得高级别的应力，必须在随后具有选择性SOI结构的衬底上施加双应力衬垫氮化物，这对期望的驱动电流的增加是必须的。
总体上，本发明方法包括以下步骤：
提供含Si结构，具有至少一个第一器件区域和至少一个第二器件区域，所述结构在其中包括分离n掺杂区域；
形成第一材料叠层，包括第一衬垫氧化物和具有第一应力的构图第一氮化物膜，其中所述构图氮化物膜位于一个所述器件区域上；
形成第二材料叠层，包括第二衬垫氧化物和具有与所述第一应力的应力类型不同的第二应力的构图第二氮化物膜，其中所述构图第二氮化物膜位于不包括所述构图第一氮化物膜的一个所述器件区域上；
在所述第一和第二器件区域之间在所述第一和第二材料叠层中形成沟槽，所述沟槽向下延伸穿过至少一个所述n掺杂区域；
横向蚀刻所述n掺杂区域以在所述沟槽的每侧上形成保持所述上面的氮化物膜的应力的空隙；以及
用氧化物填充所述空隙和沟槽。
在填充步骤后，从该结构移除所述第一和第二材料叠层的各层并且形成nFET和pFET器件。根据本发明，在该结构处于压缩应力下的部分上形成pFET，而在该结构处于拉伸应力下的部分上形成nFET。该结构具有选择性SOI结构以便nFET和pFET的结位于填充空隙上面，而器件沟道不是如此。
除了上述方法外，本发明还提供了包括应力沟道区域的半导体结构，其应力在上述范围内。本发明的半导体结构包括：
选择性SOI衬底，包括顶和底含Si层，其在预定区域中由分离掩埋氧化物区域分开；
至少一个nFET，包括源极/漏极扩散区域和拉伸应变沟道，位于所述衬底的一部分上；以及
至少一个pFET，包括源极/漏极扩散区域和压缩应变沟道，位于所述衬底的另一部分上，其中所述至少一个nFET和所述至少一个pFET的所述源极/漏极扩散区域位于所述分离掩埋氧化物区域上，并且所述应变沟道不位于所述分离掩埋氧化物区域上。
附图说明
图1(通过截面图)示出了在本发明中利用的选择性SOI结构的示意图。
图2A-2B(通过截面图)示出了具有拉伸氮化硅SiN层(图2A)和压缩SiN层(图2B)的选择性SOI结构的示意图。
图3-11(通过截面图)示出了本发明的基本工艺步骤的示意图。
具体实施方式
下面将通过参考随后的描述和结合本申请的附图更详细地描述本发明，其提供了用于在不同导电率的MOS晶体管的沟道区域中产生应力的方法以及利用该方法形成的结构。注意，本申请的附图用于说明目的，因此没有按比例画出。
根据本发明，向MOS器件的沟道施加大应力有两个关键特征：(1)在STI隔离工艺中使用双应力氮化物膜作为衬垫氮化物以及，(2)必须向随后具有选择性SOI器件结构的结构施加双氮化物隔离工艺。双应力氮化物衬里指在晶片上沉积拉伸和压缩氮化物膜覆盖期望的器件区域(nFET或pFET)。在标准体硅晶片中使用高应力氮化物膜作为STI工艺的衬垫氮化物不能在硅中引入大量应变，这是选择性SOI结构重要的原因。选择性SOI结构允许在含Si材料下面形成横向空隙，其将最终包括器件的S/D结。下面的横向空隙在器件的边缘产生自由表面。围绕器件边缘的自由表面，当施加机械应力时，允许表面处的含硅材料弯曲。从隔离沟槽的底边延伸的这些横向空隙，保持通过上面的应力氮化物层引起的应力。另外，这些空隙随后由氧化物填充，形成选择性SOI衬底的掩埋氧化物区域。填充空隙的氧化物与填充沟槽隔离区域的氧化物接触。
图1示出了本发明使用的选择性SOI结构。具体地，SOI结构10包括顶含Si半导体层16和底含Si半导体层12，其中部分顶含Si半导体层16与底含Si半导体层12通过分离掩埋氧化物区域14隔开。根据本发明，分离掩埋氧化物区域14存在于最终将接收MOS晶体管的源极/漏极结的顶含Si半导体层的区域下面。在将存在MOS沟道的顶含Si半导体层的区域下面不存在分离掩埋氧化物。本发明中使用的选择性SOI结构先前已经在2003年6月26日提交的共同待审和共同受让的美国专利申请No.10/604,102和2004年1月8号提交的10/754,320中进行了描述，在此引入这两个的整个内容作为参考。注意，图1还示出了标记为STI的沟槽隔离区域的存在。
在当前的整个申请中使用的术语“含Si半导体”指任何包括硅的半导体材料。此含Si半导体材料的示意性实例包括，但不仅限于：Si，SiGe，SiGeC，SiC，Si/Si，Si/SiC，Si/SiGe，以及Si/SiGeC。优选，含Si层12和16都由Si构成。含Si层12和16可以掺杂或未掺杂。
SOI衬底的顶含Si层16优选具有从约50nm到约200nm的厚度，更优选具有从约75nm到约100nm的厚度。底含Si层12的厚度优选从约500μm到约750μm。分离掩埋氧化物区域14可以是结晶或非晶氧化物，优选具有从约30到约100nm的厚度。
图2A示出了当在表面上存在高拉伸应力(应力＞1GPa)时含Si材料如何弯曲。拉伸氮化物膜提供将含Si材料的边缘向中心拉的横向力。作为来自衬垫氮化物的拉伸力的结果，含Si材料在边缘向上弯曲，在含Si材料沟道的中心产生压缩应变。图2B示出了当压缩氮化物用作衬垫氮化物时的实例。压缩氮化物膜在拉伸膜的相反方向提供力并且作为结果含Si材料在边缘处向下弯曲，在含Si材料沟道的中心产生拉伸应变。因此，为了在nFET和pFET上获得期望类型的应力，压缩衬垫氮化物必须用于nFET器件，并且拉伸衬垫氮化物用于pFET。另外，为了获得对期望的驱动电流的增加所必须的高级别的应力，必须在衬底例如最终具有选择性SOI结构的结构上施加双应力衬垫氮化物。
现在参考图3-11，其通过截面图示出了本发明的基本工艺步骤。具体地，图3示出了在制造本发明的结构中使用的初始结构100。如所示，初始结构100包括体含Si衬底102，其中形成n掺杂区域104。该初始结构还包括第一器件区域101A和第二器件区域101B。第一器件区域101A是将要形成nFET或pFET的区域，而第二器件区域101B是将在随后形成与在第一器件区域中的FET相比具有相反导电类型的FET的区域。
n掺杂区域104是随后将在其中形成SOI衬底10的掩埋绝缘体14的区域。优选在体含Si衬底100的上表面处或附近形成n掺杂区域104。“附近”指n掺杂区域104的上表面在距体含Si衬底102的上表面约50nm或更小内。
利用掩蔽离子注入工艺形成n掺杂区域104。在后面的工艺流程中，对未掺杂区域具有选择性地蚀刻掉n掺杂区域104，形成空隙；该空隙将有助于保持由上面的应力氮化物膜引起的应力并且用形成选择性SOI衬底的分离掩埋氧化物区域的氧化物填充，。在形成n掺杂区域104中使用的注入核素优选As，P或Sb。在形成n掺杂区域104中使用的注入能量优选在从约5KeV到约20KeV的范围内，并且优选使用从约5E14到约2E15原子/cm2的离子剂量。在注入后退火，以使n型掺杂剂激活和扩散。体含Si衬底102将变为选择性SOI衬底10的底含Si衬底12，如图1中所示。
图4示出了在初始结构100顶部形成含Si层106后的结构。通过外延生长工艺形成含Si层106，用作如图1所示的选择性SOI衬底10的顶含Si层16。含Si层106的厚度变化依赖于SOI层的期望厚度和随后形成的源极/漏极结的深度。优选，含Si层106的厚度从约5到约100nm。
下一步，在结构上形成包括第一衬垫氧化物110和具有第一应力(拉伸或压缩)的第一氮化物膜112的第一材料叠层108，如图4所示。根据本发明，第一衬垫氧化物110位于第一氮化物膜112下面，在含Si层106的表面上。通过常规的热氧化工艺或如化学气相沉积、等离子体增强化学气相沉积、蒸发、化学溶液沉积和原子层沉积的常规沉积工艺形成第一衬垫氧化物110。第一衬垫氧化物110优选具有从约2到约10nm的厚度。利用如化学气相沉积(CVD)或等离子体增强化学气相沉积(PECVD)的常规沉积工艺形成具有第一应力的第一氮化物膜112。具有第一应力的第一氮化物膜112的厚度优选从约30到约100nm。
然后，从器件区域的一个上选择蚀刻掉具有第一应力的第一氮化物膜112，以便剩余第一氮化物膜112存在于对随后在其中形成的MOS器件的驱动电流具有最大效果的器件区域中。因此，例如，如果拉伸SiN膜用作膜112，选择蚀刻工艺从随后将形成nFET器件的器件区域移除拉伸SiN膜。如果压缩膜用作膜112，从随后将形成pFET器件的器件区域选择移除压缩SiN膜。通过首先向膜112的上表面提供光致抗蚀剂，并且随后利用常规光刻工艺在光致抗蚀剂中形成图形(即，将光致抗蚀剂在辐射图形中曝光并且利用常规抗蚀剂显影剂显影曝光后的光致抗蚀剂)，实现选择蚀刻。在光刻后，实施对氧化物具有选择性地移除氮化物的蚀刻工艺。该蚀刻工艺可以包括如反应离子蚀刻，等离子体蚀刻，离子束蚀刻或激光烧蚀的任何干蚀刻技术。可选地，还可以使用利用化学蚀刻剂的湿蚀刻技术。在本发明的一个实施例中，最终结构包括在未构图衬垫氧化物110的顶部的构图第一氮化物膜112，如图5所示。虽然在第二器件区域101B上示出了构图第一氮化物膜112，但是本发明还预期构图第一氮化物膜112仅位于第一器件区域101A上的情况。
下一步，在图5示出的结构上形成包括第二衬垫氧化物116和具有与第一氮化物膜112的应力类型不同的第二应力的第二氮化物膜118的第二材料层114。在第一衬垫氧化物110和构图氮化物膜112的暴露表面上形成第二衬垫氧化物116。第二衬垫氧化物116用于在随后构图第二氮化物膜118期间保护第一氮化物膜112。第二衬垫氧化物116和第二氮化物膜118的工艺和厚度类似于上面对第一衬垫氧化物110和第一氮化物膜112的那些描述。在图6中示出了包括第二材料层114的结构。
随后，构图图6中示出的结构(如上所述)以从先前包括第一氮化物膜112的结构区域移除第二氮化物膜118。在图7中示出了此结构。如图所示，第一器件区域101A仅包括，例如，第二氮化物膜118，而第二器件区域101B仅包括第一氮化物膜112。可以根据随后在具体区域形成的器件的类型转换第一和第二氮化物膜的位置。在一个实施例中，第一器件区域101A是由压缩氮化物膜118覆盖的nFET器件区域，而第二器件区域101B是由拉伸氮化物膜112覆盖的pFET器件区域。在另一个实施例中，第一器件区域101A是由拉伸氮化物膜118覆盖的pFET器件区域，而第二器件区域101B是由压缩氮化物膜112覆盖的nFET器件区域。再次强调，压缩膜导致沟道在拉伸应变下，而拉伸膜导致沟道在压缩应变下。
图8示出了在图7示出的结构中形成至少一个沟槽开口120后的结构。如图所示，在第一和第二器件区域(分别为101A和101B)之间形成沟槽开口120，向下延伸并且穿过至少一个未掺杂区域104。通过光刻和蚀刻形成沟槽开口120。蚀刻工艺可以包括单蚀刻(湿或干)或其组合。
图9示出了在执行可以从含Si材料中形成空隙122的结构移除n掺杂区域104的横向蚀刻工艺后形成的结构。此步骤对在位于空隙上的含Si材料中产生应力是必需的。利用与未掺杂半导体区域相比对n掺杂区域104具有选择性的任何蚀刻工艺执行横向蚀刻。例如，在本发明的此步骤中可以使用在氯，即Cl2中的干蚀刻。
注意，横向蚀刻后，表面附近的含Si材料自由弯曲，由拉伸和压缩氮化硅膜提供的力引起，如上面关于图2A和2B的描述。结果，在沟道区域中的含Si材料为高应变(即，在拉伸应变氮化硅膜下的含Si材料处在压缩应变下，而在压缩应变氮化硅膜下的含Si材料处在拉伸应变下)
下一步，如在图10中所示，利用如等离子体辅助化学气相沉积的常规沉积工艺用氧化物填充由上述横向蚀刻工艺产生的至少一个沟槽开口120和空隙122。注意，与沟槽隔离区域124连接的氧化物填充空隙123形成图1中示出的分离和掩埋氧化物区域14。沉积后，使用如化学机械抛光(CMP)和/或研磨的平整化工艺以完成沟槽隔离区域124的形成。提及的一个关键方面是在由氮化物膜产生的含Si沟道中的应变因为氧化物的填充保留在含Si材料中。
然后对图10中示出的结构进行另一个平整化工艺，该工艺从该结构移除任何残留的衬垫氧化物和氮化物膜并且其后利用常规的CMOS工艺在平整化结构的表面上形成的MOS器件。本发明的此步骤提供图11中示出的结构，其中在第一器件区域101A中形成第一导电类型的第一FET 126并且在第二器件区域101B中形成不同于第一导电类型的第二导电类型的第二FET 128。具体地，在处于拉伸应变下的区域中形成nFET而在处于压缩应变下的区域中形成pFET。
如上所述，利用本领域的技术人员公知的常规互补金属氧化物半导体(CMOS)工艺步骤形成FET。例如可以通过首先在SOI衬底的顶含Si层的上表面上形成栅极介质层130形成每个FET。本发明中使用的术语“栅极介质”指典型地用作MOSFET的栅极介质的如氧化物，氮化物或氧氮化物的任何绝缘材料。通过如化学气相沉积(CVD)，等离子体辅助CVD，原子层沉积，物理气相沉积，或其它类似沉积工艺的常规沉积工艺形成栅极介质130。可选地，可以通过热氧化，氮化或氧氮化工艺形成栅极介质130。优选栅极介质130的厚度从约1到约10nm。
在栅极介质形成后，在栅极介质的顶部形成栅极导体132。栅极导体132可以包括任何导电材料，包括例如，掺杂多晶硅，导电元素金属，导电元素金属的合金，导电元素金属的硅化物，导电元素金属的氮化物，或其任意组合。在栅极导体132的内部或顶部形成扩散阻挡层和/或介质覆层。可以通过如CVD，等离子体辅助CVD，蒸发，溅射，电镀或其它类似沉积工艺的常规沉积工艺形成栅极导体132。当应用多晶硅时，多晶硅栅极导体是原位或通过沉积并随后进行离子注入形成的掺杂材料。栅极导体132的厚度优选从约100到约300nm。
注意，不同导电率的FET的栅极介质和栅极导体可以由相同的材料构成或者使用不同的栅极介质和/或栅极导体。
在形成栅极导体之后，通过光刻和蚀刻构图栅极导体特别是栅极介质。下一步，优选在至少构图栅极导体的暴露侧壁上形成(通过沉积和蚀刻)绝缘隔离物(未示出)。在形成隔离物之后，在SOI衬底的顶含Si层中通过离子注入和退火形成源极/漏极扩散区域134。如所示，源极/漏极区域134位于SOI结构的氧化物填充空隙区域上(例如，掩埋氧化物区域)。
退火引起注入掺杂剂的扩散。扩散的范围决定在SOI衬底的顶含Si层中的沟道区域的长度。这样设置沟道区域136以便其下面没有掩埋氧化物存在。
应该强调，不必需要使用常规应力衬里和/或镶嵌应力区域即可在沟道区域136中产生应力。如上所述，通过在包括双应力氮化物衬垫膜的结构中提供横向空隙在含Si材料中形成高应力沟道。从该结构移除在STI区域的形成中使用的这些衬垫膜，并且随后在其上形成CMOS器件。
虽然这里参考具体的实施例，特征和方面描述了本发明，应该知道，本发明没有因此受限制，而是有用地延伸到其它修改，变化，应用和实施例，并且因此所有这样的其它修改，变化，应用和实施例都被认为在本发明的精神和范围内。

Claims (20)

1.一种半导体结构，包括：
选择性SOI衬底，包括顶和底含Si层，其在预定区域中由分离掩埋氧化物区域分开；
至少一个nFET，包括源极/漏极扩散区域和拉伸应变沟道，位于所述衬底的一部分上；以及
至少一个pFET，包括源极/漏极扩散区域和压缩应变沟道，位于所述衬底的另一部分上，其中所述至少一个nFET和所述至少一个pFET的所述源极/漏极扩散区域位于所述分离掩埋氧化物区域上，并且所述应变沟道不位于所述分离掩埋氧化物区域上。
2.根据权利要求1的半导体结构，其中所述顶含Si层包括外延含Si层。
3.根据权利要求1的半导体结构，其中所述底含Si层是体含Si材料。
4.根据权利要求1的半导体结构，其中所述分离掩埋氧化物区域具有从约30到约100nm的厚度。
5.根据权利要求1的半导体结构，其中所述分离掩埋氧化物区域从氧化物填充沟槽隔离区域的底边延伸。
6.根据权利要求1的半导体结构，其中所述至少一个pFET和所述至少一个nFET每个都包括栅极介质和栅极导体。
7.根据权利要求6的半导体结构，其中所述栅极介质包括绝缘氧化物，氮化物或氧氮化物。
8.根据权利要求6的半导体结构，其中所述栅极导体包括掺杂多晶硅，导电元素金属，导电元素金属的合金，导电元素金属的硅化物，导电元素金属的氮化物或其组合。
9.根据权利要求1的半导体结构，其中所述应变沟道具有约500MPa或更大的应力值。
10.根据权利要求9的半导体结构，其中所述应力值从约600到约700MPa。
11.根据权利要求9的半导体结构，其中获得所述应力值不需要在所述至少一个nFET或所述至少一个pFET周围存在上面的应力氮化物膜。
12.一种制造半导体结构的方法，包括如下步骤：
提供含Si结构，具有至少一个第一器件区域和至少一个第二器件区域，所述结构在其中包括分离n掺杂区域；
形成第一材料叠层，包括第一衬垫氧化物和具有第一应力的构图第一氮化物膜，其中所述构图氮化物膜位于一个所述器件区域上；
形成第二材料叠层，包括第二衬垫氧化物和具有与所述第一应力的应力类型不同的第二应力的构图第二氮化物膜，其中所述构图第二氮化物膜位于不包括所述构图第一氮化物膜的一个所述器件区域上；
在所述第一和第二器件区域之间在所述第一和第二材料叠层中形成沟槽，所述沟槽向下延伸穿过至少一个所述n掺杂区域；
横向蚀刻所述n掺杂区域以在所述沟槽的每侧上形成保持所述上面的氮化物膜的应力的空隙；以及
用氧化物填充所述空隙和沟槽。
13.根据权利要求12的方法，其中所述形成所述含Si结构的步骤包括在体含Si衬底中在其表面处或附近注入所述n掺杂区域，并且在所述体含Si衬底上形成外延含硅层。
14.根据权利要求13的方法，其中所述注入步骤包括掩蔽离子注入工艺，其中使用As，P或Sb作为n型掺杂剂。
15.根据权利要求13的方法，其中在从约5到约20keV的能量下执行所述注入步骤，并且使用从约5E14到约2E15原子/cm2的离子剂量。
16.根据权利要求12的方法，其中所述n掺杂区域位于体含Si衬底的表面处或附近。
17.根据权利要求11的方法，其中所述构图第一氮化物膜位于将制造nFET的器件区域中，所述构图第一氮化物膜具有压缩应变，并且所述构图第二氮化物膜位于将制造pFET的器件区域中，所述构图第二氮化物膜具有拉伸应变。
18.根据权利要求17的方法，还包括从所述含Si结构移除所述第一和第二材料叠层并且形成至少一个pFET和至少一个nFET，其中在包括所述构图第二氮化物膜的区域中形成所述至少一个pFET并且在包括所述构图第一氮化物膜的区域中形成所述至少一个nFET。
19.根据权利要求12的方法，其中所述构图第一氮化物膜位于将制造pFET的器件区域中，所述构图第一氮化物膜具有拉伸应变，并且所述构图第二氮化物膜位于将制造nFET的器件区域中，所述构图第二氮化物膜具有压缩应变。
20.根据权利要求19的方法，还包括从所述含Si结构移除所述第一和第二材料叠层并且形成至少一个pFET和至少一个nFET，其中在包括所述构图第一氮化物膜的区域中形成所述至少一个pFET并且在包括所述构图第二氮化物膜的区域中形成所述至少一个nFET。
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