DE10113110A1 - Filmmaterial mit niedriger Dielektrizitätskonstante, Film und Halbleitervorrichtung, bei denen solch ein Material verwendet wird - Google Patents
Filmmaterial mit niedriger Dielektrizitätskonstante, Film und Halbleitervorrichtung, bei denen solch ein Material verwendet wirdInfo
- Publication number
- DE10113110A1 DE10113110A1 DE2001113110 DE10113110A DE10113110A1 DE 10113110 A1 DE10113110 A1 DE 10113110A1 DE 2001113110 DE2001113110 DE 2001113110 DE 10113110 A DE10113110 A DE 10113110A DE 10113110 A1 DE10113110 A1 DE 10113110A1
- Authority
- DE
- Germany
- Prior art keywords
- film
- porous material
- hydrocarbon group
- dielectric constant
- siloxane resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09D—COATING COMPOSITIONS, e.g. PAINTS, VARNISHES OR LACQUERS; FILLING PASTES; CHEMICAL PAINT OR INK REMOVERS; INKS; CORRECTING FLUIDS; WOODSTAINS; PASTES OR SOLIDS FOR COLOURING OR PRINTING; USE OF MATERIALS THEREFOR
- C09D183/00—Coating compositions based on macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon, with or without sulfur, nitrogen, oxygen, or carbon only; Coating compositions based on derivatives of such polymers
- C09D183/04—Polysiloxanes
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09D—COATING COMPOSITIONS, e.g. PAINTS, VARNISHES OR LACQUERS; FILLING PASTES; CHEMICAL PAINT OR INK REMOVERS; INKS; CORRECTING FLUIDS; WOODSTAINS; PASTES OR SOLIDS FOR COLOURING OR PRINTING; USE OF MATERIALS THEREFOR
- C09D183/00—Coating compositions based on macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon, with or without sulfur, nitrogen, oxygen, or carbon only; Coating compositions based on derivatives of such polymers
- C09D183/16—Coating compositions based on macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon, with or without sulfur, nitrogen, oxygen, or carbon only; Coating compositions based on derivatives of such polymers in which all the silicon atoms are connected by linkages other than oxygen atoms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
- H01L21/3121—Layers comprising organo-silicon compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
- H01L21/3121—Layers comprising organo-silicon compounds
- H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31652—Of asbestos
- Y10T428/31663—As siloxane, silicone or silane
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Life Sciences & Earth Sciences (AREA)
- Materials Engineering (AREA)
- Wood Science & Technology (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Laminated Bodies (AREA)
- Compositions Of Macromolecular Compounds (AREA)
Abstract
Description
Claims (17)
(R1 bis R3 verkörpern Wasserstoff, Sauerstoff oder eine einwertige Kohlenwasserstoffgruppe, X verkörpert Wasserstoff oder Silicium, und n1 ist eine ganze Zahl zwischen 5 und 200) oder durch:
(R4 bis R7 verkörpern Wasserstoff, Fluor oder eine einwer tige Kohlenwasserstoffgruppe, n2 ist eine ganze Zahl zwi schen 5 und 100, wobei wenigstens eines von R4 bis R7 Was serstoff ist) und das Polycarbosilan durch eine allgemeine chemische Formel ausgedrückt wird:
(R8 und R9 verkörpern Wasserstoff oder eine einwertige Kohlenwasserstoffgruppe, und m ist eine ganze Zahl zwischen 20 und 1000).
einem Halbleitersubstrat; und
einem Film mit niedriger Dielektrizitätskonstante, der aus Material mit niedriger Dielektrizitätskonstante hergestellt ist, das Siloxanharz und Polycarbolisan enthält, das mit dem Siloxanharz verbunden ist.
einem Halbleitersubstrat;
einem ersten Film, der auf einer Oberfläche des Halbleitersubstrates gebildet ist und aus einem ersten siliciumoxidhaltigen porösen Material hergestellt ist; und
einem zweiten Film, der direkt auf dem ersten Film gebildet ist und aus einem zweiten siliciumoxidhaltigen porösen Material gebildet ist, welches siliciumoxidhaltige poröse Material eine Ätzrate hat, die sich von einer Ätzrate des ersten siliciumoxidhaltigen porösen Materials unter derselben Ätzbildung unterscheidet.
(R10 bis R12 verkörpern Wasserstoff, Sauerstoff oder eine einwertige Kohlenwasserstoffgruppe, n1 verkörpert eine ganze Zahl zwischen 5 und 200, und X verkörpert Wasserstoff oder Silicium) oder durch:
(R13 bis R16 verkörpern Wasserstoff, Fluor oder eine einwer tige Kohlenwasserstoffgruppe, n2 ist eine ganze Zahl zwi schen 5 und 100, wobei wenigstens eines von R13 bis R16 Wasserstoff ist).
einen Graben, der in dem zweiten Film gebildet ist und eine Tiefe hat, die größer als eine Dicke des zweiten Films ist;
ein Durchgangsloch, das durch den ersten Film gebildet ist, welches Durchgangsloch durch den Graben teilweise überlappt wird; und
eine leitfähige Verdrahtungsleitung, die ein Inneres des Durchgangslochs und des Grabens vergräbt.
einen Graben, der in dem zweiten Film gebildet ist und eine Tiefe hat, die größer als eine Dicke des zweiten Films ist;
ein Durchgangsloch, das durch den ersten Film gebildet ist, welches Durchgangsloch durch den Graben teilweise überlappt wird; und
eine leitfähige Verdrahtungsleitung, die ein Inneres des Durchgangslochs und des Grabens vergräbt.
Bilden eines ersten Films aus einem ersten silicium oxidhaltigen porösen Material auf einer Oberfläche eines Halbleitersubstrates;
Bilden eines zweiten Films aus einem zweiten silicium oxidhaltigen porösen Material direkt auf einer Oberfläche des ersten Films, wobei eine Ätzrate des zweiten silicium oxidhaltigen porösen Materials schneller als eine Ätzrate des ersten siliciumoxidhaltigen porösen Materials ist;
Bilden eines Grabens mit einer Tiefe, die größer als eine Dicke des zweiten Films ist, und eines Durchgangslochs durch den ersten Film, welches Loch durch den Graben teil weise überlappt wird; und
Vergraben eines leitfähigen Materials in dem Durch gangsloch und dem Graben.
Bilden eines Lochs durch die ersten und zweiten Filme;
und
Bilden des Grabens durch Ätzen einer Zone, die durch das Loch teilweise überlappt wird, ab einer oberen Oberflä che des zweiten Films wenigstens bis zu einer oberen Ober fläche des ersten Films.
einem Halbleitersubstrat;
einem ersten Film, der auf einer Oberfläche des Halb leitersubstrates gebildet ist und aus einem ersten silicium oxidhaltigen porösen Material hergestellt ist; und
einem zweiten Film, der direkt auf dem ersten Film ge bildet ist und aus einem zweiten siliciumoxidhaltigen porö sen Material hergestellt ist,
bei der die ersten und zweiten siliciumoxidhaltigen po rösen Materialien Siloxanharz enthalten, das durch eine allgemeine chemische Formel ausgedrückt wird:
(R10 bis R12 verkörpern Wasserstoff, Sauerstoff oder eine einwertige Kohlenwasserstoffgruppe, n1 verkörpert eine ganze Zahl zwischen 5 und 200, und X verkörpert Wasserstoff oder Silicium) oder durch:
(R13 bis R16 verkörpern Wasserstoff, Fluor oder eine einwer tige Kohlenwasserstoffgruppe, n2 ist eine ganze Zahl zwi schen 5 und 100, wobei wenigstens eines von R13 bis R16 Wasserstoff ist),
bei dem ersten siliciumoxidhaltigen porösen Material wenigstens eines von R10 bis R12 eine Phenylgruppe oder eine Kohlenwasserstoffgruppe mit zwei bis fünf Kohlenstoffatomen ist oder wenigstens eines von R13 bis R16 eine Phenylgruppe oder eine Kohlenwasserstoffgruppe mit zwei bis fünf Kohlen stoffatomen ist und bei dem zweiten siliciumoxidhaltigen porösen Material keines von R10 bis R12 eine Kohlenwasser stoffgruppe mit zwei oder mehr Kohlenstoffatomen ist oder keines von R13 bis R16 eine Kohlenwasserstoffgruppe mit zwei oder mehr Kohlenstoffatomen ist.
Bilden eines ersten Films aus einem ersten silicium oxidhaltigen porösen Material auf einer Oberfläche eines Halbleitersubstrates;
Bilden eines zweiten Films aus einem zweiten silicium oxidhaltigen porösen Material direkt auf einer Oberfläche des ersten Films;
Bilden eines Grabens mit einer Tiefe, die größer als eine Dicke des zweiten Films ist, und eines Durchgangslochs durch den ersten Film, welches Durchgangsloch durch den Graben teilweise überlappt wird; und
Vergraben eines leitfähigen Materials in dem Durch gangsloch und dem Graben,
bei dem die ersten und zweiten siliciumoxidhaltigen porösen Materialien Siloxanharz enthalten, das durch eine allgemeine chemische Formel ausgedrückt wird:
(R10 bis R12 verkörpern Wasserstoff, Sauerstoff oder eine einwertige Kohlenwasserstoffgruppe, n1 verkörpert eine ganze Zahl zwischen 5 und 200, und X verkörpert Wasserstoff oder Silicium) oder durch:
(R13 bis R16 verkörpern Wasserstoff, Fluor oder eine einwer tige Kohlenwasserstoffgruppe, n2 ist eine ganze Zahl zwi schen 5 und 100, wobei wenigstens eines von R13 bis R16 Wasserstoff ist),
bei dem ersten siliciumoxidhaltigen porösen Material wenigstens eines von R10 bis R12 eine Phenylgruppe oder eine Kohlenwasserstoffgruppe mit zwei bis fünf Kohlenstoffatomen ist oder wenigstens eines von R13 bis R16 eine Phenylgruppe oder eine Kohlenwasserstoffgruppe mit zwei bis fünf Kohlen stoffatomen ist und bei dem zweiten siliciumoxidhaltigen porösen Material keines von R10 bis R12 eine Kohlenwasser stoffgruppe mit zwei oder mehr Kohlenstoffatomen ist oder keines von R13 bis R16 eine Kohlenwasserstoffgruppe mit zwei oder mehr Kohlenstoffatomen ist.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2001164913 DE10164913B8 (de) | 2000-03-29 | 2001-03-15 | Halbleitervorrichtungen mit Filmmaterial mit niedriger Dielektrizitätskonstante und Verfahren zu ihrer Herstellung |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000092138 | 2000-03-29 | ||
JP2000-092138P | 2000-03-29 | ||
JP2001-002113P | 2001-01-10 | ||
JP2001002113A JP3604007B2 (ja) | 2000-03-29 | 2001-01-10 | 低誘電率被膜形成材料、及びそれを用いた被膜と半導体装置の製造方法 |
DE2001164913 DE10164913B8 (de) | 2000-03-29 | 2001-03-15 | Halbleitervorrichtungen mit Filmmaterial mit niedriger Dielektrizitätskonstante und Verfahren zu ihrer Herstellung |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10113110A1 true DE10113110A1 (de) | 2001-10-25 |
DE10113110B4 DE10113110B4 (de) | 2009-01-02 |
Family
ID=26588767
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2001113110 Expired - Fee Related DE10113110B4 (de) | 2000-03-29 | 2001-03-15 | Filmmaterial und Film mit niedriger Dielektrizitätskonstante |
DE2001164913 Expired - Fee Related DE10164913B8 (de) | 2000-03-29 | 2001-03-15 | Halbleitervorrichtungen mit Filmmaterial mit niedriger Dielektrizitätskonstante und Verfahren zu ihrer Herstellung |
DE2001165028 Expired - Fee Related DE10165028B4 (de) | 2000-03-29 | 2001-03-15 | Halbleitervorrichtung mit einem Halbleitersubstrat und einem Film mit niedriger Dielektrizitätskonstante |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2001164913 Expired - Fee Related DE10164913B8 (de) | 2000-03-29 | 2001-03-15 | Halbleitervorrichtungen mit Filmmaterial mit niedriger Dielektrizitätskonstante und Verfahren zu ihrer Herstellung |
DE2001165028 Expired - Fee Related DE10165028B4 (de) | 2000-03-29 | 2001-03-15 | Halbleitervorrichtung mit einem Halbleitersubstrat und einem Film mit niedriger Dielektrizitätskonstante |
Country Status (4)
Country | Link |
---|---|
US (3) | US6613834B2 (de) |
JP (1) | JP3604007B2 (de) |
KR (1) | KR100703763B1 (de) |
DE (3) | DE10113110B4 (de) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006029334A1 (de) * | 2006-02-14 | 2007-08-16 | Fujitsu Ltd., Kawasaki | Material zum Ausbilden eines Belichtungslicht blockierenden Films, mehrschichtige Verbindungsstruktur und Herstellungsverfahren dafür, und Halbleitervorrichtung |
US7358299B2 (en) | 2001-03-23 | 2008-04-15 | Fujitsu Limited | Silicon-based composition, low dielectric constant film, semiconductor device, and method for producing low dielectric constant film |
DE102006062728B4 (de) * | 2006-02-14 | 2010-04-29 | Fujitsu Ltd., Kawasaki | Halbleitervorrichtung und Herstellungsverfahren dafür |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6824879B2 (en) * | 1999-06-10 | 2004-11-30 | Honeywell International Inc. | Spin-on-glass anti-reflective coatings for photolithography |
KR100795714B1 (ko) * | 2000-08-21 | 2008-01-21 | 다우 글로벌 테크놀로지스 인크. | 마이크로일렉트로닉 장치의 제조에 있어서 유기 중합체유전체용 하드마스크로서의 유기 규산염 수지 |
JP3886779B2 (ja) | 2001-11-02 | 2007-02-28 | 富士通株式会社 | 絶縁膜形成用材料及び絶縁膜の形成方法 |
US6816031B1 (en) * | 2001-12-04 | 2004-11-09 | Formfactor, Inc. | Adjustable delay transmission line |
JP4863182B2 (ja) * | 2002-01-31 | 2012-01-25 | 東ソー株式会社 | 有機シラン化合物を含んでなる絶縁膜用材料、その製造方法および半導体デバイス |
JP4063619B2 (ja) | 2002-03-13 | 2008-03-19 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
TWI300971B (en) * | 2002-04-12 | 2008-09-11 | Hitachi Ltd | Semiconductor device |
JP3974023B2 (ja) | 2002-06-27 | 2007-09-12 | 富士通株式会社 | 半導体装置の製造方法 |
AU2003295786A1 (en) * | 2002-11-21 | 2004-06-18 | University Of Florida | Elastomeric polymers |
JP3951124B2 (ja) * | 2002-12-06 | 2007-08-01 | Jsr株式会社 | 絶縁膜 |
JP2004253791A (ja) | 2003-01-29 | 2004-09-09 | Nec Electronics Corp | 絶縁膜およびそれを用いた半導体装置 |
JP2004235548A (ja) | 2003-01-31 | 2004-08-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US7098149B2 (en) * | 2003-03-04 | 2006-08-29 | Air Products And Chemicals, Inc. | Mechanical enhancement of dense and porous organosilicate materials by UV exposure |
TW200428586A (en) * | 2003-04-08 | 2004-12-16 | Matsushita Electric Ind Co Ltd | Electronic device and the manufacturing method thereof |
US20050035455A1 (en) * | 2003-08-14 | 2005-02-17 | Chenming Hu | Device with low-k dielectric in close proximity thereto and its method of fabrication |
US8053159B2 (en) | 2003-11-18 | 2011-11-08 | Honeywell International Inc. | Antireflective coatings for via fill and photolithography applications and methods of preparation thereof |
JP3666751B2 (ja) * | 2003-11-28 | 2005-06-29 | 東京エレクトロン株式会社 | 絶縁膜の形成方法及び絶縁膜形成システム |
JP2005175060A (ja) * | 2003-12-09 | 2005-06-30 | Jsr Corp | 絶縁膜およびその形成方法、ならびに膜形成用組成物 |
JP4737361B2 (ja) * | 2003-12-19 | 2011-07-27 | Jsr株式会社 | 絶縁膜およびその形成方法 |
WO2005068539A1 (ja) * | 2004-01-16 | 2005-07-28 | Jsr Corporation | ポリマーの製造方法、ポリマー、絶縁膜形成用組成物、絶縁膜の製造方法、および絶縁膜 |
JP5105041B2 (ja) * | 2004-01-16 | 2012-12-19 | Jsr株式会社 | 絶縁膜形成用組成物およびその製造方法、ならびにシリカ系絶縁膜およびその形成方法 |
EP1719793A4 (de) * | 2004-02-26 | 2009-05-20 | Jsr Corp | Polymer und herstellungsverfahren dafür, zusammensetzung zur bildung eines isolierfilms und herstellungsverfahren dafür |
JP2005272816A (ja) * | 2004-02-26 | 2005-10-06 | Jsr Corp | ポリマーおよびその製造方法、絶縁膜形成用組成物、ならびに絶縁膜およびその形成方法 |
JP5110238B2 (ja) | 2004-05-11 | 2012-12-26 | Jsr株式会社 | 絶縁膜形成用組成物およびその製造方法、ならびにシリカ系絶縁膜およびその形成方法 |
JP5110239B2 (ja) * | 2004-05-11 | 2012-12-26 | Jsr株式会社 | 有機シリカ系膜の形成方法、膜形成用組成物 |
US7776736B2 (en) * | 2004-05-11 | 2010-08-17 | Tokyo Electron Limited | Substrate for electronic device capable of suppressing fluorine atoms exposed at the surface of insulating film from reacting with water and method for processing same |
WO2005108469A1 (ja) * | 2004-05-11 | 2005-11-17 | Jsr Corporation | 有機シリカ系膜の形成方法、有機シリカ系膜、配線構造体、半導体装置、および膜形成用組成物 |
US7439111B2 (en) * | 2004-09-29 | 2008-10-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20060176683A1 (en) * | 2005-02-08 | 2006-08-10 | Chen-Cheng Chien | Outdoor light |
US7345343B2 (en) * | 2005-08-02 | 2008-03-18 | Texas Instruments Incorporated | Integrated circuit having a top side wafer contact and a method of manufacture therefor |
US8362135B2 (en) * | 2005-08-02 | 2013-01-29 | Rory E. Brennan | Compositions and methods for adhesion |
JP4616154B2 (ja) | 2005-11-14 | 2011-01-19 | 富士通株式会社 | 半導体装置の製造方法 |
JP2007273494A (ja) * | 2006-03-30 | 2007-10-18 | Fujitsu Ltd | 絶縁膜形成用組成物及び半導体装置の製造方法 |
US7927664B2 (en) * | 2006-08-28 | 2011-04-19 | International Business Machines Corporation | Method of step-and-flash imprint lithography |
WO2008036662A2 (en) * | 2006-09-18 | 2008-03-27 | Starfire Systems, Inc. | Process for preparing siloxane-based compositions and derivative compositions thereof |
US8642246B2 (en) | 2007-02-26 | 2014-02-04 | Honeywell International Inc. | Compositions, coatings and films for tri-layer patterning applications and methods of preparation thereof |
JP5071474B2 (ja) * | 2007-03-13 | 2012-11-14 | 富士通株式会社 | 半導体装置および半導体装置の製造方法 |
US7682989B2 (en) * | 2007-05-18 | 2010-03-23 | Texas Instruments Incorporated | Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better dielectric stack adhesion |
US7867689B2 (en) * | 2007-05-18 | 2011-01-11 | International Business Machines Corporation | Method of use for photopatternable dielectric materials for BEOL applications |
US8470516B2 (en) * | 2007-05-18 | 2013-06-25 | International Business Machines Corporation | Method of forming a relief pattern by e-beam lithography using chemical amplification, and derived articles |
US7919225B2 (en) * | 2008-05-23 | 2011-04-05 | International Business Machines Corporation | Photopatternable dielectric materials for BEOL applications and methods for use |
US8557877B2 (en) | 2009-06-10 | 2013-10-15 | Honeywell International Inc. | Anti-reflective coatings for optically transparent substrates |
JP5609142B2 (ja) * | 2010-02-19 | 2014-10-22 | 住友ベークライト株式会社 | 絶縁膜、積層体、半導体装置および半導体装置の製造方法 |
JP2013517616A (ja) * | 2010-01-06 | 2013-05-16 | アプライド マテリアルズ インコーポレイテッド | 酸化物ライナを使用する流動可能な誘電体 |
KR101277722B1 (ko) * | 2010-07-14 | 2013-06-24 | 제일모직주식회사 | 하이브리드 실록산 중합체, 상기 하이브리드 실록산 중합체로부터 형성된 봉지재 및 상기 봉지재를 포함하는 전자 소자 |
JP5567926B2 (ja) * | 2010-07-29 | 2014-08-06 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8864898B2 (en) | 2011-05-31 | 2014-10-21 | Honeywell International Inc. | Coating formulations for optical elements |
US9941214B2 (en) * | 2013-08-15 | 2018-04-10 | Taiwan Semiconductor Manufacturing Company | Semiconductor devices, methods of manufacture thereof, and inter-metal dielectric (IMD) structures |
KR101537660B1 (ko) * | 2013-08-27 | 2015-07-17 | 한국세라믹기술원 | 세라믹 복합 섬유를 포함하는 열 계면 재료 및 그 제조방법 |
EP3194502A4 (de) | 2015-04-13 | 2018-05-16 | Honeywell International Inc. | Polysiloxanformulierungen und beschichtungen für optoelektronische anwendungen |
US9818684B2 (en) * | 2016-03-10 | 2017-11-14 | Amkor Technology, Inc. | Electronic device with a plurality of redistribution structures having different respective sizes |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6080844A (ja) * | 1983-10-11 | 1985-05-08 | Nippon Telegr & Teleph Corp <Ntt> | パタ−ン形成用材料及びパタ−ン形成方法 |
US5264319A (en) * | 1985-05-10 | 1993-11-23 | Hitachi, Ltd. | Photosensitive resin composition having high resistance to oxygen plasma, containing alkali-soluble organosilicon polymer and photosensitive dissolution inhibitor |
US4745169A (en) * | 1985-05-10 | 1988-05-17 | Hitachi, Ltd. | Alkali-soluble siloxane polymer, silmethylene polymer, and polyorganosilsesquioxane polymer |
JPH0570119A (ja) | 1991-09-12 | 1993-03-23 | Kawasaki Steel Corp | 半導体装置の製造方法 |
JP3153586B2 (ja) * | 1991-10-15 | 2001-04-09 | 鐘淵化学工業株式会社 | ケイ素系ハイブリッド材料 |
JP3296440B2 (ja) * | 1991-10-17 | 2002-07-02 | 鐘淵化学工業株式会社 | ケイ素系ハイブリッド材料 |
JPH05117392A (ja) * | 1991-10-30 | 1993-05-14 | Fujitsu Ltd | 有機ケイ素重合体およびレジスト組成物 |
JP3418458B2 (ja) * | 1993-08-31 | 2003-06-23 | 富士通株式会社 | 半導体装置の製造方法 |
DE19600305C2 (de) | 1996-01-05 | 2001-05-03 | Siemens Ag | Herstellverfahren für eine Siliziumdioxid-Schicht auf einer Topographie sowie eine nach diesem Verfahren hergestellte Siliziumdioxidschicht |
US6077792A (en) * | 1997-07-14 | 2000-06-20 | Micron Technology, Inc. | Method of forming foamed polymeric material for an integrated circuit |
US6043147A (en) * | 1997-12-18 | 2000-03-28 | Advanced Micro Devices, Inc. | Method of prevention of degradation of low dielectric constant gap-fill material |
JPH11233500A (ja) | 1998-02-13 | 1999-08-27 | Matsushita Electric Ind Co Ltd | 絶縁膜の形成方法及びそれを用いた半導体装置と半導体装置製造方法 |
US6232235B1 (en) * | 1998-06-03 | 2001-05-15 | Motorola, Inc. | Method of forming a semiconductor device |
US6127258A (en) * | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
JP2000150516A (ja) * | 1998-09-02 | 2000-05-30 | Tokyo Electron Ltd | 半導体装置の製造方法 |
US6225238B1 (en) * | 1999-06-07 | 2001-05-01 | Allied Signal Inc | Low dielectric constant polyorganosilicon coatings generated from polycarbosilanes |
US6318124B1 (en) * | 1999-08-23 | 2001-11-20 | Alliedsignal Inc. | Nanoporous silica treated with siloxane polymers for ULSI applications |
JP4756526B2 (ja) * | 1999-10-25 | 2011-08-24 | 富士通株式会社 | 多孔質化低誘電率絶縁膜の形成方法及び該方法で形成された多孔質化低誘電率絶縁膜及び該多孔質化低誘電率絶縁膜を用いた半導体装置 |
US6677679B1 (en) * | 2001-02-06 | 2004-01-13 | Advanced Micro Devices, Inc. | Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers |
JP5930695B2 (ja) * | 2011-12-16 | 2016-06-08 | 旭化成ホームズ株式会社 | 機能パネル固定具 |
-
2001
- 2001-01-10 JP JP2001002113A patent/JP3604007B2/ja not_active Expired - Fee Related
- 2001-03-05 US US09/797,865 patent/US6613834B2/en not_active Expired - Lifetime
- 2001-03-09 KR KR1020010012331A patent/KR100703763B1/ko not_active IP Right Cessation
- 2001-03-15 DE DE2001113110 patent/DE10113110B4/de not_active Expired - Fee Related
- 2001-03-15 DE DE2001164913 patent/DE10164913B8/de not_active Expired - Fee Related
- 2001-03-15 DE DE2001165028 patent/DE10165028B4/de not_active Expired - Fee Related
-
2003
- 2003-05-30 US US10/448,092 patent/US6958525B2/en not_active Expired - Lifetime
-
2005
- 2005-08-17 US US11/205,128 patent/US7235866B2/en not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7358299B2 (en) | 2001-03-23 | 2008-04-15 | Fujitsu Limited | Silicon-based composition, low dielectric constant film, semiconductor device, and method for producing low dielectric constant film |
DE10164943B4 (de) * | 2001-03-23 | 2009-02-26 | Fujitsu Ltd., Kawasaki | Halbleitervorrichtung, umfassend als Zwischenschicht-Isolationsfilm einen Film mit niedriger Dielektrizitätskonstante |
DE10154771B4 (de) * | 2001-03-23 | 2013-02-14 | Fujitsu Ltd. | Zusammensetzung auf Siliziumbasis, Film mit niedriger Dielektrizitätskonstante und Verfahren zu dessen Herstellung |
DE102006029334A1 (de) * | 2006-02-14 | 2007-08-16 | Fujitsu Ltd., Kawasaki | Material zum Ausbilden eines Belichtungslicht blockierenden Films, mehrschichtige Verbindungsstruktur und Herstellungsverfahren dafür, und Halbleitervorrichtung |
DE102006062728B4 (de) * | 2006-02-14 | 2010-04-29 | Fujitsu Ltd., Kawasaki | Halbleitervorrichtung und Herstellungsverfahren dafür |
US7728065B2 (en) | 2006-02-14 | 2010-06-01 | Fujitsu Limited | Material for forming exposure light-blocking film, multilayer interconnection structure and manufacturing method thereof, and semiconductor device |
US7830012B2 (en) | 2006-02-14 | 2010-11-09 | Fujitsu Limited | Material for forming exposure light-blocking film, multilayer interconnection structure and manufacturing method thereof, and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2001345317A (ja) | 2001-12-14 |
KR100703763B1 (ko) | 2007-04-05 |
DE10165028B4 (de) | 2010-01-07 |
JP3604007B2 (ja) | 2004-12-22 |
DE10113110B4 (de) | 2009-01-02 |
US7235866B2 (en) | 2007-06-26 |
US20060022357A1 (en) | 2006-02-02 |
DE10164913B4 (de) | 2008-06-12 |
DE10164913B8 (de) | 2008-10-02 |
KR20010093658A (ko) | 2001-10-29 |
US20030207131A1 (en) | 2003-11-06 |
US6958525B2 (en) | 2005-10-25 |
US6613834B2 (en) | 2003-09-02 |
US20010033026A1 (en) | 2001-10-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE10164913B4 (de) | Halbleitervorrichtungen mit Filmmaterial mit niedriger Dielektrizitätskonstante und Verfahren zu ihrer Herstellung | |
DE10164943B4 (de) | Halbleitervorrichtung, umfassend als Zwischenschicht-Isolationsfilm einen Film mit niedriger Dielektrizitätskonstante | |
DE112007000215B4 (de) | Verfahren zur Herstellen einer Halbleitervorrichtung mit porösem Silizium-Dielektrikum | |
DE19804375B4 (de) | Verfahren zur Herstellung eines Zwischenschichtisolierfilmes | |
DE10053201B4 (de) | Herstellung einer Siliziumoxidschicht bei einem Halbleiterherstellungsprozess unter Verwendung einer Aufschleuder-Glaszusammensetzung | |
DE112005002692B3 (de) | Verwendung polydentater Liganden zum Versiegeln von Poren in Low-k-Dielektrika, sowie damit hergestellte Halbleitervorrichtungen | |
DE10248272A1 (de) | Halbleitervorrichtung und Verfahren für ihre Herstellung | |
DE102017127530A1 (de) | Verbindungsstruktur und Verfahren | |
CN101045820B (zh) | 形成绝缘膜的组合物以及制造半导体器件的方法 | |
DE112005001676T5 (de) | Verfahren und System zum Charakterisieren von porösen Materialien | |
KR20000074613A (ko) | 실리콘-메틸 결합을 함유하는 절연층을 포함하는 다층 구조의 절연막 및 그 형성방법 | |
DE102006029334A1 (de) | Material zum Ausbilden eines Belichtungslicht blockierenden Films, mehrschichtige Verbindungsstruktur und Herstellungsverfahren dafür, und Halbleitervorrichtung | |
EP0424638B1 (de) | Herstellung einer Halbleitereinrichtung eine Stufe zum Erzeugen einer aus Organokiesel-Sol isolierenden Schicht enthaltend | |
DE102006039001B4 (de) | Verfahren zum Herstellen einer mehrschichtigen Verbindungsstruktur | |
EP1652890B1 (de) | Phosphorhaltige silazanzusammensetzung, phosphorhaltiger siliciumoxidfilm, phosphorhaltiger siliciumoxidfüllstoff, verfahren zur herstellung eines phosphorhaltigen siliciumoxidfilms und halbleitervorrichtung | |
DE102006062728B4 (de) | Halbleitervorrichtung und Herstellungsverfahren dafür | |
CN101960582A (zh) | 布线基板、半导体装置以及半导体装置的制造方法 | |
JP4257272B2 (ja) | 半導体装置及びその製造方法 | |
JPH09213693A (ja) | 絶縁膜の形成方法 | |
JP2006351877A (ja) | 積層体の製造方法、半導体デバイスおよび半導体デバイスの製造方法 | |
DE4018449C1 (en) | Low temp. prodn. of anhydrous silicon di:oxide layer - comprises polymerising silicon-oxygen organic cpd. with oxygen or nitrogen oxide gas, depositing, converting to silicate etc. | |
JP3371333B2 (ja) | 絶縁膜の形成方法 | |
JP2004186593A (ja) | 低誘電率絶縁膜及びその製造方法並びに半導体装置 | |
DE102004020328A1 (de) | Verfahren zur Abscheidung einer mit Kohlenstoff dotierten siliziumhaltigen dielektrischen Schicht |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8172 | Supplementary division/partition in: |
Ref document number: 10164913 Country of ref document: DE Kind code of ref document: P |
|
Q171 | Divided out to: |
Ref document number: 10164913 Country of ref document: DE Kind code of ref document: P |
|
AH | Division in |
Ref document number: 10164913 Country of ref document: DE Kind code of ref document: P |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP |
|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |