DE10153609C2 - Method for producing an electronic component with a plurality of chips stacked on top of one another and contacted with one another - Google Patents

Description

The present invention relates to a process for the preparation an electronic device with several gesta pelt and contacted with each other on a chip mountable ment carrier and provided over several on the component Contact elements on the component carrier is contactable.

From US 3,579,056 A is the arrangement of chips, the backfilling in an elastic holder frame and generating an electrical contacting with contacting elements on both main surfaces of the arrangement known. In addition, the three-dimensional Stacking the components so embedded in the flexible carrier taught.

EP 0 611 129 A2 discloses chips made in a holder frame Plastic are shed. Contacting elements in the form of In terconnect pins are released at the bottom of the holder frame sets. Again, separately produced in the holder frame potted Chips stacked.

US 6,117,704 discloses a device with encapsulated and tested chips, which are arranged in several levels one above the other.

US 5,324,687 A also discloses a stacked arrangement packed chips.

DE 44 33 845 A1 discloses a method for producing a three-dimensional integrated circuit, where two finished pro zessierte substrates are interconnected. This is only subjected the upper substrate to a functional test with which the in Takten chips of the substrate are selected. Subsequently, will this substrate thinned from the back, into individual chips disassembled and only selected intact chips on that, with a detention layer provided lower substrate adjusted applied. The trenches between the applied chips are filled in and between the metallizations of the lower and upper components a vertical Connected.

From US 5,455,455 A is an electronic component with chips in a holder frame of epoxy known, with übereinanderlie ing chips with in the region of the holder frame extending Um Wirings are contacted with each other, wherein the device layered on a support or generated.  

Known method for producing a device with several The stacked chips can be stacked in the third dimension roughly divided into two groups. For one thing, the Sta pattering of packaged chips, on the other stacking nude crisps. When stacking of packaged chips these are übereinan the stacked and mitein with their contact elements (legs) connected. Examples are z. B. stacked TSOP or stacked BOC. Draw these three-dimensional designs itself by so-called Interposer (thin or thick Boards or Leadframes) for connection between the stack levels, where these interposers are mounted on the chips and with suitable ver be connected to the chip-side contact elements. This method is expensive because of its installation effort it is based on a single - the process flow, d. H. it will processed exclusively separate individual packaged chips. Due to the sometimes necessary interposer, the result is rende components of considerable height. A thinning of the Chips during the stacking process is due to the already he followed not possible housing.

A device produced by stacking naked chips made possible light contrast, a lower construction height. The chip / chip Connection system leads through the respective chip. The to  necessary fine Kontaktierungsvias are usually in one Frontend-like process generates (via-etching / passivating / Via-filling). However, this process has crucial Disadvantages for the application. First, it sets a special one Chip design ahead, the generation of contacting or Passage vias allowed. The generation of the vias is very expensive, because they come in an additional, relatively long process of Frontend processes must be created. Although the essentials processes can be carried out at the disk level, arise when stacking nude chips on disk level nevertheless difficulties regarding the yield. As each Slice only a finite yield of working chips has, when stacking the discs increases the risk for a working stack, the yield decreases exponentially with increasing stacked number of slices. An economic Component manufacturing by this method is not possible.

The invention is based on the problem of a method admit that in a simple way the production relatively low built-up components with high yield allows.

To solve this problem is a method according to the invention provided according to claim 1.  

The inventive method first proposes the creation a wafer consisting exclusively in a previous one Test as functionally tested chips. This soge Called "Known Good Wafer" is called by rasterike positionie ren of the chips and embedding the same in one insulating holding frame, preferably by means of a viscous non-conductive polymer used as filler is produced, manufactured. It is conceivable, either the same like chips or even different chips in their egg characteristics and / or dimensions are different in these Integrate wafers. This wafer or this first planar chip Arrangement will therefore come from fan-out wafer-level packaging provides. This support frame for the fan-out wafer level packa went is now not only used for fan-out, but he serves also to the vias from the chip front to Chip back to take over, d. H. the via becomes shifted to the holding frame area. The following will now be on this way creates another chip arrangement, so aufgesta pelt, with the chips and the support frame congruent over be positioned each other when the multi-chip stack off similar or equal chips is constructed. It is  but also possible, different in the different levels or different sized chips to arrange, in which case not always a congruent stacking due to the sizes differences is possible. The above step will be so often repeated as separate chip layers are provided. Are all Chip layers stacked on top of each other, so the individual construction elements by separating the stack in the area of the Halterah mens isolated.

The inventive method has over the known Ver drive considerable advantages. First, it is a complete wafer-level process, as at disk level gear is processed and only after the components in their total unit produced by forming the stack he follows. Because only working chips used the yield is very high. It can all be standard chips are used, with similar or unterschiedli chips can be integrated in every level. Farther It is a very cost effective process because the contact vias for the contacts are not affected by the conductive silicon kri stall with expensive technology, but through the support frame, resulting in much simpler thin-film and / or thick-film processes can take place. Further acts it is a process sequence that involves very little process Temperatures (<150 ° C) can be performed, which is not too has additional load on the chips. Also allows that Stacking the chips that are de facto naked, the Production of components with extremely low height, wherein during manufacture a very low risk Lich of handling and fracture results.

The inventive method allows a structure of a Multi-chip arrangement without mounting an additional counter stands, z. B. an interposer. Rather, here are the chip arrangements are built directly on each other. The rewiring  The chips are immediately at wafer level, so directly in the plane of the wafer and can be in Wafer Level Techno be processed (thin film / thick film). This made possible light of each surrounding a chip holding frame, as Contacting area serves, d. H. the electric chip chip Contacting (or even the module board) takes place in the area of the holding frame. In addition to a minimum of required Kon Clock transitions (mechanical and especially electrical) is characterized Such a manufactured multi-chip device also by his low height and the small lateral dimensions.

In a further development of the inventive idea can be provided that at least the first chip arrangement using a Carrier on which the chips are attached by means of an adhesive be generated. As a carrier can be a self-adhesive Foil or a self-adhesive tape can be used alterna tiv is also the use of a preference on its surface wise passivated silicon carrier conceivable.  

A chip arrangement that is built on an already existing can be produced according to the invention with the following steps:

• - Generating further contacting elements of the other Chipan Regulation on the upper side exposed Kontaktierungsele elements of the lower chip arrangement,
• - Applying the chips of the other chip arrangement above and preferably congruent with the chips of the lower chip order,
• - Generating the insulating support frame such that the Kon Taktierungselemente still protrude from the chip and the Fill the chips on the top side except for the chip-side con covers tact pads as insulation layer,
• - generating the rewiring,

the steps being repeated as many times as Chipanordnun to stack one above the other.

By generating the respective further contacting elements the vias are realized from top to bottom. Then the chips are positio in the given grid niert and generates the holding frame. The filler is so introduced that it chips up to the chip-side Kon Taktpads top side insulated, which is for the subsequent Erzeu rewiring is required.  

The first chip arrangement, ie the lowest arrangement on which a further chip arrangement is constructed, can be generated with the following steps:

• - Generating the contacting elements of the first chip arrangement on the support, in particular a silicon support,
• Applying the chips of the first chip arrangement,
• - Generating the insulating support frame such that the Kon still protrude from the holding frame and the filler topside the chips except for the chips Covering contact pads as an insulation layer,
• - Generating the rewiring.

It is expedient if, after the generation of the holding frame including the frame partially covering the chip cut a filler uniformly erosive Reini tion step, whereby a flat surface is generated, which is advantageous for the subsequent generation of the rewiring is liable. In addition, the overall height is slightly thinner.

As an alternative to the generation of the first and each further chip arrangement of the type described in a structure of a chip arrangement on an already existing provides a second Ver process variant before, to generate the first chip arrangement (and also each other) with the following steps:

• a) generating rewiring paths with contact points on a support, in particular a preferably passivier th silicon carrier,
• b) fixing the already provided with a rewiring Chips with their rewiring having side to Carrier pointing, so that the rewiring with the Umverdrah be connected to the tracks of the carrier,  
• c) generating the holding frame such that the chips also ih rer free side be embedded in the filler, wherein in the support frame contact vias to the via to the be formed below underlying contact points,
• d) generating additional rewiring tracks with contacting points and elements that fill the contact vias,

then steps a) to d) to form one or more further chip arrangements are repeated.

In this embodiment of the invention so chips are on the Carrier or an existing chip arrangement auf brought, which are already provided with a rewiring. It are only on the carrier or a lower Chipanord Rewiring tracks, on the one hand aufzuset of one zenden chip are contacted and the other hand in the Be run rich of the holding frame, generated.

After attaching the chips can be beneficial to the reduction the thickness of chip material are removed, d. H. here is active the thickness of a chip and thus the overall height of the resul decreasing component. The removal of the chip material as may be by wet or dry etching or by mechani treatment.

The chips themselves are made by means of a non-conductive adhesive attached, since the actual contacting over the Umverdrah tracks and the contact points and elements via the contact vias take place. After the generation of the last chip order are at the top of contact elements for Kontak animals of the below to be separated components with the Carrier produced, this being for both procedural Ausfüh ments in which a chip arrangement on one already existing is established.  

While the foregoing embodiments of the invention ßen method for contacting the rewiring tracks two chip levels the holding frame passing through contacting However, it is also possible to provide elements ability to directly contact the rewiring tracks A first, a quasi-direct contacting performing Embodiment is the method variant described above, be formed in the contact vias in the support frame, which then directly filled in the production of Umverdrahtungsbahnen who the, d. H. the rewiring tracks and their contacts in the Contact vias to the underlying rewiring level produced together.

In contrast, an embodiment enabling an immediate rewiring contact of two levels provides the following steps:

• a) arranging the chips on a carrier,
• b) generating the holding frame such that the chips in time their free pages except one the contact pads freilas send area embedded in the filler,
• c) generating rewiring tracks which extend into the Be rich the holding frame between the chips sections, wherein the thus positioned ends the rewiring tracks the contact elements for the following form a chip arrangement to be set up or arranged,
• d) applying a non-conductive adhesive for fixation the chips of the second chip arrangement and ge for insulation compared to the underlying rewiring paths such, the contact elements of the first chip arrangement leave it free gene, and applying the chips of the second chip assembly,  
• e) applying a non-conductive further filler to Formation of a holding frame such that it has the chips since Lich and top side except for the area of Kontaktie covering pads, wherein the contact elements of the first Chip arrangement remains free,
• f) generating the rewiring paths of the second chip arrangement, the end with the contact elements of the first Chipanord be contacted,
• g) if necessary, one or more repetitions of Steps d) to f).

In this embodiment of the invention, therefore, serve the ends of the Rewiring tracks themselves as contact elements for each be adjacent rewiring level. The individual retaining frame of Chips of a second chip arrangement are thereby dimensio Although they do embed the chip to a large extent, they do embed the chip Ends of the redistribution paths of the underlying chip level do not cover. The rewiring tracks of the second chipanord Now run on the support frame laterally in the underneath lying plane, where they immediately with the Umver to be connected.

The contacting elements and the Umverdrahtungsbahnen and their contact points are suitably from a produced conductive polymer. They are preferably printed.

As a filler is as described suitably a non-conductive polymer used, printed on, sprayed on or spin-coated. Generally, after generating the Holding frame, especially if this bedec a bedec kenden section, a step to reduce the Thickness of the filler while leveling the surface  consequences.

In addition to the method, the invention further relates to an electro niche device with several stacked chips, the egg after ner of the described process variants is made.  

Further advantages, features and details of the invention erge ben from the Ausführungsbeispie described below len. Showing:

FIGS. 1a-1l, the individual process steps for the manufacture of a component position, in which a chip assembly is mounted on egg ner existing chip arrangement,

FIGS. 2a-2o the process steps for producing egg nes device in which a chip assembly is mounted on an existing chip array wherein individual chips are used with pre-arranged rewiring, and

FIGS. 3a-3j, the process steps for producing egg nes component, in which the Umverdrahtungsbahnen two chips can be contacted directly with each other.

FIGS. 1a-1l show the most important method steps for producing a three-dimensional component in fan-out wafer-level packaging, in which case a chip arrangement is constructed on a respective existing chip arrangement.

To form the first "lowermost" chip arrangement, through-contacting elements 14 , preferably made of conductive silicon, are firstly applied to a carrier 13 , for example a passivated silicon carrier, mainly printed. According to Fig. 1b, a chip 15 is glued with its contacting side 16 facing up to the carrier 13 using a ge suitable adhesive. According to Fig. 1c, a holding frame 17 is produced using an insulating filler 18 , for example, epoxy resin or silicone. The filler is primarily printed. The support frame is measured so be that the through-hole elements 14 are not covered by him on the top. Furthermore, the holding frame 17 extends substantially over the chip 15 , but leaves the upper-side contact pad 19 of the chip 15 free in the middle. In step ge according to Fig. 1d, the surface of the support frame 17 example, cleaned by plasma etching or wet etching and the holding frame slightly removed. In the step shown in FIG. 1e, wires 20 are now applied to the top of the chip 15 partially covered by the holding frame 17 . These Umverdrahtun conditions 20 contact the feedthrough elements 14 with the contact pads 19th The generation of the redistribution 20 takes place by sputtering or plating a metal layer, a subsequent lithography and a subsequent wet etching step. Upon completion of the process step of Fig. 1e, the first "lower" chip assembly 21 is completed.

On this lower chip assembly 21 are now, see Fig. 1f, congruent with the via elements 14 of the un direct chip arrangement 21 further via elements 14 applied. In the step shown in FIG. 1g, a second chip 15 is now congruent over the existing chip 15 of he most chip arrangement set. The chip 15 is expediently provided on its rear side with a passivation layer, so that it is insulated from the rewiring of the lower chip arrangement 21 .

In the step according to FIG. 1h, a holding frame 17 is again described using a filler 18 in the same way as with respect to FIG. 1c. This too is then cleaned (see Fig. 1d) and slightly removed. In the step of Fig. 1i he follows the generation of the rewiring 20 of the second Chipanord voltage or level. This in turn is followed by the steps according to FIGS. 1f et seq. These are repeated as often as chip arrangements are to build. Fig. 1j shows a configura tion with four chip assemblies 21 , wherein on the uppermost Chipan Regulation 21 two contacting elements 14 are set. If the configuration is completely established, the compo elements are separated by separating the holding frame of all superposed ge chip assemblies 21 . Fig. 1j shows a ver single-component 22nd

For mounting the device 22 on a component carrier 23 , this is now reversed (flip chip), on the exposed contact elements 14 are Verbindungskleberpunkte 24 , for example, made of conductive silicone, applied over which the device 22 then on the component carrier 23 under Kontaktie tion of the via 14th with carrier-side con tact elements 25 is attached.

Fig. 2a-2o show the relevant process steps for the production of a device by building a Chipan order on an already existing, in which case chips are used, which are already tested as functional and provided with a rewiring.

The starting point is a chip 26 shown in FIG. 2a, which has already been tested as being functional. At its contacting page already a rewiring 27 and corresponding contact points 28 is generated.

As shown in Fig. 2b, for the production of the first lower chip array on a support 29 , (for example, the passi fourth surface of a silicon wafer) primarily by means of a conductive polymer rewiring or Umverdrah tungsbahnen 30 and rewiring contact points 31 using Verwen tion of a conductive polymer applied, mainly printed on. By means of a non-conductive adhesive 32 is now, see Fig. 2c, the chip 26 with its contacting side, ie the side where the rewiring is applied, glued to the carrier 29 . In this case, the chip-side rewiring 27 and the rewiring contact points 28 with the corresponding Umver wiring paths 30 and the rewiring contact points 31 on the carrier 29 contacted. If the compound has cured, it follows in the step according to FIG. 2e a material removal on the chip 26 , ie the chip is made thinner. The material can be removed as example by dry or wet etching or mechanical treatment. As can be seen clearly reduces the height of the first chip arrangement significantly.

In the step shown in FIG. 2f, the given configuration for forming a holding frame 33 in a filling material 34 is now embedded. For this example, insulating silicone is printed on and then cured. The holding frame 33 has Kontaktierungsvias 35 , which made a subsequent via to the rewiring tracks and rewiring contact points 30 , 31 which are applied to the support surface, made light. In step 2 g, the surface of the holding frame 33, which also covers the chip, is now leveled by dry or wet etching or by mechanical treatment, and the holder frame is made somewhat thinner.

In the step according to FIG. 2h, the rewiring tracks 36 and rewiring points for the next chip arrangement are now produced by printing on a conductive polymer. As can be seen, the conductive polymer fills the Kontaktvias 35 , so that a via to the underlying Umverdrahtun conditions occurs.

Subsequently, in the step according to FIG. 2i, a non-adhesive adhesive 32 is again applied, after which, in the step according to FIG. 2j, another chip 26 is placed with its contacting side facing downwards and adhesively bonded. Again, the bonding of the rewiring 27 takes place with the ent speaking Umverdrahtungsbahnen 36 on the surface of the un direct chip assembly 37 when gluing.

After sticking the chip 26 (see FIG. 2k), the chip 26 is also thinned here (see FIG. 2i). Subsequently, the embedding in a filling material for producing the Halterah mens again with the Kontaktierungsvias and the re-generation of the Umverdrahtungsbahnen, as described in FIGS. 2f-2h again.

If the entire configuration is constructed, the result is a stack of chip arrangements 37 , as shown in FIG. 2m. Again, four chip arrays 37 are exemplarily stacked übereinan of. Below, the individual components by separating the support frame, which forms as in all Ausfüh tion forms of course superimposed lie, isolated. FIG. 2m shows a separated component 38 . On the exposed upper side, in step 3, n connection adhesive spots 39 are subsequently applied using a conductive adhesive, by means of which the component 38 is glued and contacted ( FIG. 2o) onto a component carrier 40 , on the upper side of which carrier-side contact points 41 are located.

FIGS . 3a-3j show a fourth variant of the method for producing a component according to the invention, in which case the rewiring paths of two superimposed chips are directly connected to one another.

On a support 42 , z. As a film or a glass substrate is, as shown in FIG. 3a, a non-conductive polymer layer 43 , z. B. imprinted or spin coated. Subsequently, see Fig. 3b, a chip 44 is applied to the upper side preferably adhesive polymer layer 43 , after which the polymer layer is cured.

As shown in FIG. 3c, a filler 45 is then applied to Bil forming a chip 44 both laterally and also visible on the top side up to the area of the contact pads 46 covering holding frame and cured. As shown in FIG. 3d, the rewiring webs 47 are subsequently produced, which can be seen to run into the region of the lateral holding frame sections. The ends of the rewiring paths 47 thereby form contact elements 48 , which serve for the subsequent contacting to a chip arrangement to be arranged above.

On the known from Fig. 3d arrangement, a non-conductive adhesive 49 is now brought, for example, in a printing process, said adhesive layer is dimensioned such that the contact elements 48 , formed by the ends of the rewiring 47 remain free. Subsequently, a second chip 50 is glued ( Fig. 3f), after which the adhesive layer is cured.

In the step shown in Fig. 3g now another filler 51 is applied, which embeds the formation of a second chip 50 embedding and both side and top side except for the loading rich 52 of the contact pads. Also, this support frame is laterally dimensioned such that the contact elements 48 of the wiring paths 47 remain around the underlying chip levels remain free. The filler can be applied for example in egg nem printing process.

Finally, see Fig. 3h, the Umverdrahtungsbahnen 53 of the chip 50 is generated, wherein the Umverdrahtungsbahnen 53 since Lich on the support frame down in the Umverdrahtungsbah side of the chip 44 run where it can be seen with the contact elements 48 , ie the ends of the Umverdrahtungsbahnen 47 kon be clocked. The rewiring paths, as well as the redistribution paths of the underlying chip plane, can be produced by sputtering and plating as well as by means of suitable photolithographic steps.

As shown in FIG. 31, contact elements 54 and 55 are subsequently produced on the active side of the chip 50 . When the contact elements 54 are conductive adhesive to kontak animal interconnect elements, in the contact elements 55 in the example shown to Lotbällchen. Of course, only one type of contact elements can be provided. They serve to make the subsequent contact with a carrier.

The carrier 42 is finally removed and the individual Mul tichip modules to form isolated components 56 by sawing (see the indicated lateral Sägespalte) or the same isolated. The separation takes place by separation in the region of the lower support frame, which also example, by laser cutter or the like can be done.

Subsequently, such a device 56 via the con tact elements 54 , 55 with a module board 57 , on the upper side contact points 58 are provided, are fixed and contacted. In the case of the contact elements 54 , this is done using a conductive adhesive, the contact elements 55 are fused in a conventional soldering process, so that the electrical contact is formed.

It should be noted at this point that FIGS . 3a-3j show the generation of a multi-chip component 56 with two chips. Of course, it is also possible to stack a plurality of chips on top of each other, wherein the rewiring paths of the chips are each guided from top to bottom in the plane of the Umverdrah application paths 47 of the lowermost chip 44 . But it is also conceivable to contact each Umverdrahtungsbahnebene only with the underlying, so that rewiring tracks do not have to be routed too far laterally along the chip stack down. In these embodiments, however, the lateral dimension of the respective chip frames increases somewhat.

LIST OF REFERENCE NUMBERS

1

carrier

2

feedthrough

3

chip

4

holding frame

5

fillers

6

rewiring

7

contact pad

8th

bonding adhesive

9

chip system

10

protective cover

11

module

12

train

13

carrier

14

Durchkontaktierungselement

15

chip

16

contacting side

17

holding frame

18

fillers

19

contact pad

20

rewiring

21

chip system

22

module

23

component carrier

24

Connecting glue points

25

contact element

26

chip

27

rewiring

28

contact point

29

carrier

30

Umverdrahtungsbahn

31

Umverdrahtungskontaktpunkt

32

Glue

33

holding frame

34

filling material

35

Kontaktierungsvia

36

Umverdrahtungsbahn

37

chip system

38

module

39

Bonding adhesive point

40

component carrier

41

contact point

42

carrier

43

polymer layer

44

chip

45

fillers

46

contact pad

47

Umverdrahtungsbahn

48

contact element

49

Glue

50

chip

51

fillers

52

contact pad

53

Umvredrahtungsbahn

54

contact element

55

contact element

56

module

57

module Board

58

contact point

Claims (16)

A method of making an electronic component ( 22 , 38 , 56 ) having a plurality of chips ( 15 , 26 , 44 , 50 ) stacked on each other and contacted with each other mounted on a support ( 13 , 29 , 42 ); the chips ( 15 ; 26 ; 44 , 50 ) being connected via a contact device ( 14 , 20 , 24 ; 27 , 28 , 36 , 39 ; 47 , 48 , 53 , 54 , 55 ) to a component carrier ( 23 ; 40 ; 57 ). are contactable, with the following steps:

• a) generating a first planar chip arrangement ( 21 , 37 ) by spacing apart functional chips ( 15 , 26 , 44 ) in a grid and filling at least the distances between the chips ( 15 , 26 , 44 ) with a filling means ( 18 34 , 45 ) for forming a chip ( 15 ; 26 ; 44 ) fixing insulating support frame ( 17 ; 33 ) with chip nen, the electrical contact to another chip another chip assembly serving, in the region of the holding frame side of each chip ( 15 , 26 , 44 ) provided contact elements ( 14 , 36 , 48 ) of the contact device ( 14 , 20 , 24 , 27 , 28 , 36 , 39 , 47 , 48 , 53 , 54 , 55 ), which with on-chip redistribution ( 20 , 27 , 28 , 47 ) of the contact devices ( 14 , 20 , 24 , 27 , 28 , 36 , 39 , 47 , 48 , 53 , 54 , 55 ),
• b) producing a further planar chip arrangement ( 21 , 37 ) after step a) on the first chip arrangement ( 21 , 37 ) such that the chips ( 15 , 26 , 44 , 50 ) and the holding frames ( 17 , 33 ) of the two chip arrangements lie one above the other and the respective respective contact elements ( 14 , 36 , 48 , 53 ) of the two chip assemblies for the electrical chip-chip contacting are connected together electrically,
• c) optionally repeating step b) once or several times,
• d) optionally applying interconnect elements ( 24 , 39 , 54 , 55 ) of the contact device ( 14 , 20 , 24 , 27 , 28 , 36 , 39 , 47 , 48 , 53 , 54 , 55 ) to the component carrier ( 23 , 40) 57 ); and
• e) separating the each of a plurality of stacked chips (15; 26; 44) of the single chip assemblies (21; 37) existing components by separating the holding frame (17; of the fixed interconnected chip assemblies 33) (21; 37).

2. The method according to claim 1, characterized in that the support (13; 42; 29) has a self-adhesive film or tape, or preferably passivated on its surface silicon carrier is used. 3. The method according to claim 1 or 2, characterized
the further chip arrangement ( 21 ) is generated by the following steps:

• Generating further contact elements ( 14 ) of the further chip arrangement ( 21 ) on the upper side exposed contact elements ( 14 ) of the lower chip arrangement ( 21 ),
• - applying the chips ( 15 ) of the further chip arrangement ( 21 ) above and preferably congruent with the chips ( 15 ) of the lower chip arrangement ( 21 ),
• - Producing the insulating support frame ( 17 ) such that the contacting elements ( 14 ) still protrude from the holding frame ( 17 ) and the filler ( 18 ) covers the chips ( 15 ) on the upper side except for the chip-side contact pads ( 19 ) as an insulating layer,
• Generating the rewirings ( 20 ),

these steps are repeated as many times as stacking chip arrays. 4. The method according to claim 3, characterized in that the first chip arrangement ( 21 ), on which the further Chipan Regulation ( 21 ) is constructed, is produced with the following steps:

• Generating the contacting elements ( 14 ) of the first chip arrangement ( 21 ) on the carrier ( 13 ), in particular the silicon carrier,
• - applying the chips ( 15 ) of the first chip arrangement ( 21 ),
• - Generating the insulating support frame ( 17 ) such that the contacting elements ( 14 ) still protrude from the support frame ( 17 ) and the filler ( 18 ) the chips ( 15 ) covers the top side except for the chip-side contact pads ( 19 ) as an insulation layer,
• - Generating the rewirings ( 20 ).

5. The method of claim 3 or 4, characterized in that after the formation of the holding frame (17) including the chip (15) partially covering the frame portion (17), the filler (18) uniformly ablative cleaning step. 6. The method according to claim 1 or 2, characterized
the first chip arrangement ( 37 ) is produced by the following steps:

• a) generating rewiring tracks ( 30 ) with contacting points ( 31 ) on the carrier ( 29 ),
• b) fixing the already with the on-chip rewiring ( 27 ) and associated rewiring contact points ( 28 ) ver seen chips ( 26 ) with their the rewiring ( 27 ) aufwei send side to the carrier ( 29 ) pointing, so that the Umverdrah device ( 27 ) and the rewiring contact points ( 28 ) with ent speaking rewiring tracks ( 30 ) and associated Umver wirungskontaktpunkten ( 31 ) of the carrier ( 29 ) connected who,
• c) generating the holding frame ( 33 ) such that the chips ( 26 ) are also eingebet on their free side in the filler ( 34 ) Tet, wherein in the holding frame ( 33 ) contact vias ( 35 ) for the via connection to the underlying Umverdrah voltage contact points ( 31 ) are trained
• d) generating further rewiring tracks ( 36 ) with rewiring contact points and contact elements that fill the contact vias ( 35 ),

after which steps a) to d) are repeated to form one or more further chip arrangements ( 37 ). 7. The method according to claim 6, characterized in that after attaching the chips ( 26 ) is removed to reduce the thickness of chip material. 8. The method according to claim 6 or 7, characterized in that the chips ( 26 ) by means of a non-conductive adhesive ( 32 ) are attached. 9. The method according to any one of claims 1 to 5, characterized in that after the generation of the last chip arrangement on the upper side contact elements ( 14 ) for contacting the subsequently to be separated components with the component carrier ( 23 ) are generated. 10. The method according to claim 1 or 2, characterized by the following steps:

• a) arranging the chips ( 44 ) on the carrier ( 42 ),
• b) generating the holding frame ( 45 ) in such a way that the chips ( 44 ) are embedded in the filling means ( 45 ) laterally and on their free side except for a contact pad ( 46 ) of the chips ( 44 ) of the first chip arrangement;
• c) generating from the rewirings ( 47 ) which extend into the region of the holding frame sections located between the chips, the ends of the rewiring paths thus positioned forming the contact elements ( 48 ) for the chip arrangement to be constructed or arranged as follows:
• d) applying a non-conductive adhesive ( 49 ) for fi xing the chips ( 50 ) of the second chip assembly and the insulation from the underlying rewiring tracks ( 47 ) such that the contact elements ( 48 ) of the first chip assembly are exposed, and applying the chips ( 50 ) of the second chip arrangement,
• e) applying a non-conductive further filler ( 51 ) to form a holding frame such that it covers the chips ( 50 ) laterally and on top except for the area contact pads ( 52 ) of the chips ( 50 ) of the second chip arrangement, wherein the contact elements ( 48 ) of the first chip arrangement remain ben,
• f) generating the rewirings ( 53 ) of the second chip arrangement, the end with the contact elements ( 48 ) of the first chip arrangement are contacted, and
• g) if necessary, one or more repetitions of steps d) to f).

11. The method according to any one of the preceding claims, characterized in that the contact elements ( 14 ; 36 ; 48 ) and the rewiring ( 20 ; 27 , 28 ; 47 ) are produced from a conductive polymer. 12. The method according to any one of the preceding claims, characterized in that the contact elements ( 14 ; 36 ; 48 ) and the rewiring tracks ( 20 ; 27 , 28 ; 47 ) are printed. 13. The method according to any one of the preceding claims, characterized in that as filler ( 18 ; 34 ; 45 ), a non-conductive polymer is used. 14. The method according to claim 22, characterized in that the filler ( 18 ; 34 ; 45 ) is printed, sprayed or spin coated. 15. The method according to any one of the preceding claims, characterized in that after the generation of the holding frame ( 17 ; 33 ), in particular when this has a chip ( 15 ; 26 ; 44 , 50 ) from Ab-section, a step for reducing the thickness of the filler ( 18 ; 34 ; 45 ) is carried out with simultaneous leveling of the fa ce. 16. The method according to claim 15, characterized, that the thickness reduction by wet or dry etching or done by mechanical treatment.