DE10164917B4 - Halbleiterspeichersystem - Google Patents

Halbleiterspeichersystem Download PDF

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Publication number
DE10164917B4
DE10164917B4 DE10164917.7A DE10164917A DE10164917B4 DE 10164917 B4 DE10164917 B4 DE 10164917B4 DE 10164917 A DE10164917 A DE 10164917A DE 10164917 B4 DE10164917 B4 DE 10164917B4
Authority
DE
Germany
Prior art keywords
clock signal
signal
bus
memory
memory module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10164917.7A
Other languages
German (de)
English (en)
Inventor
Dong-yang Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE10164917B4 publication Critical patent/DE10164917B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
DE10164917.7A 2000-09-05 2001-09-05 Halbleiterspeichersystem Expired - Fee Related DE10164917B4 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR2000-52377 2000-09-05
KR20000052377 2000-09-05
KR10-2000-0079186A KR100396885B1 (ko) 2000-09-05 2000-12-20 고주파 클럭 신호의 주파수를 낮추어 어드레스 및커맨드의 동작 주파수로 사용하고 서로 다른 주파수의클럭 신호들을 수신하는 반도체 메모리 장치, 이를포함하는 메모리 모듈 및 시스템 메모리 모듈
KR2000-79186 2000-12-20

Publications (1)

Publication Number Publication Date
DE10164917B4 true DE10164917B4 (de) 2014-01-23

Family

ID=19687420

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10164917.7A Expired - Fee Related DE10164917B4 (de) 2000-09-05 2001-09-05 Halbleiterspeichersystem

Country Status (2)

Country Link
KR (1) KR100396885B1 (es)
DE (1) DE10164917B4 (es)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100732280B1 (ko) * 2001-06-27 2007-06-25 주식회사 하이닉스반도체 메모리 시스템
JP4812976B2 (ja) * 2001-07-30 2011-11-09 エルピーダメモリ株式会社 レジスタ、メモリモジュール及びメモリシステム
KR100546097B1 (ko) * 2001-11-21 2006-01-24 주식회사 하이닉스반도체 제어 및 어드레스 클럭 비분배형 메모리 시스템
KR100588593B1 (ko) * 2005-06-09 2006-06-14 삼성전자주식회사 레지스터형 메모리 모듈 및 그 제어방법
KR100812600B1 (ko) * 2005-09-29 2008-03-13 주식회사 하이닉스반도체 주파수가 다른 복수의 클럭을 사용하는 반도체메모리소자
KR100888597B1 (ko) * 2006-09-20 2009-03-16 삼성전자주식회사 메모리 인터페이스 제어 장치 및 제어 방법
KR101944964B1 (ko) * 2012-01-13 2019-02-01 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
US10915474B2 (en) 2017-11-29 2021-02-09 Micron Technology, Inc. Apparatuses and methods including memory commands for semiconductor memories
KR20220087231A (ko) 2020-12-17 2022-06-24 삼성전자주식회사 저전력 소모를 위하여 클럭 스위칭하는 장치, 메모리 콘트롤러, 메모리 장치, 메모리 시스템 및 방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999030240A1 (en) * 1997-12-05 1999-06-17 Intel Corporation Memory system including a memory module having a memory module controller

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265298A (ja) * 1985-09-17 1987-03-24 Fujitsu Ltd Ｅｐｒｏｍの書き込み方式
JP3078934B2 (ja) * 1992-12-28 2000-08-21 富士通株式会社 同期型ランダムアクセスメモリ
JP3277603B2 (ja) * 1993-05-19 2002-04-22 富士通株式会社 半導体記憶装置
JPH08212784A (ja) * 1995-02-03 1996-08-20 Hitachi Ltd 多ポートメモリ装置
JPH10199240A (ja) * 1996-12-26 1998-07-31 Digital Electron Corp 同期式メモリ装置
JPH10208470A (ja) * 1997-01-17 1998-08-07 Nec Corp 同期型半導体記憶装置
JPH10247388A (ja) * 1997-03-05 1998-09-14 Toshiba Corp 記憶装置
JPH11321400A (ja) * 1998-05-12 1999-11-24 Ts Tech Co Ltd シート調節装置
KR20010001968A (ko) * 1999-06-10 2001-01-05 윤종용 반도체 메모리 장치의 어드레스 버퍼

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999030240A1 (en) * 1997-12-05 1999-06-17 Intel Corporation Memory system including a memory module having a memory module controller

Also Published As

Publication number Publication date
KR100396885B1 (ko) 2003-09-02
KR20020019375A (ko) 2002-03-12

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