DE10194689B4 - Non-volatile semiconductor memories with two storage units and method for their production - Google Patents

Abstract

A non-volatile semiconductor memory having a memory cell, comprising: a channel formation region (CH) made of a semiconductor; - Charge storage films (CSF) each composed of a number of dielectric films with charge retention capacity stacked on one another; - two reservoirs of areas of the charge storage films (CSF) which overlap two ends of the channel formation area (CH); A single-layer dielectric film (DF2) in contact with the channel formation region (CH) between the memory units; - Two first control electrodes (CG1, CG2), one of which is assigned to a memory unit in each case, and which are designed such that their width decreases with increasing distance from the channel formation region; and - a second control electrode (WL) embedded in the space between the two first control electrodes (CG1, CG2) in a state insulated from the first control electrodes (CG1, CG2) with the single-layer dielectric film (DF2) in Contact is available.

Description

The invention relates to a non-volatile semiconductor memory having two memory units, each having a charge storage film of a plurality of stacked dielectric films at the two ends of a channel formation region, said memory in the storage units can store two bits of information independently, and relates to a method for producing such a memory.

BACKGROUND TECHNIQUE

Also known in the art are semiconductor memories of the so-called "metal oxide nitride oxide" (MONOS) type and other non-volatile semiconductor memories having charge storage films of a plurality of stacked dielectric films which store information by controlling amounts of charge stored in charge traps in the charge storage films.

From the US 5,408,115 For example, an EEPROM memory with one memory per memory cell is known.

More recently, the technology recognizes the fact that it is possible to inject a charge into a part of a charge region of distributed charge traps by the conventional CHE (Channel Hot Electron) injection method and binary information on the source side and the drain side of a charge storage film independently to store, as reported, independent storage of two bits of information in a memory cell.

For example, according to "HAYASHI, Y. [u. a.]: Twin MONOS cell with dual control gates. In: 2000 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, 13.-15. Charge storage films are separately mounted on the source and drain sides, control electrodes are mounted on the charge storage films, and word gate electrodes are mounted in the central part of a channel between the control electrodes in a state where a single-layered dielectric Film without charge retention is inserted.

The word gate electrodes are connected to a word line while the control electrodes are laid in a direction perpendicular to the word line and are controlled separately from the word gate electrodes. Therefore, the controllability of the position of the charge injection and the charge injection efficiency can be improved, and as a result, a high-speed write operation is achieved.

The memory cells, which are referred to as "twin MONOS cells", have word gate electrodes repeated in the row direction at a certain interval, and have sidewall-type conductive layers on side surfaces of the two sides thereof in the row direction. ONO (oxide-nitride-oxide) films, d. H. Charge-holding charge-trapping films are present just below the sidewall-type conductive layers. In contrast, individual layers of dielectric films are formed directly below the word gate electrodes, so that these parts have no charge retention capability.

The sidewall-type conductive layers and the word-gate electrodes are used as masks for introducing n-type impurities to substrate sites exposed between adjacent sidewall-type conductive layers to form n ⁺ impurity regions that act as sources or drains.

The above publication does not disclose a specific manufacturing method, but in a MONOS twin cell, there are the following problems in manufacture and structure.

For twin MONOS cells, the word gate electrodes are fabricated and then the sidewall-type conductive layers are fabricated at their sides. Thus, a step of connecting the word gate electrode to the word line is required.

Furthermore, the word gate electrodes in MONOS twin cells must first be patterned into parallel line shapes along the column direction. At this time, normally, the material for the word gate electrode is deposited, then resist patterns are formed thereon, and the material of the word gate electrode is formed by a strong anisotropic etching method, e.g. B. RIE (reactive ion etching) using the resist processed as a mask. The resist patterns are usually tapered forward in their cross-sectional shape on their side surfaces, and the resist is slightly recessed during etching, so that the sides of the word gate electrodes are slightly forwardly tapered after processing. Further, even if no resist is used and a material is used which does not form a recess in the etching, there is a tendency that a taper in the forward direction to some extent on the side surfaces of the word gate electrodes after processing due to the effect of sidewall depositions Etching is present.

The word gate electrodes must be z. B. be processed simultaneously when the word lines are structured to isolate them against the cells. However, there must be, as the control gates are already formed on the sidewalls of the word gate electrodes in a state with inserted insulating films, the word gate electrodes are selectively etched and removed while burying holes having a trapezoidal cross-sectional shape. Accordingly, in this etching, it is difficult to etch the bottoms of the side surfaces of the reverse tapered control electrodes, and slightly conductive residues are generated in these portions along the control electrodes. When a conductive residue is generated, a short circuit occurs between the word lines.

Further, the sidewall-type conductive layers are formed in a ring shape surrounding the periphery of the line-shaped conductive layers to make the word-gate electrodes. When the sidewall-type conductive layers are used as such for the control electrodes, a control electrode on the source side and a control electrode on the drain side would be electrically short-circuited. Therefore, the two control electrodes must be insulated to supply different voltages to the control electrode on the source side and those on the drain side. This isolation can not be total in a further step, for. B. when editing the word lines are executed, so that z. For example, a step of forming an etching mask opened only in the two end portions of the line-shaped conductive layers for producing the word gate electrodes, removing the sidewall-type conductive layers through the openings, and cutting off the conductive layers are required.

Further, in a twin MONOS cell, since ONO films are formed directly under the sidewall-type conductive layers, these ONO films in contact with the channel formation region extend in the column direction along the sidewall-type conductive layers. During operation, data is injected by injecting charges into an area (hereinafter referred to as storage unit) of a channel-cutting ONO film while erasing data by subtracting the stored charges to the substrate side or by injecting a charge of the reverse conduction type. When this rewrite operation is repeated, a charge tends to accumulate in an adjacent area of the memory unit. Further, there is a tendency for the charge to create a leakage path to the outside of the channel. When data is erased by subtracting the stored charges, which are electrons, from the entire surface of the channel, this does not pose a great problem because the adjacent area is also under the control of a control electrode in the same way as the memory unit at the same time accumulated electrons accumulated in the neighboring area. However, a leak path easily arises, particularly when a reverse polarity charge is injected into a memory unit to extinguish a stored charge when a charge having a polarity reversing the direction of the channel, e.g. B. an electron hole in the path of an n-channel, is accumulated in an adjacent region of the storage unit. The resulting decrease in the leakage characteristic therefore becomes a problem.

DISCLOSURE OF THE INVENTION

A first object of the invention is to eliminate the need for a step of connecting word gate electrodes and a word line by structurally enabling the fabrication of the word gate electrodes and a word line (second control electrode) as an integral element.

A second object of the invention is to prevent the generation of a conductive residue which would lead to a short circuit between word lines and to structurally eliminate the need for a step of separating two control electrodes in a single cell by clipping.

A third object of the invention is to prevent the unnecessary accumulation of charges in an adjacent area of a memory unit in a direction along a control electrode or between memory units, and to obtain a structure in which no leakage occurs.

According to the present invention, the above objects are solved by the subject-matter of independent claims 1, 12 and 13.

Preferred embodiments are subject of the dependent claims.

A nonvolatile semiconductor memory according to a first embodiment of the invention has a memory cell comprising: a channel formation region made of a semiconductor; Charge storage films each composed of a number of stacked dielectric films having charge retention capability; two memories of regions of the charge storage films that overlap two ends of the channel formation region; a single-layered dielectric film in contact with the channel formation region between the storage units; two first control electrodes, each one of which is associated with a memory unit, and which are formed so that their width decreases with increasing distance from the channel formation region; and a second control electrode incorporated in the Space between the two first control electrodes is embedded in a state insulated from the first control electrodes, wherein it is in contact with the single-layered dielectric film.

The memory cell further has two impurity regions of a semiconductor of reverse conduction type to that of the above channel formation region separated therefrom; and two auxiliary layers formed on the two impurity regions near each surface of the first control electrodes facing the outside of the memory cell.

The auxiliary layers are made of conductive layers near the outsides of the first control electrodes in a state where dielectric films or layers of polycrystalline or amorphous silicon doped with an impurity of the same conductivity type as that of the impurity regions are interposed. Alternatively, the auxiliary layers of dielectric layers are close to the outsides of the first control electrodes.

In a configuration in which a plurality of memory cells are arranged in a matrix, two first control electrodes extending from the two sides in the width direction of an auxiliary layer common to two memory cells adjacent to each other in the row direction may or may have side wall shapes may consist of molds which are connected to the above auxiliary layer. First control electrodes of the latter type consist of conductive layers which cover the two sides and the top of the auxiliary layer and have a lower connection resistance than is present in the sidewall forms.

A nonvolatile semiconductor memory according to a second embodiment of the invention has a number of memory cells, each of which has: a channel formation region of a first conductivity type semiconductor; first and second impurity regions of a second conductivity type semiconductor separated from each other in the separation direction over the channel formation region; Control electrodes arranged in a direction perpendicular to the separation direction of the first and second impurity regions and common to a number of memory cells; and charge storage films each of a plurality of dielectric films formed in layers immediately below the control electrodes and storing information in portions overlapping with the channel formation region. In this memory, memory cells adjacent in the direction perpendicular to the separation direction of the first and second impurity regions are electrically insulated by dielectric insulating layers; and pairs of the first impurity regions and pairs of the second impurity regions of the adjacent memory cells insulated by the dielectric insulating layer are connected through conductive layers, respectively.

A method of manufacturing a nonvolatile semiconductor memory according to a third embodiment of the invention is a method of manufacturing a nonvolatile semiconductor memory having a channel formation region of a first conductivity type semiconductor, two impurity regions separated therefrom and composed of a second conductivity type semiconductor, two first control electrodes formed at two ends of the channel formation region near the two impurity regions in a state of inserted charge storage films each consisting of a plurality of dielectric films, and a second control electrode forming the channel formation region between the first control electrodes in a single-layered state facing dielectric film and disposed in the separation direction of the impurity regions; with the steps of manufacturing a nonvolatile semiconductor memory; forming line-shaped auxiliary layers in the direction perpendicular to the separation direction of the impurity regions on these or on semiconductor regions where these impurity regions are to be formed; producing the charge storage film on surfaces of the auxiliary layers and a surface of the channel formation region; forming the first control electrodes along the auxiliary layers in a charged charge film inserted state; removing a part of the charge storage film by etching using the first control electrodes as a mask; producing a single-layer dielectric film on a surface of the channel formation region exposed by the removal of the charge storage film and surfaces of the first control electrodes; and forming the second control electrodes on the single-layered dielectric film and the auxiliary layers.

The method for manufacturing a nonvolatile semiconductor memory according to the third embodiment of the invention further includes the steps of: preparing dielectric insulating layers in the form of parallel lines in one direction, and preparing auxiliary layers of polycrystalline or amorphous silicon doped with a second conductive type impurity; in the form of parallel lines in a direction perpendicular to the dielectric insulating layers; and forming the impurity regions of the second conductivity type at semiconductor sites overlapping arrangement regions of the auxiliary layers between the dielectric insulating layers.

In the nonvolatile semiconductor memory according to the first embodiment and the method for manufacturing a nonvolatile semiconductor memory according to the third embodiment of the invention, since the main regions are tapered forwardly on facing surfaces of the two first control electrodes for a memory cell, the control electrodes are formed so that their Width decreases with increasing distance from the channel formation region, no residue of a conductive substance is generated, which would lead to a short circuit between second control electrodes when these second control electrodes are processed. Further, generation of word lines is completed simply by processing the second control electrodes.

In the nonvolatile semiconductor memory according to the second embodiment of the invention, the portions of the charge storage films that are adjacent to the portions of those charge storage films that form storage units on both sides in the longitudinal direction of the first control electrodes extend across the dielectric insulating layers between the channel formation regions. In that simply the thickness of the dielectric insulating layers z. For example, when charges are made in adjacent areas, even if charges are stored in adjacent areas, the effect of the charges on the semiconductor immediately under the dielectric insulating layers becomes extremely weak as compared with that in conventional cases.

BRIEF DESCRIPTION OF THE DRAWINGS

1A FIG. 10 is a plan view of a memory cell according to an embodiment. FIG. 1B is a sectional view taken along a line AA in the 1A ,

2A is a sectional view taken along a line BB in the 1A in the memory cell according to the embodiment. 2 B is a sectional view taken along a line CC in the 1A ,

3 FIG. 11 is a plan view of a memory cell array showing pads for leading out electrodes of control gates in a nonvolatile semiconductor memory according to the embodiment. FIG.

4 FIG. 16 is a sectional view enlarging a key portion of the memory cell in FIG 1A according to the embodiment shows.

5 FIG. 10 is a sectional view after fabricating a sacrificial layer in manufacturing a memory cell according to the embodiment. FIG.

6 FIG. 12 is a sectional view after the formation of openings of patterns of bit lines in the sacrificial layer, etc. in manufacturing a memory cell according to the embodiment. FIG.

7 FIG. 10 is a sectional view after producing bit lines in the manufacture of a memory cell according to the embodiment. FIG.

8th FIG. 12 is a sectional view after thermal oxidation of areas of the bit lines in the manufacture of a memory cell according to the embodiment. FIG.

9 FIG. 15 is a sectional view after the production of a charge storage film in the manufacture of a memory cell according to the embodiment. FIG.

10 FIG. 10 is a sectional view after manufacturing control gates in the manufacture of a memory cell according to the embodiment. FIG.

11 FIG. 12 is a sectional view after removing portions of the charge storage film using the control gates as a mask in the manufacture of a memory cell according to the embodiment. FIG.

12A FIG. 12 is a schematic sectional view of the structure of a memory cell according to a comparative example of the embodiment. FIG. 12B FIG. 12 is a plan view of a memory cell array centered on two memory cells according to the comparative example of the embodiment. FIG.

13 FIG. 10 is a plan view of a memory cell array and control pads according to the comparative example of the embodiment. FIG.

14 is a sectional view taken along a line AA in the 1A to illustrate the modification of the forms of the control gates of the embodiment.

15 FIG. 12 is a sectional view after the production of resist patterns relating to a first method of manufacturing control gates according to the modification. FIG.

16 Fig. 13 is a sectional view after the etching of control gates relating to a first method of manufacturing control gates of the modification.

17 Fig. 10 is a sectional view after etching the charge storage film relating to a first method of manufacturing control gates of the modification.

18 Fig. 10 is a sectional view after embedding a resist relating to a second method of manufacturing control gates of the modification.

19 FIG. 12 is a sectional view after removing portions of an oxidation stopper film relating to a second method of manufacturing control gates of the modification. FIG.

20 Fig. 10 is a sectional view after the production of a dielectric film relating to a second method of manufacturing control gates of the modification.

21 Fig. 10 is a sectional view after removing the remaining oxidation stopper film concerning a second method of manufacturing control gates of the modification.

22 Figure 11 is a sectional view after etching the control gates relating to a second method of fabricating control gates of the modification

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the invention will be explained with reference to the accompanying drawings.

First embodiment

Hereinafter, an embodiment of the invention will be explained with reference to the drawings by taking an example of a nonvolatile memory using n-channel memory cells having a VG (Virtual Ground) type memory cell array.

The 1A is a plan view of a memory cell while the 1B a sectional view taken along the line AA in the 1A is. The 2A is a sectional view taken along the line BB in the 1A while the 2 B a sectional view taken along the line CC in the 1A is.

In these figures, SUB denotes a p-type semiconductor substrate or a p-well or a silicon on insulator (SOI) layer, as well as other various types of p-type semiconductor layers. For the sake of convenience, they are hereinafter referred to as "substrate SUB".

On the substrate SUB, dielectric insulating layers ISO are formed in the form of parallel stripes in the horizontal direction (line direction) in the figures. The insulating dielectric layers ISO are made by the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method or the field isolation method. Here, the field isolation method is used, and on the substrate SUB, a dielectric film (dielectric isolation layer ISO) having a thickness of several tens nm is produced. The line-shaped region along the row direction between the dielectric insulating layers ISO is an active semiconductor region of the memory cell.

In the active semiconductor region, source / drain regions S / D doped with an S-type impurity are formed at a predetermined interval. The part of the active semiconductor region between the source / drain regions S / D is a channel formation region CH of a transistor.

Bit lines BL1 and BL2 of polycrystalline silicon doped with a high concentration of n-type impurity are prepared in the form of parallel lines in the vertical direction (column direction) of the figure at right angles to the row direction. The bit lines BL1 and BL2 are in contact with the source / drain regions S / D of the memory cell in the column direction while intersecting the dielectric insulating layers ISO and supplying the memory cell with a common source voltage or drain voltage. The thickness of the polycrystalline silicon constituting the bit lines BL1 and BL2 is z. About 100 nm to 500 nm. The surfaces of the polycrystalline silicon are covered with dielectric films DF1.

Charge storage films CSF each consisting of a plurality of dielectric films are manufactured in a state of being in contact with the dielectric films DF1 on the sides of the bit lines BL1 and BL2 and the end portions of the channel formation region. The charge storage films CSF have L-cut shapes, and are formed in their lower portions with first control electrodes (hereinafter referred to as control gates) CG1 and CG2 having sidewall shapes. The control gates CG1 and CG2 are formed together with the charge storage films CSF in the column direction along the bit lines BL1 and BL2. The control gates CG1 and CG2, which will be explained in detail later, are used e.g. For example, it is prepared by depositing a polycrystalline silicon film in a state where the surfaces of the bit lines BL1 and BL2 are covered with the dielectric films DF1 and the charge trapping films CSF, and the same is etched back. The control gates CG1 and CG2 are maintained in a state in which dielectric films are inserted on the side surfaces of the bit lines BL1 and BL2. Accordingly, the bit lines BL1 and BL2 function as "auxiliary layers" for the control gates CG1 and CG2. Further, the portions of the charge storage film which are sandwiched between the control electrodes CG1 and CG2 and the channel formation region CH, that is, d. H. the lower portions of the charge storage films CSF, to "storage units", are injected with charges for storing information.

The main areas of facing surfaces of the control gates CG1 and CG2 are tapered forward or the control gates are formed so that their width decreases with increasing distance from the channel formation area. The advantages resulting from the forward taper of the facing surfaces will be explained later. On the facing surfaces of the control gates CG1 and CG2 and on the channel formation region CH, a single-layered dielectric film DF2 is produced.

A word line WL is made by means of a conductive substance embedded in the space between the control gates. The word line WL is formed with substantially the same pattern as the active semiconductor region while intersecting the dielectric films DF1 on the bit lines BL1 and BL2. Further, side walls WL 'of a conductive substance are formed on the side surfaces of the two sides of the word lines WL in the width direction.

The reason for attaching the side walls WL 'is as follows.

In order to minimize the cell size in the column direction, it is desirable that the lines and spaces of the dielectric isolation layers ISO and the line and space of the word line WL are respectively formed with a minimum line width F determined by the resolution limit in photolithography. In this case, the width of the space between the dielectric insulating layers ISO, that is, the width of the active semiconductor region inevitably becomes almost equal to the width of the word line WL, so that there is no additional margin for positioning the two. Accordingly, in the space between the facing control gates CG1 and CG2, as shown in FIG 2 B That is, when the word line WL deviates in the width direction with respect to the active semiconductor region (channel formation region CH), finally, a region that is not superimposed on the word line WL is generated in a part of the channel formation region CH. Since this region is not subject to the electric field of the word line WL, it becomes a leakage path between the source and the drain. As a result, the channel can not be turned off. In particular, due to a deviation of the word line in the width direction, an area at which no hot electrons are injected is generated at the end of the memory unit. However, when information is erased using injection of hot holes, they are injected into the end of the memory unit because the end of the memory unit is subjected to the electric field of the control gate, and only the threshold voltage falls in the portion of the semiconductor just below the end, and finally the leakage current increases through this section.

Further, there is a problem of reducing the channel width due to a deviation of the word line WL. A reduction of the word line width leads to a decrease of the read current. Along with an increase in the leakage current, this is accompanied by the disadvantage that the decrease of the S / N ratio of a read signal is accelerated.

In the present embodiment, by attaching the side walls WL 'which considerably increase the width of the word line WL at the side surfaces thereof, it becomes possible to prevent the above-described formation of leakage path and channel width reduction while the word line WL of minimum line width W will be produced. It should be noted that the widths of the side walls WL 'must be the same as the adjustment tolerance in the photolithography, or larger, in order to achieve the purpose. Further, to achieve the purpose of processing the word line WL, it is essential not to proceed and etch the underlying dielectric film DF2. The reason is that when the dielectric film DF2 does not completely cover the surface of the channel formation region CH, the sidewalls WL 'directly contact the surface of the channel formation region CH when the word line WL in the width direction in FIG 2 B differs. Therefore, this situation must be prevented.

A memory cell having the above configuration is manufactured by connecting in series a central word transistor WT having a word line WL as a gate and two memory transistors MTa and MTb positioned on the two sides of the word transistor WT and having the control gates CG1 and CG2 become. That is, the word transistor WT operates during operation by using the channels of the two memory transistors MTa and MTb as source and drain, while the memory transistors MTa and MTb operate by connecting one of the source / drain regions S / D and the channel of the word transistor WT as source and drain.

The 3 Fig. 10 is a plan view of a memory cell array also showing pads for leading out the electrodes of the control gates.

The illustrated example corresponds to a control method in which the pair of control gates CG1, the pair of control gates CG2, and the pair of control gates CG3 on the two sides of a bit line are controlled by the same potential. In the present embodiment, since the control gates are made of conductive layers of Sidewall type, which are formed around the bit lines around, the two control gates in a memory cell, ie the control gates CG1 and CG2 or the control gates CG2 and CG3, already isolated in the manufacture of the control gates. Accordingly, it is not necessary to cut apart the two control gates in a memory cell.

To make the control pads CP1, CP2, and CP3 in the manufacture of the control gates, a conductive film for forming the control gates is deposited, then protective films having large areas are etched, and rectangular patterns are formed on the areas to form the control pads CP1, CP2, and CP3 and then there is a re-etching. After etching back, the etch stop layer is removed, whereupon the control pads CP1, CP2 and CP3 remain in these sections. The 3 is an example of producing control pads for connecting the short sides of annular control gates.

It should be noted that if it is desired to improve the degree of freedom of serial access between memory cells in the row direction by separately supplying different voltages to the control gates between adjacent cells, a step will be required where the control gates on the two sides a bit line are cut apart, and control pads must be made separately for the cut-through control gates.

The 4 Fig. 10 is a sectional view showing enlarged a key portion of a memory cell.

As it is in the 4 are charge storage films CSF z. B. of three layers of a dielectric film. The bottom film BTM and the top film TOP exist z. Example of silica, silicon oxynitride or silicon nitride with little charge traps. The lower film BTM acts as a potential barrier to the substrate while the upper film TOP acts as a film for preventing escape of stored charges to the gate side or for preventing intrusion of unnecessary charges from the gate side. A central film CS contains a large number of charge cases and acts as a film for mainly storing a charge. The central film CS is made of silicon nitride or silicon oxynitride containing a large number of traps, or an insulating substance (dielectric) of a metal oxide, etc.

When a charge is injected into a memory unit 1 in a write operation, a positive drain voltage is applied to the bit line BL1, a reference voltage is supplied to the bit line BL2, individually optimized positive voltages are supplied to the control gates CG1 and CG2, and the word line WL becomes a positive voltage from a value at which a channel is formed. In this case, electrons which are supplied to the channel from the source / drain region S / D connected to the bit line BL2 are accelerated in the channel, thereby being on the side of the source / drain region S / D connected to the bit line BL1 achieve high energy so that they pass over the potential barrier of the lower film BTM and injected into the storage unit 1 and stored.

When charges are injected into the memory unit 2, the voltages between the control gates CG1 and CG2 are switched, and the voltages between the bit lines BL1 and BL2 are switched. As a result, the electron supply side and the side where the electrons acquire high energy are reversed from the above case, and the electrons are injected into the storage unit 2.

In a read operation, a predetermined read drain voltage is applied between the bit lines BL1 and BL2, so that the memory page on which a bit to be read is written becomes the source. Further, optimized positive voltages, which are low enough to turn on the channel but do not change the threshold voltages of the memory transistors MTa and MTb, are supplied to the control gates CG1 and CG2 and the word line WL. At this time, the channel conductivity changes effectively due to the difference in the amounts of stored charges in the memory unit to be read or by the presence of charges. As a result, stored information is converted to a current value or a potential difference on the drain side and read.

When the other bit is read, the bit line voltages are switched or the control gate voltages are switched so that the memory page in which the bit is written becomes the source, thereby performing a read operation in the same manner as above.

In an erase operation, an erase voltage in the reverse direction is supplied to that in the above write operation so that the channel formation area CH and the source / drain area S / D side become high and the control gate electrode CG1 and / or CG2 side goes low. As a result, the stored charge is withdrawn from one of the storage units or both to the side of the substrate SUB, and the storage transistor returns to the erased state. It is to be noted that as another erasing method, a method in which high-energy reverse polarity charge is used may be used stored charge, which is generated in the vicinity of a not shown pn junction on the side of the source / drain region S / D or within the substrate by an electric field of the control gates for injection into the memory is attracted.

Next, referring to the in the 5 to 11 illustrated sectional views of a method for producing a memory cell explained.

First, the substrate SUB, as in the 1A and the 3 represented on its upper side with parallel, strip-shaped dielectric insulating layers ISO along the row direction. On the entire surface H) of the dielectric insulating layers ISO and on the active semiconductor region between them, as in FIG 5 3, a pad layer PAD, an oxidation stopper OS, and a sacrificial layer SF are sequentially formed. The oxidation stopper OS is a difficult to oxidize, dense film, and it consists for. B. from about 50 nm thick silicon nitride. The underlying pad layer PAD is a thin film made as required to improve the adhesion of the oxidation stopper OS to the substrate SUB and release stress, and consists e.g. B. from a silicon dioxide film of about 5 nm to 8 nm thickness. The sacrificial layer SF is a film made of a material having higher selectivity in etching than the oxidation stopper OS, and is composed of e.g. B. of a silicon dioxide film. The film thickness is determined according to the height of the bit lines.

The stacked films PAD, OS, and SF are patterned using a resist, etc. as a mask for forming parallel stripe-shaped openings along the column direction. The insulating dielectric layers ISO and the active semiconductor regions are alternately arranged and exposed in the openings along the longitudinal direction.

By depositing thick polycrystalline silicon doped with a high concentration n-type impurity and polishing or re-etching the surface, insulation is formed on the surface of the sacrificial layer SF. As a result, as stated in the 7 2, bit lines BL1 and BL2 embedded in the openings of the stacked films PAD, OS and SF are formed. The bit lines BL1 and BL2 electrically connect the active semiconductor regions exposed at the bottoms of the openings.

The sacrificial layer SF is selectively removed, and then the exposed surfaces of the bit lines BL1 and BL2 are thermally oxidized to form a dielectric film DF1 of e.g. B. 10 nm thickness form. By optimizing the thicknesses of the dielectric film DF1 and the oxidation stopper OS, the oxidation proceeds sufficiently even on the end faces of the oxidation stopper OS, so that the dielectric film DF1 of sufficient thickness can completely cover the surfaces of the bit lines BL1 and BL2. Further, in the heating step, n-type impurities diffuse into the active semiconductor region by using the polycrystalline silicon of the bit lines BL1 and BL2 as a solid-state diffusion source. As a result, source / drain regions S / D are formed. It should be noted that if the depth of the source / drain regions S / D and the concentration of the impurities in diffusion alone are insufficient, it is sufficient to preliminarily add impurities of required concentration in advance by additional heating or ion implantation through the apertures in the previous one Step in the 6 into the active semiconductor regions.

The oxidation stopper OS and the pad layer PAD are successively removed, and a charge storage film CSF is formed on the entire surface including the exposed channel formation region CH and the surfaces of the dielectric film DF1. It should be noted that if the channel forming area CSF is the one in the 4 Having shown three-layer structure and the lower film BTM is prepared by thermal oxidation, this lower film BTM is made only on the surface of the channel formation region CH.

Polycrystalline silicon which is sufficiently doped with impurities is thickly deposited, and at required locations on the polycrystalline silicon, etching protection layers for producing the inks 3 formed control pads CP1, CP2, CP3, ..., and then the polycrystalline silicon is etched back. Thereby, at the two side surfaces of the bit lines BL1 and BL2 in a state in which the dielectric films DF1 and the film CSF are inserted, control gates CG1 and CG2 having sidewall shapes are formed. Further, control pads CP1, CP2, CP3, ..., which are appropriately connected to the control gates CG1, CG2, CG3, ..., are simultaneously formed. At this time, the thickness of the polycrystalline silicon sufficiently doped with impurities is strictly controlled by determining the control gate width.

Next, the etch stop layer is removed.

To the structure according to the 1B First, the charge storage film CSF is etched using the control gates CG1 and CG2 as a mask. Thereby, the portion of the charge storage film becomes on the channel formation area CH between the control electrodes CG1 and CG2 and the portions of the charge storage film over the bit lines BL1 and BL2. Next, the surface is thermally oxidized to form a silicon dioxide film on the surfaces of the control electrodes CG1 and CG2 and the surface of the channel formation region CH exposed therebetween. Thereby, a single-layered dielectric film DF2 is formed on the surfaces of the polycrystalline or single-crystal silicon, but not on the other portions which are not highly thermally oxidized since they are made of a dielectric film. It is to be noted that even if the thickness of the gate oxide film of a MOS transistor in the center is small, insulation between interconnections is sufficiently provided because the thickness in the thermal oxidation of the doped polycrystalline silicon is twice the thickness of the monocrystalline silicon ,

Next, a conductive material for forming the word line is thickly deposited on the entire surface, and parallel, stripe-shaped patterns of a resist, etc. are formed thereon in the row direction. The conductive material is processed by RIE or other strong anisotropy etching using these patterns as a mask to produce a word line WL. Further, sidewalls WL 'become the word line WL as shown in FIG 2 B illustrated, formed. By the above, the basic structure of a memory cell is completed.

Next, advantages of the memory cell structure according to the present embodiment over the memory cell structure described in the above publication indicating a prior art will be explained. It should be noted that in the following explanation, a case where a control gate is divided into two side walls in the sectional structure described in the above publication is used in the following explanation, but the advantages of the invention remain the same even if the control gate is not is divided.

The 12A Fig. 12 is a view showing the sectional structure of the cell described in the above publication in the row direction when a control gate is divided into two. The 12B is a plan view, which is drawn centrally to two memory cells. The 13 Fig. 10 is a plan view of a memory cell array with control pads. It is to be noted that in these figures, reference numerals denoting the same configurations as in the present embodiment are given according to the same standard as in the present embodiment.

The memory cell of the comparative example is the same as the memory cell of the present embodiment in terms of the basic cell configuration including the point that a word transistor WT and two memory transistors MTa and MTb embedding these are connected in series.

However, the memory cell of the comparative example is very different in structure from the memory cell of the present embodiment in the point that it has word gates WG connected to a word line WL and at the side surfaces with control gates CG1, CG2 and CG3 having sidewall shapes in one state in which charge storage films CSF are inserted, and by the point that it has no dielectric insulating layers ISO for isolating cells in the column direction. The control gates CG1, CG2 and CG3 must be formed in the column direction, so that the word gates forming auxiliary layers during manufacture must also be formed in the form of parallel strips in the column direction. On the other hand, in order to electrically isolate word lines WL, it is necessary to cut the strip-shaped word gates WG into isolated patterns for each cell. These points are clear from the cell structure.

Hereinafter, a manufacturing method as expected for the cell structure of the comparative example will be explained simply in order.

First, a single-layered dielectric film DF and a conductive film for forming word gates WG are deposited on a substrate SUB and patterned to form parallel stripe patterns in the column direction. On the entire surface including the pattern surfaces and the surface of the substrate SUB, a charge storage film CSF is made of an ONO film. In this state, polycrystalline silicon doped with impurities is thickly deposited to embed the interstices between the conductive layers to produce the word gates WG. Etching coatings are applied to required locations, e.g. At the positions of the control gate pads CP1, CP2, CP3,..., As in FIG 13 represented, manufactured. In this state, the polycrystalline silicon is etched back under conditions of strong anisotropy. As a result, polycrystalline silicon sidewalls are formed on the both sides of the conductive layers as control gates CG1, CG1, CG2, CG2, CG3, CG3, ... to make the word gates WG in a state where the charge storage film CSF is interposed. Further, the control pads CP1, CP2, CP3, ... are simultaneously formed. The surfaces of the side walls made of polycrystalline silicon (side walls of polycrystalline silicon) are oxidized by thermal oxidation and then n-type impurities are injected into the regions of the substrate surface between the polycrystalline silicon sidewalls by ion implantation using the polycrystalline silicon sidewalls and the conductive layers forming the word gates WG as masks to source / Form drain regions S / D. Then, silicon oxide or other dielectric is embedded in the interstices between the polycrystalline silicon sidewalls, and then polished or etched back to flatten the surface of the dielectric so that the surface heights become substantially equal to those of the conductive layers for forming the word gates WG. The planarization exposes the surfaces of the conductive layers to form the word gates WG, but stops at such a degree that the surfaces of the polycrystalline silicon sidewalls are not exposed due to the presence of the thermal oxide film.

Next, on the level surface, a conductive material for forming the word lines WL is deposited, and parallel resist strips in the row direction are formed thereon. The conductor is etched using the resist as a mask to isolate the word lines WL. Also, next, the conductive layer exposed at the bottom between the word lines WL is divided by etching. As a result, word gates WG are generated with patterns isolated for each cell.

A first problem with the comparative example is the fact that residues of polycrystalline silicon tend to be generated when dividing the conductive layers to form the word gates WG into patterns for each cell in the final step. That is, as explained above, since the section of a conductive layer for producing a word gate WG is trapezoidal, when the division is made, it is required to dig in a hole having a reverse tapered side surface. As a result, polycrystalline silicon tends to remain in a stripe at the lowest point of the part shaded from the surface opening, that is, in a portion along the bottom of the side surface as shown in FIG 12B is shown. Since such a residue of polycrystalline silicon causes an electrical short between word gates WG, the memory cell array suffers from short circuits of the word lines.

In the cell structure according to the present embodiment, a division of the word gates WG is unnecessary because no conductive layers exist for producing the word gates WG. Further, in insulating the word lines WL, the leg portions of the etched-away portions have forwardly tapered side surfaces, reflecting the shapes of the sidewall-type control gates. Accordingly, there is the advantage that not easily conductive material remains in these sections.

A second problem with the comparative example is that there are no dielectric insulating layers ISO as in the present embodiment, so that charges tend to accumulate continuously in regions of the charge storage films CSF adjacent to memory units when rewrite operations are often repeated. In particular, charges that are injected only during rewrite operations, e.g. For example, for discharging, injected charges of the reverse polarity (electron holes) are only injected but not drawn off, so that they easily accumulate gradually in these regions. As a result, leak paths are easily generated outside the channels. The 12B shows charge accumulation areas and the directions of the leak paths.

In the present embodiment, the portion of the charge storage film CSF corresponding to the channel formation region CH in FIG 2A in contact, a storage unit. Adjacent areas of the memory unit lie over the dielectric insulating layers ISO. Accordingly, there is an advantage that although charges accumulate continuously in the adjacent area, these charges do not affect the channel and leak paths are not generated. It should be noted that, when the dielectric insulating layers are formed by the LOCOS or the STI method, it is more difficult to generate a leakage current because the surface area of the substrate is isolated.

As a third problem with the comparison example, as it is in the 13 6, since the control gates are annularly formed so as to surround the conductive layers to form the word gates WG, the word gates are cut through, e.g. At two points on the short sides of the conductive layers. This is because efficient 2-bit memory operations become difficult unless the two control gates CG1 and CG2, CG2 and CG3, ... in a memory cell can be independently supplied with different voltages.

In the cell structure of the present embodiment, the two control gates CG1 and CG2, CG2 and CG3,... Are already isolated in each memory cell during manufacture, as shown in FIG 3 is shown. Accordingly, in the present embodiment, as far as adjacent control gates CG1 and CG1, CG2 and CG2, ... having the same potential are used, there is an advantage in that a step of cutting the control gates is unnecessary. It should be noted that then, if it is desired to independently drive all the control gates to increase the degree of freedom in serial access operation to a VG cell array, the control gates CG1 and CG1, CG2 and CG2, 3 have to be cut through. The interfaces for the control gates differ from those of the comparative example. The number of interfaces is the same.

Notwithstanding the above, in the present embodiment, an auxiliary layer is made of a conductive material (eg polycrystalline silicon doped with impurities), and the resistances of the bit lines BL1, BL2, ... are reduced as compared with the comparative example in which they are only through Foreign substance areas are formed, wherein bit lines are embedded in the semiconductor.

Further, in the present embodiment, it is possible to reduce the channel lengths of the word transistors WT from the minimum line width F. The sources and drains of the word transistors WT are the channels of the memory transistors MTa and MTb, so that even if the channel lengths of the word transistors WT are made smaller, a penetration problem hardly occurs.

Further, in the present embodiment, a number of modifications can be made within the scope of the technical concept of the invention.

For example, the auxiliary layer for fabricating the control gates is not limited to polycrystalline silicon, and may be made of amorphous silicon or other conductors or a dielectric. In this case, it is necessary to form the source / drain regions by being buried under the dielectric insulating layers ISO, or the dielectric insulating layers ISO are applied to the two sides of the memory units and to the source / drain regions S / D are cut off. As a result, the source / drain regions S / D are formed in a line shape in the column direction, and they are used as bit lines.

Further, it is also possible not to form the dielectric film DF1 by thermal oxidation on the surface of the polycrystalline silicon in the step of FIG 8th but the charge storage film CSF in the step of 9 manufacture. In this case, in the step of 11 the surfaces of the polycrystalline silicon for producing the bit lines BL1, BL2,... are exposed by etching the charge storage film CSF, but in the subsequent thermal oxidation of the surfaces of the control gates CG1, CG2,..., also the surfaces of the polycrystalline silicon for producing the bit lines thermally oxidized, and silicon dioxide films are produced. Thus, the insulating film for word lines can be sufficiently formed. In this method, the step of forming the pad layers PAD and the oxidation stopper OS are in the 5 , the step of later removal and the step of thermal oxidation in the 8th superfluous, so there is an advantage in that the process can be simplified to that extent.

Further, the shapes of the control gates CG1, CG2, ... are not limited to the sidewall shapes formed on the sides of the auxiliary layers (bit lines BL1, BL2, ... in the above explanation) of a conductor or a dielectric. For example, as it may in the 14 is shown, the control gates CG1, CG2, .... consist of shapes that cover the sides and the surfaces of the bit lines BL1, BL2, ..., as shown in the 14 is shown. It should be noted that the shapes are limited to applications using control gates belonging to different cells from which the bitlines extend, with the same potential electrically applied.

Further, in this configuration, the charge storage films CSF are inevitably formed so as to cover the sides and the surfaces of the bit lines BL1, BL2,.... This is because in the step of insulating the charge storage films CSF according to the above 11 the portions of the charge storage films on the bit lines are protected by the control gates CG1, CG2,.

Two examples of a method for manufacturing the control gates CG1, CG2, ... will be explained below with reference to the drawings.

The first method is in the 15 to 17 illustrated. This manufacturing method can be carried out by the above-mentioned, in the 10 illustrated step of producing control gates of the sidewall type by in the 15 and 16 illustrated steps is replaced.

After making the bit lines BL1, BL2, the source / drain regions S / D, the dielectric SF1 and the charge storage film CSF by the same steps as in FIGS 5 to 9 will, as it is in the 15 is shown, a conductive film CSF, the z. B. of polycrystalline or amorphous silicon, made on the whole surface. Further, on those portions of the conductive film CGF lying on the bit lines BL1 and BL2, resist patterns R1 are formed by photolithography.

The conductive film CGF is patterned by etching using the resist patterns R1 as a mask. This will, as in the 16 is shown, the control gates CG1 and CG2, which are isolated in the upper part of the center of the channel formation region prepared.

It is desirable that the etching be carried out under conditions of sufficiently strong anisotropy and with a small clearance of the resist patterns R1. Along with a reduction in the thickness of the resist patterns R1 during the etching, the edges thereof are recessed, and as a result, the major portions of the side surfaces of the control gates CG1 and CG2 are tapered forward. It should be noted that the edges of the resist patterns R1 are rounded in advance, e.g. B. by a post-annealing at a relatively high temperature to make the austerity of the edges easier.

As it is in the 17 is shown, the charge storage film CSF is separated by etching using the control gates CG1 and CG2 as a mask. Furthermore, the structure of the 14 to obtain the dielectric films DF2 and the word line WL by the same method as explained above to complete the basic structure of the memory cell.

The second method is one for producing a mask layer in processing the conductive film CGF by self-aligning with the shape of the base. The second method is in the 18 to 22 illustrated. This manufacturing method can be carried out by that in the 10 shown and explained above step of producing control gates of the sidewall type by in the 18 to 22 illustrated steps is replaced.

After making the bit lines BL1, BL2l, the source / drain regions S / D, the dielectric CF1 and the charge storage film CSF by the same steps as described in FIGS 5 to 9 as is shown in the 18 is shown, a conductive film CGF of z. B. polycrystalline or amorphous silicon on the entire surface. Next, on the surface of the conductive film CGF, an oxidation stopper film OSF of e.g. As silicon nitride made thin. Further, a resist is applied, baked, and then etched back to embed recessed portions on the surface through a resist R2.

By etching in this state using the resist R2 as a mask, as shown in FIG 19 is shown, parts of the Oxidationsstoppfms OS over the bit lines BL1 and BL2 removed.

The resist R2 is removed, and then the conductive film CGF exposed around the oxidation stopper film OSF is selectively thermally oxidized to form dielectric films DF2 via the bit lines BL1 and BL2, as shown in FIG 20 is shown.

As it is in the 21 is shown, the Oxidationsstoppfmm OSF is removed.

The conductive film CGF is patterned by etching using the dielectric films DF2 as a mask. As a result, as stated in the 22 is formed, control gates CG1 and CG2, which are separated in the upper part of the center of the channel forming area formed.

It is desirable that the etching be carried out under conditions of sufficiently strong anisotropy and sparing of the dielectric films DF2. Since the dielectric films DF2 are fabricated by selective oxidation using the oxidation stop film OSF, the closer it is to the front end, the smaller the thickness, in the same manner as in the aforementioned bird's beak in LOCOS. Accordingly, along with a reduction in the thickness of the dielectric films DF2 during the etching of the control gates, the edges of the dielectric films DF2 are recessed. As a result, the major portions of the side surfaces of the control gates CG1 and CG2 are tapered forward.

Next, an etching process is performed by using the control gates CG1 and CG2 as a mask to separate the charge storage film. Furthermore, the structure of the 14 to produce dielectric films DF2 on the sides of the control gates CG1 and CG2, and the word line WL is manufactured by the same method as explained above to complete the basic structure of the memory cell.

In the nonvolatile semiconductor memory and the method of manufacturing according to the invention, the step of connecting word gate electrodes and a word line as in the prior art is unnecessary, and no residue of a conductive material is generated which would cause a short circuit between second control electrodes.

Even if uncontrollable charges continuously accumulate in nearby areas outside the memory units in the direction along the first control electrodes, the presence of the dielectric insulating layers causes the effect of charges on the channel to be considerably weakened, resulting in leaking characteristics even if rewrite operations are performed repeatedly.

The two first control electrodes in a memory cell are already isolated during manufacture, so that a process for separating them for independent control becomes superfluous.

When the auxiliary layer is made of a conductive material, the resistance of the bit lines is considerably reduced as compared with the case of configuring the bit lines only by impurity regions embedded in the semiconductor. Further, when the first control electrodes are formed to cover the side surfaces and the upper surface of the auxiliary layer, the resistances of the first control electrodes are reduced as compared with sidewall shapes.

Further, even if the widths of lines and spaces of the second control electrodes are formed with the minimum limit in lithography processes, the leakage current is not increased, and the channel width is not reduced as a result of misalignment of the second control electrodes. As a result, the S / N ratio for a read signal does not decrease.

LIST OF REFERENCE SIGNS

• MTa, MTb

  memory transistors

  WT

  word transistor

  WL, WL1, WL2, WL3

  Word lines (second control electrodes)

  WL

  Side wall

  BL1, BL2, BL3

  bit

  CG1, CG21, CG3

  Control gates (first control electrodes)

  ISO

  dielectric insulating layer

  SUB

  Substrate (semiconductor)

  S / D

  Source / drain region (impurity region)

  CH

  Channel forming region

  DF1

  dielectric film

  DF2

  single layer dielectric film

  CSF

  Charge storage film

  CP1, CP2, CP3

  Control contact pads (lead-out areas of the first control electrode)

  BTM

  lower film

  CS

  central charge storage film

  TOP

  upper film

  PAD

  Pad layer

  OS

  oxidation stopper

  SF

  sacrificial layer

  WG

  word gate

  OSF

  Oxidation stopper film

  R1, R2

  resistors

Claims (26)

A non-volatile semiconductor memory having a memory cell, comprising A channel formation region (CH) made of a semiconductor; Charge storage films (CSF) each of a number of stacked dielectric films with charge retention capability; Two memories of areas of the charge storage films (CSF) overlapping two ends of the channel forming area (CH); A single-layered dielectric film (DF2) in contact with the channel formation region (CH) between the memory units; - Two first control electrodes (CG1, CG2), each one of which is assigned to a memory unit, and which are formed so that their width decreases with increasing distance from the channel forming region; and a second control electrode (WL) embedded in the space between the two first control electrodes (CG1, CG2) in a state insulated from the first control electrodes (CG1, CG2), with the single-layered dielectric film (DF2) in Contact stands. The nonvolatile semiconductor memory according to claim 1, wherein the memory cell further comprises: Two impurity regions (S / D) of a reverse conduction type semiconductor to that of the channel formation region (CH) separated therefrom; and Two auxiliary layers (BL1, BL2) formed on the two impurity regions (S / D) near each surface of the first control electrodes (CG1, CG2) facing the outside of the memory cell. A nonvolatile semiconductor memory according to claim 2, wherein the auxiliary layers (BL1, BL2) comprise conductive layers near the outsides of the first control electrodes in a dielectric film inserted state (DF1). A nonvolatile semiconductor memory according to claim 3, wherein the conductive layers comprise layers of polycrystalline or amorphous silicon doped with an impurity of the same conductivity type as that of the impurity regions (S / D). A non-volatile semiconductor memory according to claim 2, wherein the auxiliary layers (BL1, BL2) comprise dielectric layers (DF1) near the outsides of the first control electrodes. A non-volatile semiconductor memory according to claim 2, wherein A number of memory cells each having the channel formation region (CH), the two memory units, the first and second control electrodes (CG1, CG2, WL), the two auxiliary layers (BL1, BL2) and the two impurity regions (S / D) in a matrix are arranged to form a memory cell array, - The two auxiliary layers (BL1, BL2) are arranged in the column direction and they are common to a number of memory cells and they are common to two memory cells adjacent in the row direction; - wherein the two first control electrodes (CG1, CG2) are arranged along the two auxiliary layers (BL1, BL2) and they are common to a number of memory cells; and - wherein the second control electrode (WL) is arranged in the row direction and is common to a number of memory cells. A nonvolatile semiconductor memory according to claim 6, wherein two first control electrodes (CG1, CG2) which widthwise embed the two sides of the auxiliary layers (BL1, BL2) common to two memory cells adjacent in the row direction are electrically connected. A nonvolatile semiconductor memory according to claim 7, wherein: The first control electrodes (OG1, CG2) have sidewall-shaped conductive layers formed on the two sides in the width direction of the auxiliary layers (BL1, BL2); and - Wherein two first control electrodes (CG1, CG2) are connected to said side wall form outside of the memory cell array with each other. A nonvolatile semiconductor memory according to claim 7, wherein said first control electrodes (CG1, CG2) have conductive layers covering the two sides and the surfaces of the auxiliary layers (BL1, BL2). A nonvolatile semiconductor memory according to claim 6, wherein the dielectric insulating films (DF2) for electrically insulating the channel forming region (CH) between memory cells adjacent in the row direction are formed between second control electrodes (WL) at least in surface regions of the semiconductor. A non-volatile semiconductor memory according to claim 10, wherein: - The second control electrodes (WL) on the two sides in the width direction side walls have; and - The side walls overlap with edges of the dielectric insulating layers (DF2). A non-volatile semiconductor memory having a number of memory cells each having: A channel formation region (CH) made of a semiconductor of first conductivity type; A first and a second impurity region (S / D) of a second conductivity type semiconductor which are separated from each other in the separation direction over the channel formation region (CH); - control electrodes (CG1, CG2) arranged in a direction perpendicular to the separation direction of the first and second impurity regions (S / D) and common to a number of memory cells; and Charge storage films (CSF) each of a plurality of dielectric films formed in layers immediately under the control electrodes (CG1, CG2) and storing information in portions overlapping with the channel formation region (CH); being in this store Memory cells which are adjacent in the direction perpendicular to the separation direction of the first and second impurity regions (S / D) are electrically insulated by dielectric insulating layers (ISO); and - Pairs of the first impurity regions (S / D) and pairs of the second impurity regions (S / D) of the adjacent memory cells, which are isolated by the electrical insulating layer (ISO), respectively by conductive layers (BL1 / BL2) are connected. A method of fabricating a nonvolatile semiconductor memory having a channel formation region (CH) of a first conductivity type semiconductor, two impurity regions (S / D) separated therefrom in a separation direction and composed of a second conductivity type semiconductor, two first control electrodes (CG1, CG2) formed at two ends of the channel formation region (CH) near the two impurity regions (S / D) in a state with inserted charge storage films (CSF) each consisting of a plurality of dielectric films, and a second control electrode (WL) that faces the channel formation region (CH) between the first control electrodes (CG1, CG2) in a single-layered dielectric film (DF2) inserted state and is disposed in the separation direction of the impurity regions (S / D); this method of manufacturing a nonvolatile semiconductor memory comprises the steps of: forming line auxiliary layers (BL1, BL2) in the direction perpendicular to the direction of separation of the impurity regions thereon or on semiconductor regions where these impurity regions are to be formed; - forming the charge storage film (CSF) on surfaces of the auxiliary layers (BL1, BL2) and a surface of the channel formation region (CH); - producing the first control electrodes (CG1, CG2) along the auxiliary layers (BL1, BL2) in a charge storage film (CSF) inserted state; Removing a portion of the charge storage film (CSF) by etching using the first control electrodes (CG1, CG2) as a mask; - forming a single-layer dielectric film (DF2) on a surface of the channel formation region (CH) exposed by the removal of the charge storage film (CSF) and surfaces of the first control electrodes (CG1, CG2); and - producing the second control electrodes (WL) on the single-layered dielectric film (DF2) and the auxiliary layers (BL1, BL2). A method of manufacturing a nonvolatile semiconductor memory according to claim 13, wherein said auxiliary layers (BL1, BL2) comprise dielectric layers (DF1). A method of manufacturing a nonvolatile semiconductor memory according to claim 13, wherein said auxiliary layers (BL1, BL2) comprise conductive layers. A method of manufacturing a nonvolatile semiconductor memory according to claim 15, wherein said auxiliary layers (BL1, BL2) comprise polycrystalline or amorphous silicon doped with a second conductivity type impurity. A method of manufacturing a nonvolatile semiconductor memory according to claim 16, further comprising the step of forming the second conductivity type impurity regions (S / D) by solid-state diffusion using said auxiliary layers (BL1, BL2) as diffusion sources. The method for producing a nonvolatile semiconductor memory according to claim 16, further comprising the step of selectively thermally oxidizing the surfaces of the polycrystalline or amorphous silicon constituting the auxiliary layers (BL1, BL2) to provide insulation between the second control electrodes (WL) and the auxiliary layers (Fig. BL1, BL2). The method of manufacturing a nonvolatile semiconductor memory according to claim 18, wherein the step of preparing the auxiliary layers (BL1, BL2) includes the steps of: Coating a pad oxide film, a nitride film and a sacrificial film in this order to form a film stack; Removing parts of the film stack by etching; Embedding polycrystalline or amorphous silicon doped with a second conductivity type impurity into portions from which the film stack has been removed to produce the auxiliary layers; - Remove the sacrificial layer and Thermally oxidizing the surfaces of the polycrystalline or amorphous silicon using the nitride film as the oxidation stopper film. The method for producing a nonvolatile semiconductor memory according to claim 19, wherein when the surfaces of the polycrystalline or amorphous silicon are thermally oxidized, the impurity regions (S / D) of the second conductivity type are formed by solid diffusion using the polycrystalline or amorphous silicon as the diffusion source. The method of manufacturing a nonvolatile semiconductor memory according to claim 19, wherein the step of preparing the auxiliary layers further includes the steps of: - Making openings in the film stack by patterns of the auxiliary layers; - doping a second conductivity type impurity through the openings to form the second conductivity type impurity regions in the semiconductor regions exposed at the bottoms of the openings; and Embedding polycrystalline or amorphous silicon doped with impurities into the openings. A method of manufacturing a nonvolatile semiconductor memory according to claim 13, wherein, in the step of manufacturing the first control electrodes (CG1, CG2), first control electrodes of sidewall shapes are formed on the two sides in the width direction of the auxiliary layers (BL1, BL2) by depositing and back etching a conductive film become. The method of manufacturing a nonvolatile semiconductor memory according to claim 13, wherein the step of preparing the first control electrodes (CG1, CG2) further includes the steps of: - depositing a conductive film (CGF); - forming an etch stop layer (R1) on the conductive film (CGF) overlying the auxiliary layers (BL1); and Etching the conductive film (CGF) while protecting the upper portions of the auxiliary layers (BL1, BL2) by the etching protection layer (R1) to separate the conductive film (CGF) in a portion over the central portion of the channel formation region (CG) CH) is located. The method of manufacturing a nonvolatile semiconductor memory according to claim 23, wherein the step of preparing the etching protection layer (R1) further includes the steps of: Forming an oxide stopper film (OSF) on inner walls of a recess in the conductive film (CGF), which is formed to reflect the shapes of the auxiliary layers; - thermally oxidizing the surfaces of portions of the conductive film (CGF) overlying the auxiliary layers which are not covered with the oxidation stop film (OSF) to form the etch stop layer (DF2); and - removing the oxidation stop film (OSF). A method of manufacturing a nonvolatile semiconductor memory according to claim 13, further comprising the steps of: Fabricating dielectric insulating layers (ISO) in the form of parallel lines in one direction; and producing polycrystalline or amorphous silicon auxiliary layers (BL1, BL2) doped with a second conductivity type impurity in the form of parallel lines in a direction perpendicular to the dielectric insulating layers (ISO); and - forming the impurity regions (S / D) of the second conductivity type at semiconductor sites which overlap arrangement regions of the auxiliary layers (BL1, BL2) between the dielectric insulating layers (ISO). The method of manufacturing a nonvolatile semiconductor memory according to claim 13, wherein the step of preparing the first control electrode (CG1, CG2) includes the steps of: Depositing a conductive film (CGF) to produce the first conductive electrodes; Forming an etching protection layer (R1) on portions of the conductive film (CGF) to form lead-out areas for the first control electrodes (CG1, CG2); and - Etching of the conductive film (CGF).

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