DE102004038970A1 - HF intermediate connection for multiple wiring structures comprises an electrically conducting filler or coating on the wall of a via - Google Patents
HF intermediate connection for multiple wiring structures comprises an electrically conducting filler or coating on the wall of a via Download PDFInfo
- Publication number
- DE102004038970A1 DE102004038970A1 DE200410038970 DE102004038970A DE102004038970A1 DE 102004038970 A1 DE102004038970 A1 DE 102004038970A1 DE 200410038970 DE200410038970 DE 200410038970 DE 102004038970 A DE102004038970 A DE 102004038970A DE 102004038970 A1 DE102004038970 A1 DE 102004038970A1
- Authority
- DE
- Germany
- Prior art keywords
- interconnect
- sleeve
- overall structure
- layer
- impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
- H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09809—Coaxial layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
Abstract
Description
Die Erfindung betrifft eine HF(Hoch-Frequenz) Zwischenverbindung für Mehrfach-Verdrahtungsebenen mit impedanzdefinierten Leiterbahnstrukturen, wobei die Mehrfach-Verdrahtungsebenen auf konventionellen Verdrahtungsträgern oder in waferebenen realisiert werden, deren Substrat/Laminat eine geringe HF-Dämpfungscharakteristik aufweist.The This invention relates to an RF (high frequency) interconnect for multiple wiring levels with impedance-defined trace structures, the multiple-wiring levels realized on conventional wiring substrates or in wafer planes whose substrate / laminate has a low RF attenuation characteristic.
Der Stand der Technik zeigt, dass dem peripheren Aufbau der angewandten Halbleiterspeicherschaltkreise, der z.B. deren elektrische Kontaktierungsstruktur zur nächst höheren Verdrahtungsebene realisiert, eine Schlüsselrolle zur Erfüllung der wachsenden Anforderungen an die funktionalen technischen Kennwerte zukommt. Insbesondere bestehen diese wachsenden Anforderungen für die Datenübertragungsraten und für die Zuverlässigkeitskennwerte des Gesamtverbundes der elektronischen Baugruppe.Of the Prior art shows that the peripheral structure of the applied Semiconductor memory circuits, e.g. their electrical contacting structure to the next higher Wiring level realized a key role to fulfill the growing Requirements for the functional technical characteristics. In particular, these growing demands are for data transfer rates and for the reliability characteristics of the overall assembly of the electronic assembly.
Diese wachsenden Anforderungen müssen erfüllt werden, um mit der Entwicklung der elektronischen Bauteile, wie z. B. der CPU und der Logik-Bausteine, die die Entwicklung maßgeblich bestimmen, Schritt zu halten. So ist für die CPU die Taktrate und für die Logik-Bausteine die Schaltzeit bzw. die Signal-Anstiegszeit jeweilige Messstabsgröße für diese Entwicklung.These growing demands must be met with the development of electronic components, such. B. the CPU and the logic building blocks that govern the development determine to keep up. So for the CPU is the clock rate and for the logic devices the switching time or the signal rise time respective dipstick size for this development.
Aus elektro-physikalischen Gründen ist bei einer Taktrate ab 1 GHz und höher, sowie einer Schaltzeit von 3 Nanosekunden und schneller, der Signal-Integrität besondere Aufmerksamkeit zu widmen.Out electro-physical reasons is at a clock rate from 1 GHz and higher, as well as a switching time of 3 nanoseconds and faster, the signal integrity special To pay attention to.
Beim Einsatz höchstintegrierter Schaltungen mit immer kom pakteren Gehäusen, die stets kleinere Anschlussraster und immer größere Anschlusszahlen aufweisen, muss auch der erforderliche periphere Aufbau die Anforderungen erfüllen. So führt diese aufgezeigte Entwicklungstendenz bei den konventionellen Umverdrahtungsstrukturen auf Wafer-Ebene bzw. bei den bisherigen Leiterbahnstrukturen auf Interposern und Leiterplatten zu dichter belegten Signallagen mit geringsten Leiterbahnbreiten.At the Use of highly integrated Circuits with ever more com pact housings, the ever smaller connection grid and ever larger numbers of connections Also, the required peripheral structure must meet the requirements fulfill. So leads This development trend in the conventional rewiring structures on the wafer level or in the previous interconnect structures Interposers and printed circuit boards to denser signal layers with lowest conductor track widths.
Um die vorstehend genannte Signal-Integrität zu gewährleisten, werden beim Stand der Technik die Leiterbahnstrukturen impedanzdefiniert ausgeführt.Around To ensure the above-mentioned signal integrity, are in the state technology, the track structures executed impedance defined.
Damit verbundenen sind bei der Gestaltung impedanzrichtiger Leitungen verbesserte Ätztoleranzen zu realisieren.In order to connected are in the design of impedance correct lines improved etching tolerances to realize.
Zur Reduzierung von "Crosstalks" zwischen Leitbahnen, welche durch Übersprechen (Crosstalk) benachbarter Leitbahnen infolge deren kapazitiver Kopplung auftreten, und zur Reduzierung von Signalreflexionen auf den Leiterbahnstrukturen werden dazu vorzugsweise impedanzrichtige Mikrokoaxialleitungen angewandt.to Reduction of "crosstalks" between interconnects, which by crosstalk (Crosstalk) of adjacent interconnects due to their capacitive coupling occur and to reduce signal reflections on the interconnect structures For this purpose, preferably impedance-correct micro-coaxial cables applied.
Ein beim Stand der Technik bekanntes weiteres Mittel zur Erfüllung der wachsenden Anforderungen ist eine optimale Entflechtung der Leiterbahnstrukturen durch Mehrfach-Mikrovia-Bohrlagen. Zum in Entflechten werden derzeit 2 Mikrometer-Via-Bohrlagen in Kombination mit konventioneller Bohrtechnik eingesetzt. Die Bohrdurchmesser der Mikro-VIAs lassen sich nicht mehr durch klassisches Bohren erzeugen. Es müssen alternative Methoden, wie z. B. Laser-Bohren, Plasma- oder Foto-Strukturierung eingesetzt werden.One known in the prior art further means for fulfilling the Growing demands are optimal unbundling of the conductor track structures through multiple microvia drilling positions. To the At present, 2 micron via drilling positions are being used in combination with conventional drilling technology used. The drilling diameter of the micro-VIAs can not be produce more by classical drilling. There have to be alternative methods, like z. As laser drilling, plasma or photo structuring used become.
Mit solchen Mikro-VIA Technologien werden z. B. mit mehrlagigen Umverdrahtungsebenen (3D-Redistribution Layer) direkte Verdrahtungswege orthogonal zu den Verdrahtungsebenen (in Z-Richtung) geführt.With such micro-VIA technologies are z. B. with multi-layer redistribution layers (3D Redistribution Layer) direct wiring paths orthogonal to the wiring levels (in the Z direction).
Bei der Realisierung von impedanzdefinierten Leiterbahnstrukturen wird bei vorhandenem definierten Dielektrikum vorzugsweise die Impedanz der Leiterbahnstrukturen durch die Geometrie der Signalleiter, die Abstände zwischen diesen Signalleitern und die Abstände der Signalleiter zum Bezugspotenzial eingestellt.at the realization of impedance-defined interconnect structures if there is a defined dielectric, preferably the impedance the conductor track structures through the geometry of the signal conductors, the distances between these signal conductors and the distances of the signal conductors to the reference potential set.
Die impedanzdefinierten Leiterbahnstrukturen sind nach dem Stand der Technik klassifiziert in: Single Ended, Differentiell, Coplanar, Differentiell-Coplanar.The impedance-defined interconnect structures are according to the state of Technique classified in: Single Ended, Differential, Coplanar, Differentially-coplanar.
„Single Ended" bedeutet dabei, dass eine Leiterbahn mit Referenz zu einer oder zu zwei Powerplanes steht. Unter „Differentiell" ist zu verstehen, dass zwei gekoppelte Leiterbahnen in Referenz zu einer oder zu zwei Powerplanes steht. Bei einer „coplanaren Leiterbahnstruktur" steht eine Leiterbahn mit Referenz zu einer oder zu zwei Powerplanes und wird links und rechts von Potential führenden Leiterbahnen oder Masseflächen flankiert, wohingegen bei einer „differentiellcoplanaren" Leiterbahn zwei gekoppelte Leiterbahnen mit Referenz zu einer oder zu zwei Powerplanes stehen und rechts und links von Potential führenden Leiterbahnen oder Messeflächen flankiert werden."Single Ended "means doing a lead with reference to one or two powerplanes stands. By "differential" is meant that two coupled tracks in reference to one or two powerplanes stands. In a coplanar Track structure "stands a trace with reference to one or two powerplanes and becomes leading left and right of potential Tracks or ground planes flanked, whereas in a "differential coplanar" track two Coupled tracks with reference to one or two powerplanes are flanked and flanked right and left by potential leading conductors or exhibition areas become.
Für jede dieser vier Impedanzklassen sind je zwei Impedanztypen Stripline – die impedanzdefinierte Leiterbahn liegt zwischen zwei Potential führenden Masseflächen – und Mikrostrip – die impedanzdefinierte Leiterbahn liegt über einer Potential führenden Massefläche – zugeordnet.For each of these four impedance classes are each two impedance types Stripline - the impedance-defined Trace lies between two potential-carrying ground planes - and microstrip - the impedance-defined ones Track is over a potential leader Ground plane - assigned.
Als verbleibender Nachteil ist ersichtlich, dass für die Führung der impedanzdefinierten Leiterbahnstrukturen über mehrere Verdrahtungsebenen hinweg keine Lösungen bekannt sind.When remaining disadvantage is evident that for the management of impedance defined Track structures over several wiring levels no solutions are known.
Somit besteht die erfindungsgemäße Aufgabenstellung darin, eine HF-Zwischenverbindung für Mehrfach-Verdrahtungsebenen mit impedanzdefinierten Leiterbahnstrukturen zu schaffen, die einfach und mit reproduzierbaren und vorgebbaren Parametern realisiert werden kann.Consequently exists the task of the invention therein, an RF interconnect for multiple wiring levels To create impedance-defined trace structures that are simple and be realized with reproducible and specifiable parameters can.
Die Lösung der erfindungsgemäßen Aufgabenstellung wird dadurch erreicht, dass HF-Zwischenverbindung durch eine elektrisch leitfähige Füllung oder Beschichtung der Wandung eines VIA repräsentiert wird. Hierbei sind die Verdrahtungsebenen zumindest mittelbar jeweils auf einer ersten und einer zweiten Isolationslage angeordnet, die sich auf einer ersten und einer zweiten elektrisch leitfähigen Schicht befinden, die sich beidseitig auf einem Substrat befinden. Weiterhin ist das VIA mit einer ersten Hülse einer leitfähigen Schicht versehen und koaxial um diese ist eine zweiten Hülse einer Isolationsschicht angeordnet, wobei diese zweiten Hülse die HF-Zwischenverbindung umschließt.The solution the task of the invention is achieved in that HF interconnection by an electric conductive filling or coating the wall of a VIA is represented. Here are the wiring levels at least indirectly each on a first and a second insulation layer disposed on a first and a second electrically conductive layer are the are on both sides of a substrate. Furthermore, this is the VIA with a first sleeve a conductive Layer provided and coaxial about this is a second sleeve one Insulation layer disposed, said second sleeve, the RF interconnect encloses.
In einer Ausgestaltung der Erfindung ist vorgesehen, dass der Gesamtaufbau von der HF-Zwischenverbindung, von der ersten Hülse, der leitfähigen Schicht und von der zweiten Hülse der Isolationsschicht solche geometrischen Abmaße aufweist, mit der die Impedanzrichtigkeit/Impedanzdefinition gewährleistet wird.In An embodiment of the invention provides that the overall structure from the RF interconnect, from the first sleeve, the conductive layer and from the second sleeve the insulating layer has such geometrical dimensions, with which ensures the impedance accuracy / impedance definition becomes.
In einer weiteren Variante wird aufgezeigt, dass sich zusätzlich auf den Gesamtaufbau von der HF-Zwischenverbindung, von der ersten Hülse der leitfähigen Schicht und von der zweiter Hülse der Isolationsschicht aufbauend auf die zweite Hülse der Isolationsschicht eine/oder weitere Hülse(n) der leitfähigen Schicht und anschließend eine/oder weitere Hülse(n) der Isolationsschicht sich alternierend bezüglich der Leitfähigkeit der jeweiligen Hülse fortsetzt.In another variant is shown that in addition to the overall structure of the RF interconnect, from the first sleeve of the conductive layer and from the second sleeve the insulating layer based on the second sleeve of the insulating layer a / or further sleeve (s) the conductive one Layer and then one or more sheath (s) the insulation layer alternating with respect to the conductivity the respective sleeve continues.
Eine weitere Variante der Erfindung wird derart realisiert, dass die elektrisch leitfähigen Schichten in dem VIA durch eine Metallisierung aufgebaut sind und eine abschließende Oberflächenveredlung aufweisen.A Another variant of the invention is realized such that the electrically conductive Layers in the VIA are constructed by a metallization and a final one Surface finishing exhibit.
In Fortführung der Erfindung ist weiterhin vorgesehen, dass der Gesamtaufbau in dem VIA auf konventionellem Verdrahtungsträger oder Wafer-Ebene angeordnet ist.In continuation the invention is further provided that the overall structure in the VIA on conventional wiring substrate or wafer level arranged is.
In einer zusätzlichen Ausgestaltung der Erfindung ist vorgesehen, dass der Gesamtaufbau in dem VIA mit
- – Füllung mit Polymerpasten (Dispensen von Silberpaste) oder
- – Palladiumbekeimung mit anschließender Aktivierung (Direktmetallisierung) oder
- – Bekeimung mit Graphit (Blackhole Technologie) oder
- – Belegung mit leitfähigem Polymerfilm aufgebaut ist.
- - filling with polymer pastes (dispensing of silver paste) or
- - Palladiumbekeimimung with subsequent activation (direct metallization) or
- - Germination with graphite (blackhole technology) or
- - Occupancy is constructed with conductive polymer film.
Die Erfindung wird nachfolgend anhand eines Ausführungsbeispiels näher erläutert. Dabei zeigt:The Invention will be explained in more detail with reference to an embodiment. Showing:
In
Auf
diesen Schichten aufbauend sind jeweils die erste und zweite Isolationslage
Die
HF-Zwischenverbindung
Der
Gesamtaufbau der HF-Zwischenverbindung
In
Anschließend setzt
eine/oder weitere Hülse(n)
- 11
- HF-ZwischenverbindungRF interconnect
- 22
- erste leitfähige Schichtfirst conductive layer
- 33
- zweite leitfähige Schichtsecond conductive layer
- 44
- erste Isolationslagefirst insulation layer
- 55
- zweite Isolationslagesecond insulation layer
- 66
- ersten Hülse der leitfähigen Schichtfirst Sleeve of the conductive layer
- 77
- ersten Hülse der Isolationsschichtfirst Sleeve of the insulation layer
- 88th
- erste Verdrahtungsebenefirst wiring level
- 99
- zweite Verdrahtungsebenesecond wiring level
- 1010
- Substratsubstratum
- 1111
- VIAVIA
- 1212
- weitere Hülse(n) der leitfähigen SchichtFurther Sleeve (s) the conductive one layer
- 1313
- weitere Hülse(n) der IsolationsschichtFurther Sleeve (s) the insulation layer
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200410038970 DE102004038970B4 (en) | 2004-08-10 | 2004-08-10 | RF interconnection for multiple wiring levels with impedance-defined trace structures |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200410038970 DE102004038970B4 (en) | 2004-08-10 | 2004-08-10 | RF interconnection for multiple wiring levels with impedance-defined trace structures |
Publications (2)
Publication Number | Publication Date |
---|---|
DE102004038970A1 true DE102004038970A1 (en) | 2006-02-23 |
DE102004038970B4 DE102004038970B4 (en) | 2008-08-28 |
Family
ID=35721280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE200410038970 Expired - Fee Related DE102004038970B4 (en) | 2004-08-10 | 2004-08-10 | RF interconnection for multiple wiring levels with impedance-defined trace structures |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102004038970B4 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3838486A1 (en) * | 1988-11-12 | 1990-05-17 | Standard Elektrik Lorenz Ag | Circuit base for radio-frequency lines |
US6605551B2 (en) * | 2000-12-08 | 2003-08-12 | Intel Corporation | Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance |
US6710259B2 (en) * | 1993-05-17 | 2004-03-23 | Electrochemicals, Inc. | Printed wiring boards and methods for making them |
-
2004
- 2004-08-10 DE DE200410038970 patent/DE102004038970B4/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3838486A1 (en) * | 1988-11-12 | 1990-05-17 | Standard Elektrik Lorenz Ag | Circuit base for radio-frequency lines |
US6710259B2 (en) * | 1993-05-17 | 2004-03-23 | Electrochemicals, Inc. | Printed wiring boards and methods for making them |
US6605551B2 (en) * | 2000-12-08 | 2003-08-12 | Intel Corporation | Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance |
Non-Patent Citations (2)
Title |
---|
WAN, CHI-CHAO: A Review of the Technology Deve- lopement of Direct Metallization. In: Proc. Natl. Sci. Counc. ROC (A), vol. 23, No. 3, 1999, pp. 365 -8 |
WAN, CHI-CHAO: A Review of the Technology Deve- lopement of Direct Metallization. In: Proc. Natl. Sci. Counc. ROC (A), vol. 23, No. 3, 1999, pp. 365-8 * |
Also Published As
Publication number | Publication date |
---|---|
DE102004038970B4 (en) | 2008-08-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7767913B2 (en) | Electronic devices including conductive vias having two or more conductive elements for providing electrical communication between traces in different planes in a substrate, and accompanying methods | |
DE60314868T2 (en) | IMPROVED STRUCTURE OF STACKED CONTACT HOLES IN MULTILAYER ELECTRONIC CONSTRUCTION ELEMENTS | |
US6891272B1 (en) | Multi-path via interconnection structures and methods for manufacturing the same | |
DE19781846B4 (en) | Circuit housing, in particular flip-chip or C4 housing with power supply and ground planes | |
DE112009000351B4 (en) | Microelectronic package containing silicon patches for high density interconnects, and methods of making same | |
US5272600A (en) | Electrical interconnect device with interwoven power and ground lines and capacitive vias | |
DE10197124B4 (en) | Multi-stage electrical capacitor and suitable manufacturing process | |
CN1842248B (en) | Off-grid decoupling device and method of ball grid array (BGA) | |
US5508938A (en) | Special interconnect layer employing offset trace layout for advanced multi-chip module packages | |
US20060185890A1 (en) | Air void via tuning | |
DE102005036834A1 (en) | Circuit board and method of fabricating a circuit board | |
US20070184687A1 (en) | Circuit board provided with digging depth detection structure and transmission device with the same mounted | |
US6894228B2 (en) | High performance dense wire for printed circuit board | |
DE10018358A1 (en) | Semiconductor component manufacturing method, involves separating insulating layer on semiconductor substrate and producing connection strip conductor connected with strip conductor layer of semiconductor elements in layer. | |
DE10106161A1 (en) | Reliable multilayer planar connective structure on integrated circuit chip, combines materials of differing dielectric constant and elasticity | |
DE10317101A1 (en) | On-chip noise reduction system and a method of manufacturing the same | |
DE102016102522B4 (en) | Connection structure and method for its production | |
DE112013003806T5 (en) | Multilayer transmission lines | |
DE102005062967A1 (en) | High-frequency conductor for packaging of integrated circuits | |
DE112005000438B4 (en) | An interconnection structure and method for connecting buried signal lines to electrical devices | |
CN113811068A (en) | Embedded microstrip line with slot for high-speed signal routing | |
DE102004038970B4 (en) | RF interconnection for multiple wiring levels with impedance-defined trace structures | |
US7196906B1 (en) | Circuit board having segments with different signal speed characteristics | |
DE102004037826B4 (en) | Semiconductor device with interconnected semiconductor devices | |
CN113678574B (en) | Packaging device for common mode rejection and printed circuit board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8127 | New person/name/address of the applicant |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE |
|
8364 | No opposition during term of opposition | ||
R081 | Change of applicant/patentee |
Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE |
|
R081 | Change of applicant/patentee |
Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |