DE102004047313B3 - Semiconductor arrangement with a tunnel contact and method for its production - Google Patents
Semiconductor arrangement with a tunnel contact and method for its production Download PDFInfo
- Publication number
- DE102004047313B3 DE102004047313B3 DE200410047313 DE102004047313A DE102004047313B3 DE 102004047313 B3 DE102004047313 B3 DE 102004047313B3 DE 200410047313 DE200410047313 DE 200410047313 DE 102004047313 A DE102004047313 A DE 102004047313A DE 102004047313 B3 DE102004047313 B3 DE 102004047313B3
- Authority
- DE
- Germany
- Prior art keywords
- wafer
- substrate
- manufacturing
- implantation
- doping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000002513 implantation Methods 0.000 claims abstract description 17
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000000407 epitaxy Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 3
- 238000000576 coating method Methods 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000010276 construction Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 230000002146 bilateral effect Effects 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 238000002360 preparation method Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 7
- 230000005641 tunneling Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000035876 healing Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Abstract
Bei einer Halbleiteranordnung aus Siliciumcarbid oder dergleichen mit einem Wafer als Substrat ist ein hochleitfähiger Tunnelkontakt vorhanden. Dazu wird ein n-Substrat verwendet, wobei eine Umkehrung der Dotierung beim weiteren epitaktischen Wachstum erfolgt. Bei der Herstellung einer solchen Anordnung durch epitaktische Beschichtung eines n-dotierten Wafers als Substrat mit einem p-dotierten Halbleitermaterial (p-Epitaxie) wird zur Herstellung des Tunnelkontaktes vor der p-Epitaxie eine n-Implantation in den Wafer vorgenommen. Es können so insbesondere IGBT-artige Bauelemente hergestellt werden.In a semiconductor device of silicon carbide or the like having a wafer as a substrate, a highly conductive tunnel junction is present. For this purpose, an n-substrate is used, wherein a reversal of the doping takes place during further epitaxial growth. In the production of such an arrangement by epitaxially coating an n-doped wafer as a substrate with a p-doped semiconductor material (p-epitaxy), an n-implantation into the wafer is carried out to establish the tunnel contact before the p-epitaxy. In particular, IGBT-type components can be produced in this way.
Description
Die Erfindung bezieht sich auf eine Halbleiteranordnung aus Siliciumcarbid oder ähnlichem Material mit großem Bandabstand, gemäß dem Oberbegriff des Patentanspruches 1. Daneben bezieht sich die Erfindung auch auf ein zugehöriges Verfahren zur Herstellung einer derartigen Halbleiteranordnung, insbesondere zur Verwendung als spezifische Schaltelemente.The This invention relates to a silicon carbide semiconductor device or similar Material with big Band gap, according to the preamble of claim 1. In addition, the invention also relates to an associated one Method for producing such a semiconductor device, in particular for use as specific switching elements.
Halbleiteranordnungen bestehen üblicherweise aus einem Wafer als Substrat und darauf befindlichen halbleitenden Schichten vorgegebener Dotierung. Durch geeigneten Aufbau und mit zugehörigen Elektroden kann aus der Anordnung ein Halbleiterschaltelement gebildet werden.Semiconductor devices usually exist from a wafer as a substrate and semiconducting thereon Layers of given doping. By suitable construction and with associated Electrodes can be formed from the arrangement of a semiconductor switching element become.
Für eine Reihe von insbesondere bipolaren Schaltern, die auf dem Halbleitermaterial Siliciumcarbid (SiC) aufbauen, benötigt man eine p-leitende Rückseite des SiC-Materials. Da p-leitende Substrate (Wafer) – bedingt durch die Kristallzuchttechnik – eine schlechte spezifische Leitfähigkeit in der Größenordnung von einigen Ωcm haben, sind solche p-Wafer zum Aufbau eines Schaltelementes nicht verwendbar.For a series in particular bipolar switches acting on the semiconductor material Silicon carbide (SiC) build, one needs a p-conductive back of the SiC material. As p-type substrates (wafers) - conditional through the crystal growing technique - one poor specific conductivity in the order of magnitude of a few Ωcm have such p-wafers are not usable for the construction of a switching element.
Bekanntermaßen kann zwar der reale Widerstand des Substrates durch Dünnen des p-Wafers proportional mit der Dicke verringert werden. Ein Einsatz derartiger Substrate in der Leistungselektronik wird allerdings durch die Defektdichte der p-Wafer, die deutlich über der von derzeit verfügbaren n-leitenden Substraten liegt, verhindert. Dies gilt bei der vorhandenen Defektdichte der p-Wafer wegen der dadurch bedingten statischen Verluste aus technischen, sowie wegen der geringen Ausbeute auch aus wirtschaftlichen Gründen.As is known, can Although the real resistance of the substrate by thinning the p-wafer proportional be reduced with the thickness. A use of such substrates in power electronics, however, is due to the defect density the p-wafers that are well over that of currently available n-type substrates is prevented. This applies to the existing one Defect density of the p-wafer due to the resulting static Losses for technical, as well as for the low yield also because of economical reasons.
Letzteres Problem könnte nur durch einen Qualitätssprung in der Entwicklung zukünftiger p-Substrate gelöst werden. Aller dings sprechen sowohl Entwicklungsprobleme wie auch geschätzter Marktbedarf gegen einen raschen Fortschritt aufgrund einer derartigen Entwicklung. Im Übrigen werden bei Anwendungen solcher Substrate zusätzlich meist hohe Ströme mit entsprechend großen Chipflächen gefordert.The latter Problem could be only by a jump in quality in the development of future p-substrates solved become. However, both development problems and also speak estimated market needs against rapid progress due to such a development. Furthermore In applications of such substrates in addition usually high currents with accordingly huge chip areas required.
Aus
der WO 2004/075253 A2, der
Daneben
zeigt die
Weiterhin
beinhaltet die
Ausgehend von vorstehend abgehandeltem Stand der Technik ist es Aufgabe der Erfindung, eine alternative Realisierung von Halbleiteranordnungen für obigen Zweck anzugeben.outgoing From the above-discussed prior art, it is the task of Invention, an alternative implementation of semiconductor devices for the above Purpose to specify.
Die Aufgabe ist erfindungsgemäß durch die Merkmale des Patentanspruches 1 gelöst. Ein Verfahren zur Herstellung einer solchen Halbleiteranordnung ist Gegenstand des Patentanspruches 9. Weiterbildungen der Anordnung und des zugehörigen Herstellungsverfahrens, insbesondere zur Ausbildung von Schaltelementen, sind in den Unteransprüchen angegeben.The Task is inventively by the features of claim 1 solved. A method of manufacture Such a semiconductor device is the subject of the claim 9. further developments of the arrangement and the associated manufacturing method, in particular for the formation of switching elements, are specified in the subclaims.
Mit der Erfindung wird eine alternative Möglichkeit für Halbleiteranordnungen, insbesondere zwecks Einsatz als bipolare Schalter, unter Verwendung von n-Wafern als Ausgangssubstrat angegeben. Dabei werden auf dem SiC-Halbleitermaterial Tunnelkontakte realisiert. Bei Anwendung des erfindungsgemäßen Tunnelkontaktes für Bauelemente hat dies jedoch keine Umkehrung der Dotierungen und damit auch keine Umkehrung der gewohnten Spannungen zur Folge.With The invention provides an alternative possibility for semiconductor devices, in particular for the purpose Used as a bipolar switch, using n-wafers as Starting substrate indicated. In this case, tunnel contacts are formed on the SiC semiconductor material realized. When using the tunnel junction according to the invention for components has However, this does not reverse the doping and thus none Reversal of the usual tensions result.
Weitere Einzelheiten und Vorteile der Erfindung ergeben sich aus der nachfolgenden Figurenbeschreibung von Ausführungsbeispielen anhand der Zeichnung in Verbindung mit den Patentansprüchen.Further Details and advantages of the invention will become apparent from the following Description of the figures of exemplary embodiments with reference to the drawing in conjunction with the claims.
Es zeigenShow it
Es
soll eine Halbleiteranordnung auf der Basis von Siliciumcarbid (SiC)
mit wenigstens einem Tunnelkontakt versehen werden. Dabei bedient
man sich der Technologie der Ionenimplantation, was zunächst anhand
der
In
In
einer Alternative gemäß
Statt
der N-Ionen im ersten Teilschritt kommen ggf. auch Phosphor(P)-Ionen
zur Implantation in Frage, wobei im zweiten Teilschritt entsprechend
obigen Ausführungen
gearbeitet wird. In beiden Fällen lässt sich
somit ein SiC-Tunnelkontakt auf dem n-Wafer realisieren mit nahezu
abruptem, symmetrischem pn-Übergang,
dessen Verhalten anhand von
In
Beim
angegebenen Beispiel hat das n-Substrat eine Dotierungskonzentration
von etwa 5·e18cm–3, die p-Epi-50 nm-Schicht
eine Dotierungskonzentration von etwa 3·e16cm–3 und
die Al 25 kV-Ionenimplantation
eine Dosis von 5·e14cm–2.In
In the example given, the n-type substrate has a doping concentration of about 5 · e 18 cm -3 , the p-epi 50 nm layer has a doping concentration of about 3 · e 16 cm -3, and the Al 25 kV ion implantation has a dose of 5 · e 14 cm -2 .
In
Durch
den scharfen Übergang
der Zustandsdichte gemäß
In
Die
Schicht
Im
aktiven Gebiet des Bauelementes ist im Zentrum eine p+-Kontaktschicht
aber
dieser gestuften Anordnung ist eine Isolationsschicht
Wesentlich
ist, dass auf dem Wafer durch die spezifische Herstellungsweise
ein schmales Tunnelgebiet
In
Durch
die Epitaxie der Epi-Schichten
Bei
den in den
Letzteres
Problem wird bei obigen Beispielen durch die Herstellung eines ohm'schen Kontaktes
Durch Einführung einer ebenfalls flachen n-Implantation mit maximaler Dosis in den n-Wafer 30 vor der p-Epitaxie kann die Bandverbiegung entsprechend den Dotiergradienten weiter vergrößert werden. Die bei der Implantation eingebrachte hohe Defektdichte verbessert durch sog. „Trap-assisted Tunneling" die Kontaktleitfähigkeit weiter mittels einer drastischen Erhöhung der Rekombinationsgeschwindigkeit von Elektronen und Löchern. Dabei wird Vorteilhafterweise ausgenutzt, dass in Siliciumcarbid (SiC) abrupte pn-Obergänge derart innerhalb eines Bereiches von 5 bis 20 nm möglich sind, da praktisch keine Diffusion während der nachfolgenden Prozessschritte erfolgt. Ein üblicher Ausheilschritt aktiviert elektrisch die implantierten Dotierstoffe im Kristallgitter, möglichst mit differenzierter Wirkung auf die Defekt-Niveaus.By introduction a likewise flat n-implantation with maximum dose in the n-wafer 30 prior to p-epitaxy, the band bending corresponding the Dotiergradienten be further increased. The at implantation introduced high defect density improved by so-called "trap-assisted tunneling" the contact conductivity further by means of a drastic increase in the recombination rate of electrons and holes. It is advantageously exploited that in silicon carbide (SiC) abrupt pn-junctions are possible within a range of 5 to 20 nm, there is virtually no diffusion during the subsequent process steps takes place. A usual healing step activated electrically the implanted dopants in the crystal lattice, if possible with a differentiated effect on the defect levels.
Mit dem beschriebenen Verfahren ist es also möglich, auf einem n++-Substrat einen p-Emitter zu erzeugen. Damit können z.B. mit bekannten Prozessen, insbesondere durch Verwendung einer dicken n-Epi-Schicht mit hoher Trägerlebensdauer, verbesserte bipolare und hochsperrende Schalter mit der gewohnten Polarität aufgebaut werden. Die Verwendung des technisch i. Allg. mangelhaften SiC-p-Substrates wird dabei umgangen.With the method described, it is thus possible to generate a p-emitter on an n ++ substrate. Thus, for example, with known processes, in particular by using a thick n-epi layer with high carrier lifetime, improved bipolar and high-blocking switch can be constructed with the usual polarity. The use of the technical i. Gen. deficient SiC-p substrate is thereby bypassed.
Vorteilhafterweise
ist es entsprechend
Claims (18)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200410047313 DE102004047313B3 (en) | 2004-09-29 | 2004-09-29 | Semiconductor arrangement with a tunnel contact and method for its production |
CNA2005800329766A CN101032029A (en) | 2004-09-29 | 2005-09-19 | Semiconductor assembly comprising a tunnel contact and method for producing said assembly |
PCT/EP2005/054655 WO2006034970A1 (en) | 2004-09-29 | 2005-09-19 | Semiconductor assembly comprising a tunnel contact and method for producing said assembly |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200410047313 DE102004047313B3 (en) | 2004-09-29 | 2004-09-29 | Semiconductor arrangement with a tunnel contact and method for its production |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102004047313B3 true DE102004047313B3 (en) | 2006-03-30 |
Family
ID=35406197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE200410047313 Expired - Fee Related DE102004047313B3 (en) | 2004-09-29 | 2004-09-29 | Semiconductor arrangement with a tunnel contact and method for its production |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN101032029A (en) |
DE (1) | DE102004047313B3 (en) |
WO (1) | WO2006034970A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4786621B2 (en) * | 2007-09-20 | 2011-10-05 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
CN103151262A (en) * | 2011-12-07 | 2013-06-12 | 无锡华润华晶微电子有限公司 | Planar insulated gate bipolar transistor and preparation method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3254278A (en) * | 1960-11-14 | 1966-05-31 | Hoffman Electronics Corp | Tunnel diode device |
US5338944A (en) * | 1993-09-22 | 1994-08-16 | Cree Research, Inc. | Blue light-emitting diode with degenerate junction structure |
DE19954343A1 (en) * | 1999-11-11 | 2001-05-23 | Infineon Technologies Ag | Surface emitting laser diode enables higher light yield to be achieved with less heating |
US20030015042A1 (en) * | 2001-07-20 | 2003-01-23 | Wilhelm Florin | Magnetoinductive flowmeter |
EP0864180B1 (en) * | 1995-11-29 | 2004-07-21 | QinetiQ Limited | Low resistance contact semiconductor diode |
WO2004075253A2 (en) * | 2003-02-14 | 2004-09-02 | Cree, Inc. | Inverted light emitting diode on conductive substrate |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5087576A (en) * | 1987-10-26 | 1992-02-11 | North Carolina State University | Implantation and electrical activation of dopants into monocrystalline silicon carbide |
US6011279A (en) * | 1997-04-30 | 2000-01-04 | Cree Research, Inc. | Silicon carbide field controlled bipolar switch |
SE525574C2 (en) * | 2002-08-30 | 2005-03-15 | Okmetic Oyj | Low-doped silicon carbide substrate and its use in high-voltage components |
-
2004
- 2004-09-29 DE DE200410047313 patent/DE102004047313B3/en not_active Expired - Fee Related
-
2005
- 2005-09-19 CN CNA2005800329766A patent/CN101032029A/en active Pending
- 2005-09-19 WO PCT/EP2005/054655 patent/WO2006034970A1/en active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3254278A (en) * | 1960-11-14 | 1966-05-31 | Hoffman Electronics Corp | Tunnel diode device |
US5338944A (en) * | 1993-09-22 | 1994-08-16 | Cree Research, Inc. | Blue light-emitting diode with degenerate junction structure |
EP0864180B1 (en) * | 1995-11-29 | 2004-07-21 | QinetiQ Limited | Low resistance contact semiconductor diode |
DE19954343A1 (en) * | 1999-11-11 | 2001-05-23 | Infineon Technologies Ag | Surface emitting laser diode enables higher light yield to be achieved with less heating |
US20030015042A1 (en) * | 2001-07-20 | 2003-01-23 | Wilhelm Florin | Magnetoinductive flowmeter |
WO2004075253A2 (en) * | 2003-02-14 | 2004-09-02 | Cree, Inc. | Inverted light emitting diode on conductive substrate |
Non-Patent Citations (3)
Title |
---|
Peters,D., Schröner,R., Friedrichs,P., Völkl,J., Mitlehner,H., Stephani,D.: An 1800 V Triple Implated Vertical 6H-SiC MOSFET. In: IEEE Trans. on Electron Devices, ISSN 0018-9383, 1999, Vol. 46, No. 3, S. 542-545 * |
Sugg,A.R., Chen,E.I., Richard,T.A., Maranowski, S.A., Holonyak,N.jr.: n-p-(+-n+)-n AjyGa1- y-As-GaAs-InxGa1- xAs quantum-well laser with p+-n+ GaAs-InGaAs tunnel contact on n-GaAs. In: Applied Physics Letters, ISSN 0003- 6951, 1993, Vol. 62, No. 20, S. 2510-2512 |
Sugg,A.R., Chen,E.I., Richard,T.A., Maranowski, S.A., Holonyak,N.jr.: n-p-(·+·-n·+·)-n Aj¶y¶Ga¶1¶-¶y¶-As-GaAs-In¶x¶Ga¶1¶-¶xAs quantum-well laser with p·+·-n·+· GaAs-InGaAs tunnel contact on n-GaAs. In: Applied Physics Letters, ISSN 0003- 6951, 1993, Vol. 62, No. 20, S. 2510-2512 * |
Also Published As
Publication number | Publication date |
---|---|
CN101032029A (en) | 2007-09-05 |
WO2006034970A1 (en) | 2006-04-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102009038731B4 (en) | Semiconductor component with charge carrier compensation structure and method for manufacturing a semiconductor component | |
DE102018103973B4 (en) | SILICON CARBIDE SEMICONDUCTOR COMPONENT | |
DE3122768C2 (en) | ||
DE10207522B4 (en) | Semiconductor component and method for its production | |
DE112010005626B4 (en) | Semiconductor device | |
DE102006047244B4 (en) | Semiconductor device with a monocrystalline semiconductor body and method for producing the same | |
DE112016003510T5 (en) | SEMICONDUCTOR PROTECTION AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE | |
DE102016112512A1 (en) | Semiconductor device having an oxygen diffusion barrier layer and manufacturing method | |
DE102015100340A1 (en) | BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR | |
EP1812970A1 (en) | Semiconductor device and methods for the production thereof | |
DE112019003790T5 (en) | SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE | |
DE102011054825A1 (en) | A semiconductor device and a method of manufacturing a semiconductor device | |
DE102014108279A1 (en) | SEMICONDUCTOR DEVICE WITH RECOMBINATION CENTERS AND MANUFACTURING METHOD | |
DE102012021534B4 (en) | SCHOTTKY SEALING LAYER SEMICONDUCTOR ELEMENT FROM THE GRAY TYPE AND MANUFACTURING METHOD THEREFOR | |
DE102017131354A1 (en) | A wide bandgap semiconductor device and a method of forming a wide bandgap semiconductor device | |
DE112016006374B4 (en) | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME | |
DE102018216855A1 (en) | A silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device | |
DE102012023512A1 (en) | Silicon carbide-barrier layer-schottky diode, has trenches provided in region of silicon carbide layer with depth and in distance so that electrical field intensity at schottky-transition-boundary surface is equal to specific value or small | |
DE102009031314B4 (en) | Semiconductor device made of silicon with partially band gap and method for producing the same | |
DE102005039564A1 (en) | Semiconductor component and method for its production | |
EP1307923A1 (en) | High-voltage diode and method for the production thereof | |
DE102016108125B4 (en) | Semiconductor device and manufacture thereof | |
DE102016104757B4 (en) | Semiconductor transistor and method of forming the semiconductor transistor | |
DE102018123439B4 (en) | Power semiconductor transistor, method for processing a power semiconductor transistor and method for producing a power semiconductor transistor | |
DE102004047313B3 (en) | Semiconductor arrangement with a tunnel contact and method for its production |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8100 | Publication of the examined application without publication of unexamined application | ||
8364 | No opposition during term of opposition | ||
R081 | Change of applicant/patentee |
Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: SICED ELECTRONICS DEVELOPMENT GMBH & CO. KG, 91058 ERLANGEN, DE Effective date: 20110419 |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |