DE102005035699B4 - Semiconductor power device with charge compensation structure and method of making the same - Google Patents

Abstract

Semiconductor power device with charge compensation structure (2), wherein the semiconductor power device (1) has a field effect device with a vertical weak to medium doped drift path (4) between a first electrode (5) on the top (20) of the semiconductor power device (1) and a second electrode (6 ) on the rear side (26) of the semiconductor power component (1), the drift path (4) having vertically aligned drift zones (9) surrounded by a vertically aligned trench structure (8) as a charge compensation structure (2), and wherein the trench structure ( 8) comprises an anisotropically conductive material (10) having in layers (11, 12) orthogonal to the trench depth (t) alternately high and low conductivities and in the trench depth (t) a low conductivity, wherein the anisotropically conductive material is selected from the group consisting of:
a) graphite whose planes (11, 12) are arranged orthogonal to the trench depth (t) with highly conductive hexagonal structured crystal lattice planes (14) alternating with non-conducting Van of the Waal bonding planes (18) disposed therebetween;
b) filled plastic mixed with agglomerates ...

Description

In conventional MOSFETs with drift path, the maximum donor concentration [N _D ] in an n ^{- region} as the drift path and thus also the electrical conductivity of the drift path is determined by the required blocking capability or vice versa. In the avalanche breakthrough, approximately 1.5 × 10 ¹² cm ^-2 donors are then ionized, which find their counter-charge in the acceptor charge of the p-type region of the conventional MOSFET structure. If a higher donor concentration is to be made possible, countercharges for the donor atoms of the drift path or of the n ^{- region} must be found approximately in the same component plane as the drift path. In MOS field plate transistors with trench structure, as is known from the publication US 6,573,558 B2 are known, this is done by the charge carriers of the field plate.

at Compensating components such as the "CoolMOS", alternating in cells have arranged n-areas and p-areas, this happens by acceptors of the p-regions as countercharges.

In this context, a weakly doped n ^- or p ^{- region is} understood as meaning an impurity concentration [N] which can be either a donor concentration [N _D ] or a complementary acceptor concentration [N _A ] and between 1 × 10 12 cm -3 ≤ [N] ≤ 1 × 10 16 cm -3 is.

A medium-doped n- or p-type region is understood as meaning a region of a semiconductor power component, the average impurity concentration between 1 × 10 16 cm -3 ≤ [N] ≤ 1 × 10 18 cm -3 having. A highly doped n ⁺ or p ⁺ region is understood as meaning a region of a semiconductor power component which is heavily doped and has an impurity concentration between 1 × 10 18 cm -3 ≤ [N] ≤ 1 × 10 20 cm -3 having. A metallically conductive semiconductor region is understood as meaning a region of a semiconductor power component which has an extremely high doping and an impurity concentration between 1 × 10 20 cm -3 ≤ [N] ≤ 1 × 10 22 cm -3 having.

If the electrical conductivity of a drift path with n ^- -conducting zones by compensation structures such. B. in a "CoolMOS" can be further improved so that it reaches a mean n-type dopant concentration, the degree of compensation must be adjusted more accurately. This is already reaching the limits of technological feasibility, so that the drift distance of "CoolMOS" semiconductor power devices has an impurity concentration up to [N] ≦ 2 × 10 ¹⁷ cm ^-3 .

From US 6,573,558 B2 known MOS field plate transistors with trench structure have the disadvantage that depending on the type of connection of the field plate either at the source or at the drain end to the n ^- area the full reverse voltage drops and thus very thick insulation layers are required. At 600 V continuous load, an approximately 3 μm to 6 μm thick SiO ₂ would be required, which significantly reduces the effect of the field plate in the provision of countercharges for the drift path.

Instead of a more exact compensation at the "CoolMOS" became with the patent applications DE 10 2004 007 197 A1 and DE 10 2004 007 196 A1 proposed that the counter-charge is provided by a trench structure with a significantly higher dielectric constant than the surrounding Si. In order to create technically or economically attractive possibilities of use, the relative dielectric constant of the insulator, with which the trench is filled in the Si, would have to be approximately ε _r ≈ 1000. With typical trench widths and widths of the drift path in the range of a few μm, it is possible to achieve on-resistance values for 600 V components, which are already a factor of 3 better than in "CoolMOS" today.

Other semiconductor power devices with trench structure are from the document US 6,608,350 B2 known. With such known trench structures, a high-voltage transistor having a low on-state resistance can be formed on an n ⁺ -type semiconductor substrate having a lightly doped semiconductor body region on the n ⁺ -type semiconductor substrate by diffusing compensation regions from the trench structure into the lightly doped semiconductor body region. The trench can be filled with a dielectric or a highly resistive semi-insulating material, as it is also in the DE 19848828 C2 is described. Semiconductor power devices with trench structure are also from the documents US 4,893,160 A and US 5,282,018 A known.

Further miniaturization of semiconductor power devices for high voltage applications, there is a growing need to further reduce the on-resistance of the drift path in order, on the one hand, to reduce the power loss and thus the heating of the semiconductor power component and, on the other hand, to increase the permissible forward currents in the on-state, without having to increase the required semiconductor chip area.

task The invention is a semiconductor power device with drift path and trench structure indicating a further increased rated current density in case of passage and a much higher one Doping the drift path by an improved charge carrier compensation structure allows.

These The object is achieved with the subject matter of the independent claims. advantageous Further developments of the invention will become apparent from the dependent claims.

According to the invention is a Semiconductor power device with charge compensation structure created. The semiconductor power device is a field effect device with a vertical weak to moderately doped drift path between a first electrode on top of the semiconductor power device and a second electrode on the back side of the semiconductor power device. The drift path has vertically erect drift zones, the from a vertically oriented trench structure for carrier compensation are surrounded. The trench structure has an anisotropically conductive material alternating in planes orthogonal to the trench depth and low conductivities and in the direction of the trench depth a low conductivity having.

In This connection is under high electrical conductivity a conductivity understood, which comes close to a metallic conductivity. Below lower conductivity resistances are understood as with weakly doped semiconductors, with plastics and / or occur in insulating materials and ceramics. Under lower conductivity becomes an electrical conductivity understood that reaches a value between the high conductivity and the low conductivity lies, with the low conductivity at least one order of magnitude and preferably more than five orders of magnitude is lower than the high conductivity.

In a preferred embodiment According to the invention, the trench structure has a crystalline carbon in the form of a graphite, in which highly conductive, hexagonal structured Crystal lattice planes with non-conductive layers between them Van der Waals Alternate binding planes. These crystal lattice planes are orthogonal arranged to the trench depth. This results in one of atomic layers composite structure, in the monoatomic planes with high conductivity with bonding levels without atomic hulls alternately so that in the course of the trench depth monoatomic planes, in which the potential level is kept, with binding areas alternate, in which a fraction of the voltage applied to the trench structure is reduced. In this embodiment The invention is only about a crystalline carbon in the trench structure and the growth of the graphite structure in such a way to control that the crystal lattice planes are orthogonal to the trench depth Arrange.

In a further preferred embodiment According to the invention, the material of the trench structure comprises a filled plastic on which is filled with agglomerates of electrically conductive nanoparticles, wherein the agglomerates layer by layer conductive networks in planes orthogonal to the trench depth, which alternate with insulating plastic layers. Agglomerates of layered conductive networks can be opened up Apply plastic layers in the trench structure by sputtering, so that in the change of dusting of nanoparticle agglomerates and insulating plastic layers a structure results in which in the levels with conductive networks and channels from agglomerates a potential level is maintained, and between the electrically conductive networks stacked in the trench Stress reduction in the respective plastic layers takes place. In order to is achieved that in the adjacent drift a corresponding Field distribution trains that allows for higher concentrations at dopants in the drift path, for example with an epitaxial Deposition, can be introduced.

Preferably For example, the material in the trench structure is an anisotropically conductive Adhesive. Such adhesives are characterized in that when printing the adhesive forms a highly conductive layer and without such a pressurization a high electrical Retains resistance. This can be used to the effect that in the trench structure the adhesive is introduced layer by layer, and the layers alternately under a high pressure atmosphere and cure under normal pressure or vacuum. In the highly conductive, under Pressure cured Layers, in turn, the potential is fixed locally, while in the insulating layers between the electrically highly conductive Layers the voltage applied to the trench structure iteratively degrades. The effect on field distribution in the drift path is similar, as with a layer capacitor in the trench structure.

Thus, in the described and the three following preferred embodiments, layers with high and low conductivity can be used in the direction of the trench structure on a microscopic scale occur alternately so that macroscopically still results in a low conductivity in the direction of the trench.

In a further preferred embodiment According to the invention, the trench structure alternately has carbon nanoparticles and insulating plastic layers in such a way that alternately Layers of a conductive carbon network and monomolecular or some molecule layers alternating strong layers of insulating plastic. This structure The graphite structure is already very close because the plastic layers between the conductive carbon networks with a monomolecular Layer thickness only slightly more than 1.0 nm thick. This structure has opposite The graphite structure has the advantage that a breeding of crystalline carbon in a trench structure is not required. Rather, the Carbon networks also have amorphous structures with corresponding conducting channels exhibit.

In a further preferred embodiment invention, the trench structure alternately electrically conductive, highly doped silicon nanoparticles and insulating plastic layers on. The alternating levels change from a conducting one highly doped silicon network and monomolecular or some molecular layers strong levels of insulating plastic. Also this trench structure comes the replenishment the trenches with a crystalline carbon in the form of graphite very close because the insulating plastic layers are applied very thin and the Silicon nanoparticles have a mean grain size of the order of magnitude of a few nanometers.

In Another trench structure is replaced by metal nanoparticles and insulating plastic layers in such a way that levels off with a conductive metal network and monomolecular or some molecular layers strong levels of insulating plastic in the vertical direction alternate. In this vertical direction means that the levels extend orthogonal to the trench depth. The introduction of high Concentrations of metal nanoparticles for forming metal networks on a very thin Plastic layer is possible by that alternating metals and plastic on each other in the trench structure by sputtering or chemical-physical Deposition be applied.

Farther it is envisaged that the anisotropically conductive material of the trench structure in its thermal expansion behavior the thermal expansion behavior adapted to the semiconductor body is. This is particularly advantageous for semiconductor power devices with blocking voltages over 100 volts, especially in such semiconductor power devices the Trench depth is several 10 microns. For unadapted coefficients of expansion would one grave filling lead to a semiconductor wafer or a semiconductor chip to a warpage, which make the subsequent process steps difficult or impossible.

Semiconductor power devices are preferably produced as MOSFETs or IGBTs or bipolar transistors or by pn ^- n diodes and / or as Schottky diodes with a corresponding charge compensation structure according to the invention in the drift paths.

One Process for producing a semiconductor wafer with in lines and Columns arranged semiconductor chip positions for semiconductor power devices with charge compensation structure has the following process steps on. First becomes a heavily doped semiconductor wafer of a first conductivity type produced. On this highly doped semiconductor wafer is a weak to medium doped epitaxial layer of the same conductivity type for the formation of drift paths in the respective semiconductor chip positions applied. After completion of the epitaxial layer, whose Thickness depends on the reverse voltage resistance of the power semiconductor device, is in the epitaxial layer, a trench structure to form Drift zones of epitaxial material surrounded by the trench structure be introduced.

there can preferably the trench structures and the drift paths in Shape of juxtaposed honeycombs on the semiconductor wafer in the semiconductor chip positions. In this case will be as a trench structure columnar etching holes in introduced the epitaxial layer.

After that is an anisotropic conductive material in the trench structures of Semiconductor chip positions deposited, the material in planes orthogonal to the trench depth alternating high and low conductivities has and in the direction of the trench depth a lower conductivity has. The definition of high and low conductivity, and low conductivity has already been explained above.

Next, formation of a first electrode terminal pattern in an upper portion of the epitaxial layer in the semiconductor chip positions occurs as far as the formation of a body region of a complementary conductivity type and a heavily doped junction region for the first electrode is concerned. These are merely preparations for applying the corresponding first electrode such as a collector, anode or source electrode per semiconductor power device type on the top side of the semiconductor body. In the case of MOSFETs or IGBTs the These method steps also include the preparation of a third electrode in the form of an insulated gate on the semiconductor body. Thereafter, the electrodes can be mounted on top of the semiconductor body.

To this preparation of the surface of the Semiconductor body is a metal layer on the back of the semiconductor wafer forming a second electrode in the semiconductor chip positions. So practically all functional areas are for one Semiconductor power chip in the respective semiconductor power chip positions arranged and completed the semiconductor wafer. For the production of the semiconductor chip itself, the semiconductor wafer is merely along the rows and columns are split, and the semiconductor chips become in appropriate housings packed into semiconductor power devices.

Instead of this procedure, at first an epitaxial layer made on a heavily doped semiconductor wafer and then a trench structure is introduced into this epitaxial layer can, in an alternative method, be described in the following will also be reversed. In the alternative Process for producing a semiconductor wafer with in lines and Columns arranged semiconductor chip positions for semiconductor power devices with charge compensation structures, the following process steps carried out.

First, As in the above method, a heavily doped semiconductor wafer of a provided first conductivity type. Subsequently, on this highly doped Semiconductor wafer first no epitaxial layer grown, but a layer of anisotropic conductive material with layered anisisotropy of conductivity deposited, with the layered anisisotropy of the conductivity is formed such that the layers alternately high and low conductivities have, and orthogonal to the layer plane, a lower conductivity consists.

To producing such a layer of anisotropically conductive Material becomes a selective removal of the anisotropic conductive layer partially exposing the surface of the heavily doped substrate performed in the semiconductor chip positions. After the surface of the highly doped semiconductor wafer is partially exposed, is a weak to medium doped Epitaxial layer of the first conductivity type on the semiconductor wafer applied to the formation of drift zones. These drift zones are then from the anisotropic guide the material of the layer in the semiconductor chip positions surround.

After that can form a first electrode connection structure in a upper portion of the epitaxial layer in the semiconductor chip positions as far as the formation of a body zone of the complementary conductivity type is concerned and a heavily doped junction zone of the first conductivity type for Applying the first electrode is. This is the structuring completed the top of the semiconductor wafer. Then you can the bottom or back the semiconductor wafer, a metal layer are applied, the for forming the second electrodes in the semiconductor chip positions is required.

After completion of such a semiconductor wafer, only the semiconductor wafer is separated into its chip positions for the production of semiconductor power devices, and the individual semiconductor power chips are packaged in corresponding housings for semiconductor power components. Semiconductor power devices of the MOSFET type, of the IGBT type, of the bipolar transistor type as well as of the pn ^- n diode type and / or of the Schottky diode type with charge compensation structures can preferably be produced with this method.

Preferably becomes the formation of the first electrode terminal structure in a upper portion of the epitaxial layer in the semiconductor chip positions performed to a source-gate structure. First, the Forming a body zone of the complementary conductivity type, for example by diffusion or ion implantation plus diffusion and a heavily doped source connection zone of the first conductivity type introduced into this body zone. This structure will be found then in the upper area of the epitaxial layer while on the epitaxial layer a gate oxide and then a gate electrode as a third electrode of a MOSFET or a IGBTs is produced.

With the application of a metal layer on the back side of the semiconductor wafer as a second electrode, practically a drain electrode of a MOSFET or cathode of a pn ^- n diode is completed. If instead of a heavily doped substrate of the first conductivity type, a highly doped substrate of the complementary conductivity type or a backside ion implantation and diffusion with impurities of the complementary conductivity type is performed, then a backside emitter of an IGBT can be arranged as a second electrode on the backside of the semiconductor body.

In a preferred embodiment of the method, for the deposition of an anisotropically conductive material or for depositing a layer of anisotropically conductive material on a semiconductor wafer, carbon is deposited such that a graphitic structure of the carbon with highly conductive, hexagonal structured crystal lattice planes and with non-conducting Van der Waalian bonding planes arranged therebetween is formed alternately.

The Formation of a crystalline carbon structure in the form of the graphite structure on a silicon semiconductor wafer is by suitable deposition parameters by means of a chemical vapor deposition or by means of Pyrolysis feasible. It is easier, the entire wafer evenly with a layer of the anisotropically conductive material of the graphite to provide, as in an already prefabricated and structured Trench structure to grow graphite crystals.

insofar would be here the above mentioned alternative methods are used to package such semiconductor power devices manufacture.

In a further embodiment of the Procedure will be for depositing an anisotropically conductive material in the trench structure or for the Depositing a layer of an anisotropically conductive material on a semiconductor wafer alternating carbon nanoparticles and Insulating plastic layers deposited in such a way that layers with a conductive carbon network and monomolecular planes alternating of insulating plastic. For this separation both can Method, used with and without prepared trench structure Especially since the deposition of carbon nanoparticles on monomolecular Layers of insulating plastic by appropriate sputtering or CVD deposition techniques possible is.

at another implementation The method is intended for depositing an anisotropic conductive material or for depositing a layer of anisotropically conductive material a semiconductor wafer substrate alternately metal nanoparticles and isolate insulating plastic layers in such a way that levels with a conductive metal network and monomolecular or few molecular layers alternating strong layers of insulating plastic. Also with this procedure it is advantageous that the monomolecular or a few molecule layers strong Plastic layer by means of, for example CVD or plasma deposition and the metal network of metal nanoparticles, for example by means of Sputtering, both in a prepared trench structure, as well on the unstructured top of a semiconductor wafer relatively unproblematic can be realized.

Farther it is intended for the deposition of an anisotropically conductive material or for deposition a layer of anisotropically conductive material on a semiconductor wafer alternating agglomerates of electrically conductive nanoparticles and isolate insulating plastic layers such that Layers with a conductive network of conductive agglomerates and alternate layers of insulating plastic. Such agglomerates from nanoparticles assume that these networks have a thickness which show several tens of nanometers in thickness and due to the Agglomeration a relatively uneven distribution in the highly conductive Have levels, so that as insulating plastic layer a monomolecular layer is insufficient, but rather an insulating Plastic layer of several 10 nanometers thickness is produced.

As already mentioned above, the preferred deposition methods for the nanoparticles are the sputtering or the CVD method while for training the trench structure in an anisotropically conductive layer on a Semiconductor wafers and also for forming a trench structure in an epitaxial layer Semiconductor material, a laser ablation is possible. On the other hand Such structures also achieved by dry etching in the plasma.

In summary it should be noted that the invention is a deposition of a layer with strongly anisotropic electrical conductivity in a trench structure of sufficient depth, ideally the conductivity be very high in the lateral direction orthogonal to the trench depth should, while she in the vertical direction, that is so in the direction of the trench depth, should be extremely small. Furthermore should be within this layer of high electrical layers conductivity and alternate layers with minimal electrical conductivity. About free charge carrier the lateral stratification then becomes charges for compensation the dopant charges in the adjacent semiconductor material of Drift zones provided. By contrast, the vertical low causes conductivity in the direction of the trench depth an additional leakage current path, the with the help of low conductivity should be minimized. With such a deposition of an anisotropic Material in a trench structure is the production cost for such Semiconductor power components noticeable reduced.

A preferred example of a highly anisotropic material is graphite. This graphite forms a layer grid with even layers. Within the layers, each carbon atom is surrounded by a neighbor, the carbon atoms joining together into hexagonal lines according to their environment, as is known from the benzene ring. These hybridized than sp ₂ carbon atoms exhibit perpendicular to the hybrid standing p _z orbitals on a fourth valence. These orbitals extend over the entire layer and show a delocalized (p _i ) bond system, half of which is occupied by electrons.

While now within the hexagonal crystal lattice, the cohesion through Covalent bonds are caused to act between the individual Layers only weak Van der Waal forces. For this reason, results an approximate metallic conductivity in the hexagonal layers while the resistance between the layers with sufficient material quality extreme can be high. Accordingly, graphite is an ideal filler for the Trench structure of the semiconductor power device.

Instead of Of graphite but also offer other materials, such as Polymers on. Analogous to the contacting of LCDs also materials can be used which are an electrically conductive material, such as based on amorphous carbon, or doped silicon particles or of finely divided metal particles, in an insulating Matrix is located. This matrix is designed so that in one Level free, with the conductive Particles filled Channels exist, which can also be branched, and in the vertical direction such connections are ideally absent Completely or are much less common.

A Another known variant of such anisotropically conductive materials are known as so-called anisotropic conductive adhesives in which the Example by applying pressure in one direction a conductive electrical Compound can be generated while orthogonal to an almost perfect isolation prevails.

One particular advantage of the invention, with such materials works, is that the thermal expansion behavior by the Use of inorganic fillers to the expansion behavior of a semiconductor material, such as silicon, at least approximated can be adjusted. This is especially true for components above of 100 volts blocking capability important because because of the wide space charge zone correspondingly deep Trench structures needed be, with high thermomechanical stresses at unmatched thermal expansion behavior of conventional filled trench structures on a semiconductor wafer and in the components at least one strong warping of the Can cause components or the semiconductor wafer.

As already mentioned above is it beneficial for that Manufacturing process, depending on the material or composite material, first to create the trenched semiconductor structure, and then the anisotropically electrically conductive To introduce material into the trench structure, or if necessary also to proceed in reverse, in the first on a semiconductor wafer, the anisotropically electrically conductive material is generated as a layer, and then introduced trenches in this material that will be over then epitaxial deposition with corresponding semiconductor material and so that they are filled with appropriate drift path material.

The The invention will now be described with reference to the accompanying figures.

1 shows schematically the structure of an anisotropic conductive material for semiconductor power devices, using the example of a graphite lattice;

2 shows a schematic cross section through a semiconductor power device 1 , according to an embodiment of the invention.

1 shows schematically the structure of an anisotropically conductive material for semiconductor power devices, using the example of a graphite lattice 29 , The graphite grid 29 has hexagonal crystal lattice planes 14 with covalent bonds that extend in layers across the crystal lattice, with the conductivity latticed into this hexagonal crystal 14 corresponds to a metallic conductivity. Between the hexagonal crystal lattice planes 14 In the z-direction, p _z orbitals of the fourth valence electron are arranged, which form a bond plane 18 between the hexagonal crystal lattice planes 14 span, which is dominated only by Van der Waal forces. This binding level 18 therefore has a low electrical conductivity.

If graphite lattices are arranged in a trench structure of a semiconductor power component, electrically highly conductive crystal lattice planes alternate 14 with electrically low conductive bonding levels 18 from. The conductivity in the z-direction is accordingly opposite to the conductivity of the hexagonal crystal planes 14 greatly reduced. In 1 Let the marks a on the z-axis be the center of the hexagonal crystal lattice planes 14 while mark b is the center of the binding plane 18 marked on the z-axis. The four connecting lines between the carbon atoms C on graphite lattice sites symbolize the four valence electrons of the carbon atoms C.

2 shows a schematic cross section through a semiconductor power device 1 , according to an embodiment of the invention. The semiconductor power device 1 has a semiconductor body 3 on top of a heavily doped substrate 19 a first conductivity type n and a drift path 4 exists, which has a length l and from the top 20 of the semiconductor body 3 up to the top 23 of the substrate 19 extends. The half lead terkörper 3 points to its top 20 at least one first electrode 5 which is a source electrode S in this embodiment of the invention. On the back side 26 has the semiconductor body 3 a second electrode 6 which is a drain electrode D in this embodiment of the invention.

A gate electrode 7 is formed as a planar gate G and has a polysilicon layer. The polysilicon layer is through a gate oxide layer 24 from a channel region in a p-type bodyzone 21 isolated, wherein the channel region of a boundary of a heavily doped source region 25 of the same conductivity type as the n-type drift path 4 , to the limit of the drift distance 4 in the body area 21 extends and in an upper area 28 the epitaxial layer 27 is arranged.

In this embodiment of the invention is as a charge compensation structure 2 a trench structure 8th in the drift route 4 from the top 20 of the semiconductor body 3 up to the top 23 of the substrate 19 within the source area 25 introduced so that adjacent drift zones 9 form. The walls 16 the trench structure 8th are with an insulation layer 17 covered in silicon dioxide. The thickness w of the insulation layer 17 is in the range of 0.03 μm ≤ w ≤ 3 μm. The semiconductor body 3 consists of a monocrystalline silicon crystal of the heavily doped substrate 19 and from the drift track 4 consisting of one or more monocrystalline epitaxial layers 27 is formed.

An isolation layer 17 made of silicon dioxide has the advantage that after an introduction of a trench in the source region 25 through the drift path 4 through to the top 23 of the heavily doped substrate 19 , the insulation layer 17 by thermal oxidation of the silicon of the trench walls 16 can be produced. Other insulation layers 17 may be by nitriding the silicon material, or by physical deposition, for example in the form of sputtering, or by plasma deposition or by CVD deposition on the walls of the trench structure 8th , getting produced. In the trench structure 8th an anisotropically conductive material is arranged, which consists of a stack 13 composed of electrically highly conductive material layers and electrically low conductive or insulating layers of material alternately.

These layers along the trench depth t are preferably monatomic or monomolecular layers arranged alternately 11 respectively. 12 , so that a potential distribution 15 in the trench structure setting in the drift path 4 influences the field distribution. The potential distribution 15 in the trench structure schematically shows the diagram on the right side of the 2 , The abscissa shows the voltage U and the ordinate the drift path length x. Due to the applied drain voltage U _D , a step voltage ΔU is applied to each of the very thin material layers with low electrical conductivity. This potential distribution 15 within the trench structure 8th influences the field distribution of the drift path 4 such that a higher dopant concentration and thus a lower on resistance of the semiconductor device between the two electrodes 5 and 6 is possible without the maximum reverse voltage U _{max is} reduced.

The dopant concentration in the drift path 4 may be due to the trench structure 8th with an anisotropically conductive material 10 by about a further 10 power over semiconductor devices with drift paths, as they are known from the above-mentioned documents, can be increased. The representation, both the potential distribution 15 in the trench structure 8th , as well as in the alternating sequence of a highly conductive atomic layer 12 and a nearly insulating acting layer 11 is not true to scale, but strongly distorted, since the voltage curve between mono-atomic layers and / or monomolecular layers can only be represented in principle.

The conductivity within the trench structure 8th in the vertical z-direction is significantly lower than the electrical conductivity in the areas 12 with high electrical conductivity, and thus has an anisotropy of the conductivity between the alternating horizontal regions of low conductivity 11 and high conductivity 12 , as well as an anisotropy between the conductivity in the vertical z-direction of the trench structure in relation to the horizontally alternating regions 11 and 12 which extend orthogonal to the z-direction.

1

Semiconductor power device

2

Charge compensation structure

3

Semiconductor body

4

drift or drift zone

5

source electrode or first electrode

6

drain or second electrode or metal layer

7

gate electrode or third electrode

8th

grave structure

9

drift region

10

anisotropic conductive material

11

alternating Low conductivity range or level

12

alternating Range of high conductivity or Level or plastic layer

13

stack from monomolecular layers

14

Crystal lattice plane

15

potential distribution

16

wall the trench structure

17

insulation layer

18

van the Waal binding plane

19

highly paid Semiconductor wafer

20

top the semiconductor wafer or semiconductor power component

21

Body zone

23

top of the substrate

24

gate oxide layer

25

highly paid source region

26

back the semiconductor wafer or the semiconductor power component

27

epitaxial layer

28

upper Area of the epitaxial layer

29

graphite lattice

a

hexagonal Crystal planes with covalent bonding

b

van the Waal binding plane with orbitals of the fourth valence electrons

C

Carbon atom on graphite grid

D

drain

G

gate

l

Length of drift

n, p

cable types

S

source electrode

t

grave depth

.DELTA.U

Voltage drop across one insulation layer

U _max

Voltage blocking capability

w

thickness the insulation layer

Claims (15)

Semiconductor power device with charge compensation structure ( 2 ), wherein the semiconductor power device ( 1 ) a field effect device with a vertical weak to medium doped drift path ( 4 ) between a first electrode ( 5 ) on the top ( 20 ) of the semiconductor power device ( 1 ) and a second electrode ( 6 ) on the back side ( 26 ) of the semiconductor power device ( 1 ), wherein the drift path ( 4 ) vertically oriented drift zones ( 9 ) formed by a vertically oriented trench structure ( 8th ) as a charge compensation structure ( 2 ), and wherein the trench structure ( 8th ) an anisotropically conductive material ( 10 ), which in layers ( 11 . 12 ) orthogonal to the trench depth (t) has alternating high and low conductivities and in the direction of the trench depth (t) has a low conductivity, wherein the anisotropically conductive material is selected from the group consisting of: a) graphite whose levels ( 11 . 12 ) with highly conductive hexagonal structured crystal lattice planes ( 14 ) with intervening non-conducting Van der Waal binding planes ( 18 ) are arranged orthogonal to the trench depth (t); b) filled plastic filled with agglomerates of electrically conductive nanoparticles, wherein the agglomerates layer by layer conductive networks in planes ( 12 ) orthogonal to the trench depth (t), which are coated with insulating plastic layers ( 11 ) alternate; c) anisotropically conductive adhesive; d) carbon nanoparticles ( 11 ) and insulating plastic layers arranged such that alternating planes ( 12 ) from a conductive carbon network and monomolecular layers ( 11 ) or levels ( 11 ) alternate from several molecule layers of an insulating plastic; e) electrically conductive highly doped silicon nanoparticles and insulating plastic layers arranged such that alternating planes ( 11 . 12 ) from a conductive highly doped silicon network ( 12 ) and monomolecular planes ( 11 ) or levels ( 11 ) alternating from several molecular layers of an insulating plastic and f) metal nanoparticles and insulating plastic layers ( 11 ) arranged such that planes ( 11 . 12 ) with a conductive metal network ( 12 ) and monomolecular planes ( 11 ) or levels ( 11 ) alternate from several molecule layers of an insulating plastic in the vertical direction. Semiconductor power device according to claim 1, characterized in that the anisotropically conductive material ( 10 ) of the trench structure ( 8th ) in its thermal expansion coefficient the thermal expansion coefficient of the semiconductor body ( 3 ) is adjusted. Semiconductor power component according to one of the preceding claims, characterized in that the semiconductor power component ( 1 ) a MOSFET, an IGBT, a bipolar transistor, a pn ^- n diode and / or a Schottky diode with charge compensation structure ( 2 ) having. Method for producing a semiconductor wafer with semiconductor chip positions arranged in rows and columns for semiconductor power devices ( 1 ) with charge compensation structure ( 2 ) according to one of claims 1 to 3, wherein the method comprises the following method steps: - producing a highly doped semiconductor wafer of a first conductivity type (n ⁺ or p ⁺ ); Application of a weakly to medium doped epitaxial layer ( 27 ) of the first conductivity type for the formation of drift paths ( 4 ) in the semiconductor chip positions on the semiconductor wafer; - introduction of a trench structure ( 8th ) into the epitaxial layer ( 27 ) with the formation of drift zones ( 4 ) of epitaxial material derived from the trench structure ( 8th ) in the semiconductor chip positions; Depositing an anisotropically conductive material ( 10 ) in the trench structures ( 8th ) of the semiconductor chip positions, the material ( 10 ) in levels ( 11 . 12 ) orthogonal to the trench depth (t) alternately high and low conductivities and in the direction of the trench depth (t) has a low conductivity; Forming a first electrode connection structure in an upper region ( 28 ) epitaxial layer ( 27 ) in the semiconductor chip positions as far as the formation of a body zone ( 21 ) of the complementary conductivity type and a heavily doped junction zone ( 25 ) of the first conductivity type; Applying a metal layer to the backside of the semiconductor wafer ( 26 ) forming a second electrode ( 6 ) in the semiconductor chip positions. Method for producing a semiconductor power component ( 1 ) with charge compensation structure ( 2 ) according to one of claims 1 to 3, wherein the method comprises the following method steps: - producing a highly doped semiconductor wafer of a first conductivity type by a method according to claim 4; Separating the semiconductor wafer into semiconductor chips, packaging the semiconductor chips into semiconductor power devices ( 1 ). A method according to claim 4 or 5, characterized in that for selective removal of the layer of anisotropically conductive material ( 10 ) a laser ablation process is used. A method according to claim 4 or 5, characterized in that for a selective removal of the layer of ( 10 ) conductive material or for introducing a trench structure ( 8th ) into the epitaxial layer ( 27 ) a plasma dry etching is used. Method for producing a semiconductor wafer with semiconductor chip positions arranged in rows and columns for semiconductor power devices ( 1 ) with charge compensation structure ( 2 ) according to one of claims 1 to 3, wherein the method comprises the following method steps: - producing a highly doped semiconductor wafer of a first conductivity type; Depositing a layer of anisotropically conductive material ( 10 ) on the semiconductor wafer with layered anisotropy of the conductivity such that the layers ( 11 . 12 ) have alternating high and low conductivities and a low conductivity orthogonal to the layer plane; Selective removal of the layer of anisotropically conductive material ( 10 ) with partial exposure of the upper side ( 23 ) of the heavily doped substrate ( 19 ) in the semiconductor chip positions; Introduction of a weakly to medium doped epitaxial layer ( 27 ) of the first conductivity type on the semiconductor wafer into the generated trenches in the anisotropic conductive material to form drift zones ( 9 ) derived from the anisotropically conductive material ( 10 ) of the layer are surrounded in the semiconductor chip positions; Forming a first electrode connection structure in an upper region ( 28 ) of the epitaxial layer ( 27 ) in the semiconductor chip positions as far as the formation of a body zone ( 21 ) of the complementary conductivity type and a heavily doped junction zone ( 25 ) of the first conductivity type; Applying a metal layer to the backside of the semiconductor wafer ( 26 ) forming a second electrode ( 6 ) in the semiconductor chip positions. Method for producing a semiconductor power component ( 1 ) with charge compensation structure ( 2 ) according to one of claims 1 to 3, wherein the method comprises the following method steps: - producing a highly doped semiconductor wafer of a first conductivity type by a method according to claim 8; Separating the semiconductor wafer into semiconductor chips, packaging the semiconductor chips into semiconductor power devices ( 1 ). Method according to one of Claims 4 to 9, characterized in that MOSFETs, IGBTs, bipolar transistors, pn ^- n diodes and / or Schottky diodes with charge compensation structure (US Pat. 2 ) getting produced. Method according to one of claims 4 to 10, characterized in that forming the first electrode connection structure in an upper area ( 28 ) of the epitaxial layer ( 27 ) is performed in the semiconductor chip positions to a source-gate structure by forming a body zone ( 21 ) of the complementary conductivity type and a highly doped source connection zone ( 25 ) of the first conductivity type in the epitaxial material and on the epitaxial layer ( 27 ) the formation of a gate oxide ( 24 ) and a gate electrode (G) as a third electrode ( 7 ) of a MOSFET. Method according to one of claims 4 to 11, characterized in that with the application of a metal layer on the back ( 26 ) of the semiconductor wafer as a second electrode ( 6 ) a drain electrode (D) is produced. Method according to one of claims 4 to 12, characterized in that for the deposition of an anisotropically conductive material ( 10 ) in the trench structure ( 8th ) or for the deposition of a layer of anisotropically conductive material ( 10 ) are used on a semiconductor wafer sputtering. Method according to one of claims 4 to 12, characterized in that for the deposition of an anisotropically conductive material ( 10 ) in the trench structure ( 8th ) or for the deposition of a layer of anisotropically conductive material ( 10 ) are used on a semiconductor wafer deposition process from the gas phase. Method according to one of claims 4 to 12, characterized in that for the separation that of an anisotropically conductive material ( 10 ) in the trench structure ( 8th ) or for the deposition of a layer of anisotropically conductive material ( 10 ) are used on a semiconductor wafer chemical or physical vapor deposition processes.