DE102005044142B3 - Production of electroconductive filling in trench in a semiconductor substrate or layer and a trench capacitor fills trench with silicon and phosphorus and deposits an arsenic monolayer - Google Patents

Abstract

A production process for an electrically conductive filling (30) in a trench in a semiconductor substrate (10) or layer comprises preparing the substrate and trench, depositing amorphous or polycrystalline silicon and phosphorus simultaneously in the trench and then forming at least one monolayer of arsenic atoms on the silicon/phosphorus interface. An independent claim is also included for a trench capacitor in a semiconductor substrate as above.

Description

The The invention relates to a method for producing an electrical conductive filling in a trench, which in a semiconductor substrate or in a Layer is formed on the semiconductor substrate. The invention relates about that in addition, in particular according to the method produced, trench capacitor.

at Semiconductor manufacturing becomes trenches in semiconductor substrates or in layers formed thereon to be electrically conductive conductive Structures on the one hand or isolation areas on the other Page to ask. In the first case, the trenches after their formation - often by means of an etching step - with a electrically conductive filling provided, for example, conductor tracks, contact plugs or To form capacitor electrodes. Especially with those in the monocrystalline semiconductor substrate (Silicon) produced trenches instead of a metal mostly an amorphous or polycrystalline Silicon layer deposited, which improves the electrical conductivity is doped.

The Deposition of doped, amorphous or polycrystalline silicon as an electrically conductive filling especially applied in the case of trench capacitors. Trench capacitors include deeply etched into the semiconductor substrate with very high aspect ratio, the as a quotient of height or calculate the depth and width of the trench.

Of the Trenching of the trench capacitor is usually on the inner wall with a thin capacitor dielectric Mistake. This classically consists of a layer sequence of Oxide, nitride and again oxide (ONO). Other dielectric materials are also possible. A lower portion of the trench is in the semiconductor substrate of surrounded by a buried doped region, which comprises a first capacitor electrode forms. The electrically conductive filling inside the trench forms the second capacitor electrode.

In a dynamic memory with random read or write access (DRAM, dynamic random access memory) will store over one accomplished selection transistor connected to the trench capacitor. This one is about one Controlled word line, so that in the electrically conductive filling in Digging the trench capacitor electrical charges from a bit line can be written or read in this.

is a doping with donors provided (n-doping), is in the Usually an element of the fifth Main group in the periodic table of elements for the deposition of poly-silicon added. For example, the n-doping of the amorphous is known or polycrystalline silicon either with arsenic or with phosphorus. In the case of arsenic, LPCVD (Low Pressure Chemical Vapor Deposition) or a CVD reactor (Chemical Vapor Deposition) in Each step first the amorphous or polycrystalline silicon deposited on the substrate, then, in a second step, a short separation of Arsenic to form monolayers on the surface of amorphous or polycrystalline Silicon layer takes place. The steps can be repeated. It this results in a digital doping profile, which is only achieved by thermal post-processing is converted into a homogeneous doping profile, so that the arsenic atoms are incorporated into the poly-silicon lattice.

The Alternating deposition steps in the LPCVD or the CVD reactor are in comparison somewhat time-consuming for a uniform, simultaneous separation step. The However, simultaneous deposition of arsenic with the poly-silicon has become in the high aspect ratios and the not insignificant dopant depletion (electrical activation only at 10% to 50%) in the case of arsenic in the condenser trenches as difficult to prove. On the other hand, the digital doping profile also throws according to the sequential Abscheidide problems in that, if the Abscheidedicke the amorphous or polycrystalline silicon layer inaccurate against the Trench width is determined, each time the last steps of the deposition by arsenic no longer feasible are. Due to this, the degree of doping in the electrical conductive filling deviate significantly from given target values.

On the other hand offers Phosphorus as an alternative dopant has the advantage that a simultaneous Depositing with amorphous or polycrystalline silicon also at high aspect ratios in the trenches possible is. Furthermore, in phosphorus, the degree of electrical Activation compared to arsenic much higher. The deposit has therefore a higher one Efficiency measured on the deposited material volume. At the same Number of deposited atoms is thus an improved conductivity reachable.

However, that in the current semiconductor production, in particular of memory modules, with random read / write access, the electrically conductive filling of the trench capacitors is not performed exclusively with phosphorus doping, is because when carried out with phosphorus, amorphous or polycrystalline silicon deposition, a migration of, for example holes filled with air in the ditch filling occurs to the trench walls, which can not be prevented. The formation of such holes (voids) is hardly avoidable and takes place in the growth process, which begins at the trench walls, approximately along the central axis of a seen from above round or oval trench. In the middle, the growing layers meet. In principle, such voids can also occur with arsenic-doped silicon. There, however, arsenic suppresses void diffusion much more efficiently than phosphorus.

Usually these disturb holes in the middle of the trench little because the cross section of the trench one having relatively low ohmic resistance. At the thermal However, post-processing can these holes to the moat walls migrate, which also occurs when doping with phosphorus, if the post-processing is carried out at very low temperatures. Are the holes then first at the moat walls, so occur there on the one hand very high field peaks, where the electric conductive filling on the edges the holes encounters the capacitor dielectric. Second, the effective capacitor area at the Grabeninnenwänden reduced to the buried doped region through the holes.

In the US 5,652,165 a method for producing a stacked capacitor is described. Prior to formation of the capacitor electrodes, transistors are fabricated on the substrate whose source / drain regions are made accessible by contact openings formed in an insulating layer. On the insulating layer and in the contact openings, a layer of polysilicon is deposited, which is doped in situ with arsenic and phosphorus.

In the EP 1 493 712 A2 a method of manufacturing MEMS devices is described in which amorphous silicon is deposited to form an electrically conductive layer structure. By doping with arsenic and phosphorus compressive stresses and tensile stresses are generated in the layers, which compensate to some extent.

In US 2002/0086481 A1 is a method for producing deeper Trench capacitors described. The inner walls of the ditch are covered with a lined dielectric layer, which is the capacitor dielectric forms. A capacitor electrode passes through inside the trench doped polysilicon formed. In an upper area of the ditch a doped polysilicon layer is arranged, for which a Implantation of arsenic and / or phosphorus is indicated.

In US 2004/0084149 A1 is an apparatus for forming silicon-containing Described films on a substrate. An example is given that the silicon-containing film is preferably amorphous and a or several other elements, including arsenic and phosphorus may contain. Another example relates to HSG silicon films (hemispherical silicon grain).

It An object of the present invention is an improved method for the To provide electrically conductive filling in trenches, which in particular also for the future expected further reduction of the structure sizes. It is a further object to provide a trench capacitor with improved To offer quality.

The Task is solved by the method for producing an electrically conductive filling in one Trench with the features of claim 1 or with the Trench capacitor with the features of claim 8.

The method for producing an electrically conductive filling in a trench, which is formed in a semiconductor substrate or in a layer on the semiconductor substrate, comprises the steps
Providing the semiconductor substrate with the trench and depositing the substances amorphous or polycrystalline silicon, arsenic and phosphorus to form the electrically conductive filling in the trench, wherein
the deposition of amorphous or polycrystalline silicon and the deposition of phosphorus are carried out simultaneously, the deposition of arsenic is carried out separately from the deposition of amorphous or polycrystalline silicon and phosphorus, and
depositing arsenic comprises forming at least one monolayer of arsenic atoms on a surface formed by the amorphous or polycrystalline silicon and the phosphorus.

• a) eine amorphe oder polykristalline Siliziumschicht,
• b) Phosphor und
• c) Arsen,

wobei in der Grabenfüllung der Phosphor homogen und das Arsen inhomogen zwischen dem amorphen oder polykristallinen Silizium verteilt ist;
ein als dielektrische Schicht an einer Innenwand des Grabens ausgebildetes Kondensatordielektrikum und
eine zweite als vergrabenes dotiertes Gebiet in dem Halbleitersubstrat an der Innenwand des Grabens ausgebildete Kondensatorelektrode.The object is also achieved by a trench capacitor in a semiconductor substrate, comprising a trench formed in a semiconductor substrate, a first capacitor electrode formed as an electrically conductive filling, which is deposited in at least one lower portion of the trench, wherein the electrically conductive filling comprises:

• a) an amorphous or polycrystalline silicon layer,
• b) phosphorus and
• c) arsenic,

wherein in the trench filling the phosphor is homogeneous and the arsenic is inhomogeneously distributed between the amorphous or polycrystalline silicon;
a capacitor dielectric formed as a dielectric layer on an inner wall of the trench; and
a second buried doped region in the semiconductor substrate formed on the inner wall of the trench capacitor electrode.

It For example, a semiconductor substrate, such as a semiconductor wafer, is provided. in which or in which a trench is formed in a layer. at the trench may be an arbitrarily shaped depression in the Substrate or act in the layer on the substrate. According to one embodiment the invention is the trench of a trench capacitor. This is typically done with very high aspect ratios from bigger than 10: 1 or 50: 1 formed. For example, digging can be a depth of 7 μm at a width of 90 nm. There is currently a desire these aspect ratios even further to enlarge. This especially with the transition be the case for 70 nm technology. This embodiment will be below closer to explain be.

at the trenches but it can also be those of deep tracks. In this case own the trenches a small width, but a considerably longer length. Even with such ditches can of big ones aspect ratios be the talk.

Of Others come as trenches also contact holes considering, for example, different metallization levels connect a circuit with each other. A use of amorphous or Polycrystalline silicon as trench filling (contact hole filling) comes especially when considered with the contact plug one Track and metallization level with doped areas on the is to connect monocrystalline substrate. An example is the Connection of bit lines to source / drain regions of a selection transistor in a memory cell with random read / write access.

It is further provided, the electrically conductive filling in the trench of amorphous or polycrystalline silicon doped with both arsenic and to set up with phosphorus. Separation steps are carried out in each case can be performed simultaneously or separately. It was the surprising Found that in a combination of the two dopants, the separation of which requires a greater effort in itself and would not normally have been sought, the benefits mentioned and benefits the respective material properties are retained. The disadvantages By contrast, the individual substances are replaced by the benefits of each other substance compensated.

So For example, it was found that when doping with arsenic those expected by the simultaneous doping with phosphorus Migration of the holes, which inevitably arise in the poly-silicon filling, towards the trench walls repressed becomes. The depletion of electrically active arsenic atoms in the electric conductive filling on the other hand becomes complete through the increased compensated for electrical activation of the phosphorus atoms.

In summary let yourself say that by combining arsenic and phosphorus as common Dopants for an electrically conductive filling Poly-silicon reliability the function - in particular a trench capacitor - as well the electrical properties in terms of conductivity sometimes considerably can improve.

phosphorus also delivers because of the higher Rate of activation also makes the bigger contribution to electrical conductivity. When arsenic is separated from poly-silicon in time, This creates a digital doping profile with the consequence of a insufficient As doping, if not the last monolayer more as desired into the ditch, because this is filled is. This effect then plays but because of the dominance of the contribution of Phosphorus only a minor role.

A particular advantage arises from the fact that the deposition of each of amorphous or polycrystalline silicon, phosphorus and arsenic can be carried out together in a (LP) CVD reactor. According to one embodiment of the invention, amorphous or polycrystalline silicon and phosphorus are deposited simultaneously, which can be done, for example, by adding phosphine gas (PH ₃ ) to the gas forming the amorphous or polycrystalline silicon layer (SiH ₄ ).

Subsequently, in the same (LP) CVD reactor, the deposition parameters such as temperature, pressure, etc. are varied to initiate arsine (AsH ₃ ) to produce one or more monolayers of arsenic on the surface formed after the first deposition of the phosphorus doped amorphous or polycrystalline silicon is formed or formed. Thereafter, it is possible to return to the original device parameters in order to again deposit an amorphous or polycrystalline silicon layer with a phosphorus doping. So it is not necessary to remove the semiconductor wafer from the reactor.

Embodiments with regard to the trench capacitor also provide those which are usually introduced later in an upper part of the trench Trench filling to be provided with a doping of phosphorus and arsenic. This offers the advantage of a continuous conductivity over the entire depth of the trench capacitor. The background is that usually first in the larger lower region of the trench, the capacitor electrode is formed on the basis of the electrically conductive filling. This is separated from the buried doped region as the second capacitor electrode by the capacitor dielectric (NO, ONO or Al ₂ O ₃ , etc.).

Of the The upper part of the trench is then inserted by an etch back process filling freed to bring in an insulation collar in the upper area, which in a dense memory cell array the considered capacitor trench isolated from a neighboring one. Subsequently, an electric again conductive filling introduced into the upper area, which by further steps connected to source and drain regions of a selection transistor becomes.

This upper area presents before its (second) backfilling with electrically conductive Material in turn a trench with now moderate aspect ratio. Another embodiment sees Therefore, before, as an alternative to the previous embodiment here now for this second backfilling amorphous or polycrystalline silicon doped with either phosphor alone or only with arsenic. Due to the low aspect ratio the time advantage has a stronger effect here. The migration of holes provides in contrast, due to the non-existent capacitor dielectric in the upper area only a small problem dar. It comes in particular Phosphorus as a dopant into consideration.

One Another advantage of the invention is that in the case of trench capacitors due to the reduced migration of the holes to the trench walls an essential larger thermal Budget for the post-processing available stands. Because the production of the electrically conductive trench filling in a relatively early one Stage of manufacturing a memory chip is performed open thus for a variety of succession processes the possibility, even at higher temperatures to be able to produce critical structure widths.

The Invention will now be described with reference to an embodiment with the aid of a Drawing closer explained become. Show:

1 - 8th in cross-sectional profiles steps of producing an electrically conductive filling in a trench capacitor according to an embodiment of the invention;

9 - 10 a representation of the problem of migration of holes (voids) according to the prior art.

An embodiment of the inventive method for producing an electrically conductive trench filling is based on a sequence of steps in cross-sectional profiles in the 1 - 8th shown. The cross-sectional profiles show the formation of a trench with electrically conductive filling concerning a trench capacitor.

1 shows the provided semiconductor substrate 10 (monocrystalline silicon), in which a trench 18 (Deep Trench) is formed. The ditch 18 becomes in the silicon substrate according to this embodiment 10 Based on an etching mask comprehensive send a layer 12 etched from silicon nitride. The layer 12 is thereby opened in a photolithographic process with exposure of a resist layer and subsequent development process at the location of the trench to be created. The layer 12 Silicon nitride usually lies on an oxidation layer 14 on the semiconductor substrate 10 on. A buried spiked area 16 is in a lower area of the trench 18 formed in which in advance a glass layer with a dopant in the trench 18 deposited and then this dopant is diffused out. It may be borosilicate glass or arsenic glass, etc.

2 shows the state after the glass layer is removed and a so-called NOLA layer 20 (NOLA: "Non-Conformal Liner by ALD") The NOLA deposition is for example in the publication EP 1,525,610 Al by Infineon Technologies AG, Munich. The details presented in the publication are referred to in this document. The NOLA deposition involves CVD (Atomic Layer Deposition) deposition using process gases TMA and H ₂ O. The process result is the formation of an Al ₂ O ₃ layer in the upper part of the trench. Typically, the layers are thick in the range of 5-12 nm. The NOLA layer 20 extends only into the upper part of the trench, the lower part of the trench 18 is on its sidewalls free from any layer.

The NOLA process is used to widen the lower part of the trench 18 , The expansion causes an increase in the diameter and thus the surface within the trench. The capacity of the capacitor is thus advantageously increased. As a further supporting measure (not in 2 shown) may be the surface on the sidewalls within the trench 18 be increased by formation of an HSG (Hemispherical Silicon Grain) layer. These measures are taken in particular when, due to the structural reduction, the trench width in the upper region is only 90 nm, or in particular only 70 nm. An enlargement of the depth of the trench capacitor for surface enlargement with an increase in the aspect ratio is only possible to a limited extent in these technology stages.

3 shows the result of the etching process in the silicon substrate at the trench inner walls, where the trench of the trench capacitor is bottle-shaped.

4 shows the state after removal of the NOLA layer 20 ,

As in 5 is then a layer of a thin dielectric 22 applied as a capacitor dielectric. Al ₂ O _{3 is} used in the technology stages considered here, in particular 70 nm.

After these process steps, the semiconductor substrate is now fed to a (LP) CVD reactor. As in 6 is shown, in a first deposition step, amorphous silicon having a layer thickness of about 20 nm in the trench is formed therein 18 deposited. This layer can be doped or undoped. In the application example, it is doped with phosphorus. The ditch 18 is thus not yet completely filled. In the next step, the assignment of this doped layer with AsH ₃ takes place, typical occupancy times are 30-60 minutes. In the next step, the gases SiH ₄ and phosphine gas (PH ₃ ) are simultaneously fed for the deposition of doped amorphous or polycrystalline silicon. Then the second arsenic occupancy can take place exactly as described above. Finally, the capacitor trench is completely filled with a phosphorus doped amorphous or polycrystalline silicon layer as in 7 as a layer 30b shown. The process parameters for this deposition essentially include temperature, pressure and gas flows. The respective usable range of parameter values extends according to this example for the individual parameters:
Temperature: 500-650 ° C
Pressure: 0.5-600 Torr corresponding to 66.661 Pa-79993.4 Pa
SiH ₄ : 100-500 sccm
AsH ₄ and PH3: 30-300 sccm
H ₂ : 0.5-20 slm

The specified process parameters are related to systems Batch processing, typically in a LPCVD (LowPressure CVD) Mode as well as CVD processes in a single-disk system, to the subatmospheric Pressure range can work.

The grown in the first and second deposition step layer 24 of poly-silicon is thus homogeneously doped with phosphorus. A first share 30a the electrically conductive trench filling is completed, which is a surface 26 having.

After reaching the mentioned layer thickness of the layer 24 the supply of gases for the deposition of poly-silicon and phosphorus is stopped, and a change of the device parameters made. It is now fed to Arsingas (AsH ₃ ), resulting in a monolayer, or several monolayers, of arsenic on the surface 26 deposit (reference numeral 28 ).

As in 7 is shown, is then changed back to the deposition of poly-silicon doped with phosphorus. The further doping with arsenic can be carried out as indicated above, but it is also possible in principle to dispense with this additional arsenic doping. This depends on the layer thicknesses with which the deposition steps for the poly-silicon with the phosphor are carried out in each case in relation to the trench width, here 70 nm. The trench 18 is now filled and the monolayers with the arsenic are equal to a digital doping profile in the midst of the doped with phosphorus amorphous or polycrystalline silicon layer.

8th describes the condition after etch back of the conductive trench fill in the trench 18 to above the buried doping area 16 , In this moderate thermal process, the incorporation of the arsenic atoms into the poly-silicon lattice already takes place. However, a completely homogeneous distribution and charge carrier activation is only achieved in subsequent high-temperature steps. The electrically conductive trench filling 30 now includes the fillings created in the partial steps 30a . 30b as well as the monolayers 28 , As mentioned, by taking into account smaller layer thicknesses for the poly-silicon deposition far more partial fillings 30a . 30b alternating with monolayers 28 be set up.

The trench capacitor 34 comprising a first capacitor electrode as a buried doping region 16 , a capacitor dielectric as a dielectric layer 22 and a second capacitor electrode as an electrically conductive trench filling 30 is thus formed.

Connection of the trench capacitor to a selection transistor is made possible by further conformally depositing an insulating layer to form an isolation collar. This can be alternately doped with another electrically conductive trench filling made of amorphous or polycrystalline silicon with phosphorus and arsenic or with one doped with either phosphorus or arsenic. Further details of the trench connection depend on whether a planar or a vertical selection transistor is desired.

The Training the selection transistors and their positioning is done again according to the state of the technique. The formation of the trench capacitor according to the invention is to none of the specific embodiments but limited by vertical or planar selection transistors rather generally applicable. A particularly advantageous effect achieves the method according to the invention applied to trench capacitors with widths of 70 nm or less. At the high aspect ratios became found that the digital doping profile of arsenic far out is less homogenized and more and more as an uncertainty factor Beech beats. Since the layer thicknesses of the poly-silicon are not chosen arbitrarily small can, Therefore, it may be easier to create a digital "stage" for arsenic possibly is not used and therefore the degree of doping considerably undercut becomes. This is compensated by the combination with phosphorus.

simultaneously is the migration of holes on Reason of the addition of phosphorus by the arsenic effectively prevents which especially in the case of surface enlargement, for example by NOLA or HSG stronger would hit, because the holes occupy a larger surface area at the same size, especially with the HSG application.

The problem of void migration is in the 9 and 10 shown. A layer of poly-silicon 30 ' , which is doped according to the prior art only with phosphorus, is in the trench 18 been separated. Along the longitudinal axis of the trench 18 An irregular hole forms 32 where the growing layers meet, and the holes can no longer be filled. 10 shows the state after application of a subsequent thermal annealing and / or oxidation process, structure-changing plasma etching or a later aluminum deposition. The irregular hole structure 32 splits and wanders as a multitude of holes 33 (Voids) towards the trench inner wall of the trench 18 out. There they are deposited on the capacitor dielectric 22 at. The surface of the dielectric is thereby disadvantageously reduced, while at the same time at the edges of the voids 33 such field peaks affecting the function of the trench capacitor arise. As mentioned, by the inventive method and the trench capacitor according to the invention in the 9 and 10 fixed effects shown or at least reduced.

10

Semiconductor substrate

12

silicon nitride

14

oxidation layer

16

buried doping

18

dig

20

NOLA layer

22

dielectric layer, Al ₂ O ₃

24

amorphous or polycrystalline silicon layer

26

surface

28

Monolayer (n) from arsenic

30a, b

part fillings trenching with amorphous and polycrystalline silicon doped with phosphorus

30

electrical conductive trench filling, doped with phosphorus and arsenic

30 '

electrical conductive trench filling, endowed exclusively with phosphorus

32

hole structure after deposition of amorphous or polycrystalline silicon

33

Holes, voids, migrated to trench inner wall

Claims (13)

Process for producing an electrically conductive filling ( 30 ) in a ditch ( 18 ), which in a semiconductor substrate ( 10 ) or in a layer on the semiconductor substrate, comprising the steps of: - providing the semiconductor substrate ( 10 ) with the ditch ( 18 ) and - depositing the substances amorphous or polycrystalline silicon, arsenic and phosphorus to form the electrically conductive filling ( 30 ) in the trench ( 18 ), wherein - the deposition of amorphous or polycrystalline silicon and the deposition of phosphorus are performed simultaneously, - the deposition of arsenic is carried out separately from the deposition of amorphous or polycrystalline silicon and phosphorus, and - the deposition of arsenic the formation of at least one monolayer ( 28 ) of arsenic atoms on a surface formed by the amorphous or polycrystalline silicon and the phosphorus. Method according to claim 1, wherein the trench ( 18 ) having an aspect ratio of a depth to a width of more than 10: 1. Method according to claim 1, wherein the trench ( 18 ) having an aspect ratio of a depth to a width of more than 50: 1. Method according to one of claims 1 to 3, wherein the trench is formed with a width of less than 75 nm. Method according to one of claims 1 to 4, wherein prior to the deposition of amorphous or polycrystalline silicon and phosphorus, a dielectric layer ( 22 ) in the trench ( 18 ) is deposited to form a capacitor dielectric so that the electrically conductive filling ( 30 ) in the trench ( 18 ) forms a capacitor electrode in a trench capacitor after deposition. Method according to one of claims 1 to 5, wherein after the deposition of arsenic, a thermal process step on the semiconductor substrate ( 10 ) is carried out so that arsenic atoms diffuse out into the amorphous or polycrystalline silicon. Method according to one of claims 1 to 6, wherein the steps simultaneous deposition of amorphous or polycrystalline silicon and phosphorus and deposition of arsenic in an alternating manner be repeated at least once. Trench capacitor in a semiconductor substrate with - a trench ( 18 ) in the semiconductor substrate ( 10 ), - a first capacitor electrode passing through a buried doped region ( 16 ) in the semiconductor substrate on the inner wall of the trench ( 18 ) is formed, - a capacitor dielectric, which through a dielectric layer ( 22 ) on an inner wall of the trench ( 18 ), and - at least in a lower portion of the trench ( 18 ) arranged second capacitor electrode by an electrically conductive trench filling ( 30 ) of a) amorphous or polycrystalline silicon, b) phosphorus and c) arsenic, wherein in the trench filling ( 30 ) the phosphor is homogeneous and the arsenic is inhomogeneously distributed between the amorphous or polycrystalline silicon. Trench capacitor according to claim 8, wherein an upper portion of the trench ( 18 ) by an insulation collar of the semiconductor substrate ( 10 ) is isolated. Trench capacitor according to claim 9, wherein in the upper portion of the trench ( 18 ), laterally enclosed by the insulation collar, an electrically conductive trench filling ( 30 ) comprising a) amorphous or polycrystalline silicon and b) phosphorus. Trench capacitor according to claim 9, wherein in the upper portion of the trench ( 18 ), laterally enclosed by the insulation collar, an electrically conductive trench filling ( 30 ) comprising a) amorphous or polycrystalline silicon and b) arsenic. Trench capacitor according to claim 9, wherein in the upper portion of the trench ( 18 ), laterally enclosed by the insulation collar, an electrically conductive trench filling ( 30 ) comprising a) amorphous or polycrystalline silicon, b) phosphorus and c) arsenic. Trench capacitor according to one of claims 8 to 12, wherein the trench ( 18 ) has an inner wall provided with an HSG (Hemispherical Silicon Grain) structure for surface enlargement.