DE102006006825A1 - Semiconductor component e.g. ball grid array semiconductor component, has semiconductor chip with protective casing, and soldering ball arranged in recess of electrical insulating layer and connected with connecting carrier - Google Patents

Semiconductor component e.g. ball grid array semiconductor component, has semiconductor chip with protective casing, and soldering ball arranged in recess of electrical insulating layer and connected with connecting carrier Download PDF

Info

Publication number
DE102006006825A1
DE102006006825A1 DE102006006825A DE102006006825A DE102006006825A1 DE 102006006825 A1 DE102006006825 A1 DE 102006006825A1 DE 102006006825 A DE102006006825 A DE 102006006825A DE 102006006825 A DE102006006825 A DE 102006006825A DE 102006006825 A1 DE102006006825 A1 DE 102006006825A1
Authority
DE
Germany
Prior art keywords
semiconductor chip
electrically conductive
connection carrier
conductive elements
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102006006825A
Other languages
German (de)
Inventor
Soo Gil Park
Kenneth Rebibis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102006006825A priority Critical patent/DE102006006825A1/en
Publication of DE102006006825A1 publication Critical patent/DE102006006825A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Component has a semiconductor chip (401) with a protective casing (406) and a contact surface (409). An electrically conducting connecting carrier (402) consists of a contact finger, which is arranged corresponding to the contact surface. Electrically conducting units (403) are arranged between the contact finger and the contact surface, and are made of polymer or resin. An electrically insulating layer with a recess is superimposed on the carrier. A soldering ball (405) is arranged in the recess and is connected with the carrier, where the layer is made of glass fiber reinforced resin. An independent claim is also included for a method for manufacturing a semiconductor component.

Description

Die Erfindung betrifft ein Halbleiterbauelement und ein Verfahren zum Herstellen eines Halbleiterbauelements.The The invention relates to a semiconductor device and a method for Producing a semiconductor device.

Zur Kontaktierung von Halbleiterchips in Halbleiterbauelementen werden Halbleiterchips mit Hilfe von Bonddrähten auf einen Verbindungsträger, beispielsweise einem Lead Frame montiert.to Contacting of semiconductor chips in semiconductor devices are Semiconductor chips by means of bonding wires on a connection carrier, for example mounted on a lead frame.

Ein üblicher Aufbau eines solchen Halbleiterbauelementes mit einem Lead Frame ist in 1 gezeigt. Der Halbleiterchip 101 und der Lead Frame 102 sind in einem Halbleiterchip-Gehäuse 105 angeordnet. Der Lead Frame 102 verläuft vom Inneren des Gehäuses 105 nach außen in Form von metallischen Anschlussstiften 106, die sich an den Seiten des Halbleiterchip-Gehäuses 105 befinden. Das Drahtbonden des Halbleiterchips mit dem Lead Frame muss für jede Kontaktfläche des Halbleiterchips separat durchgeführt werden.A common structure of such a semiconductor device with a lead frame is shown in FIG 1 shown. The semiconductor chip 101 and the lead frame 102 are in a semiconductor chip package 105 arranged. The lead frame 102 runs from the inside of the case 105 to the outside in the form of metallic pins 106 located on the sides of the semiconductor chip housing 105 are located. The wire bonding of the semiconductor chip to the lead frame must be performed separately for each contact surface of the semiconductor chip.

Die zunehmende Miniaturisierung und Integration von Halbleiterbauelementen führt sowohl zu verkleinerten Gehäusebauformen sowie einer steigenden Funktionalität, was häufig eine steigende Anzahl von Anschlusskontakten bedingt. Deshalb ist es bei hochintegrierten Halbleiterbauelementen nicht länger möglich, alle Anschlusskontakte an den Seiten des Gehäuses anzuordnen, was zur Bildung des sogenannten BGA-Standards (Ball Grid Array) führte.The increasing miniaturization and integration of semiconductor devices leads both to reduced housing types as well as increasing functionality, which is often an increasing number conditioned by contacts. That is why it is highly integrated Semiconductor devices no longer possible, to arrange all the terminals on the sides of the housing, resulting in formation the so-called BGA standard (Ball Grid Array).

Bei einem BGA-Halbleiterbauelement erfolgt die Kontaktierung mittels Lotkugeln, die in einem Raster, dem Ball Grid Array, unterhalb des Halbleiterbauelementes angeordnet sind. Die weiter fortschreitende Miniaturisierung führte zur Entwicklung des FBGA- oder FPBGA-Standards (Fine Pitch Ball Grid Ar ray) mit einem noch feineren Raster der Lotkugeln. Die vorliegende Erfindung schließt FBGA- und FPBGA-Halbleiterbauelemente als Untergruppe von BGA-Halbleiterbauelementen ein.at a BGA semiconductor device contacting takes place by means of Lotkugeln, in a grid, the ball grid array, below the Semiconductor component are arranged. The progressing Miniaturization led for the development of the FBGA or FPBGA standard (Fine Pitch Ball Grid Ar ray) with an even finer grid of solder balls. The present Invention includes FBGA and FPBGA semiconductor devices as a subset of BGA semiconductor devices one.

Der Aufbau eines herkömmlichen BGA-Halbleiterbauelements 200 ist in 2 gezeigt. Ein Halbleiterchip 201 ist mit seiner aktiven Seite nach oben auf einem Substrat 202 aufgebracht und mittels Drahtbondverbindungen 203 elektrisch mit dem Substrat 202 verbunden. Das Substrat 202 ist hinsichtlich Material und Aufbau einer mehrlagigen Leiterplatte ähnlich, jedoch sind die Außenabmessungen und die in dem Substrat 202 gebildeten Strukturen wesentlich kleiner. Die Unterseite des Substrates 202 enthält Kontaktflächen, auf denen die Lotkugeln 204 angeordnet sind. Der Halbleiterchip 201 ist in einem Gehäuse 205 angeordnet, welches auf einer Seite durch das Substrat 202 begrenzt wird.The structure of a conventional BGA semiconductor device 200 is in 2 shown. A semiconductor chip 201 is with its active side up on a substrate 202 applied and by wire bonds 203 electrically with the substrate 202 connected. The substrate 202 is similar in material and construction to a multilayer printed circuit board, but the external dimensions and those in the substrate are similar 202 formed structures much smaller. The underside of the substrate 202 contains contact surfaces on which the solder balls 204 are arranged. The semiconductor chip 201 is in a housing 205 arranged on one side by the substrate 202 is limited.

3 zeigt den Aufbau eines anderen herkömmlichen BGA-Halbleiterbauelements 300, wobei der Halbleiterchip 301 mit seiner aktiven Seite nach unten mittels Lotbumps 303 elektrisch und mechanisch mit dem Substrat 302 verbunden ist. Die Unterseite des Substrates 302 enthält Kontaktflächen, auf denen Lotkugeln 304 angeordnet sind. Der Halbleiterchip 301 ist in einem Gehäuse 305 angeordnet, welches auf einer Seite durch das Substrat 302 begrenzt wird. 3 shows the structure of another conventional BGA semiconductor device 300 , wherein the semiconductor chip 301 with its active side down using solder bumps 303 electrically and mechanically with the substrate 302 connected is. The underside of the substrate 302 contains contact surfaces on which solder balls 304 are arranged. The semiconductor chip 301 is in a housing 305 arranged on one side by the substrate 302 is limited.

Die Halbleiterbauelemente 200, 300 gemäß 2 und 3 haben unter anderem den Nachteil, dass das Substrat, hergestellt aus glasfaserverstärktem Kunstharz und der Halbleiterchip (aus Silizium) ein stark unterschiedliches thermisches Ausdehnungsverhalten haben, was zu mechanischen Spannungen und damit zu Zuverlässigkeitsproblemen bei den gebildeten Halbleiterbauelementen 200, 300 führt. Zudem stellen die relativ hohen Materialkosten des Substrates 202, 302 einen erheblichen Anteil der Gesamtkosten der Halbleiterbauelemente 200, 300 dar.The semiconductor devices 200 . 300 according to 2 and 3 have, inter alia, the disadvantage that the substrate, made of glass-fiber reinforced synthetic resin and the semiconductor chip (made of silicon) have a very different thermal expansion behavior, resulting in mechanical stresses and thus reliability problems in the semiconductor devices formed 200 . 300 leads. In addition, the relatively high material costs of the substrate 202 . 302 a significant proportion of the total cost of the semiconductor devices 200 . 300 represents.

Der Erfindung liegt das Problem zugrunde, ein zuverlässiges und zugleich kostengünstiges Halbleiterbauelement zu schaffen.Of the The invention is based on the problem of a reliable and cost-effective semiconductor device to accomplish.

Das Problem wird durch das Halbleiterbauelement sowie durch das Verfahren zum Herstellen eines Halbleiterbauelements mit den Merkmalen gemäß den unabhängigen Patentansprüchen gelöst. Beispielhafte Ausgestaltungen der Erfindung ergeben sich aus den abhängigen Ansprüchen. Die Ausgestaltungen der Erfindung gelten sowohl für das Halbleiterbauelement als auch, für das Verfahren zum Herstellen eines Halbleiterbauelements.The Problem is caused by the semiconductor device as well as by the method for producing a semiconductor device having the features according to the independent patent claims. exemplary Embodiments of the invention will become apparent from the dependent claims. The Embodiments of the invention apply to both the semiconductor device as well, for the method of manufacturing a semiconductor device.

Ein Halbleiterbauelement weist mindestens einen Halbleiterchip auf, welcher Kontaktflächen aufweist, die in einem vorgegebenen geometrischen Raster auf dem Halbleiterchip angeordnet sind. Das Halbleiterbauelement weist einen elektrisch leitfähigen Verbindungsträger auf mit Kontaktfingern, die entsprechend dem geometrischen Raster der Kontaktflächen des Halbleiterchips angeordnet sind, sowie mehrere elektrisch leitfähige Elemente, die zwischen einem Kontaktfinger des Verbindungsträgers und einer Kontaktfläche des Halbleiterchips angeordnet sind und eine elektrische Verbindung herstellen. Auf dem Verbindungsträger ist eine elektrisch isolierende Schicht mit Durchbrüchen angebracht, die zur Aufnahme von Lotkugeln dienen, wobei die Lotkugeln mit dem Verbindungsträger elektrisch leitend verbunden sind. Ferner weist das Halbleiterbauelement eine Schutz-Umhüllung des Halbleiterchips auf, wobei das Gehäuse des Halbleiterbauelementes auf einer Seite durch die elektrisch isolierende Schicht mit den Lotkugeln begrenzt wird.One Semiconductor device has at least one semiconductor chip, which contact surfaces which, in a given geometric grid on the Semiconductor chip are arranged. The semiconductor device has a electrically conductive connection support on with contact fingers, which correspond to the geometric grid the contact surfaces the semiconductor chip are arranged, as well as a plurality of electrically conductive elements, between a contact finger of the connection carrier and a contact surface of the semiconductor chip are arranged and an electrical connection produce. On the connection carrier is an electrically insulating Layer with breakthroughs attached, which serve to receive solder balls, wherein the solder balls with the connection carrier are electrically connected. Further, the semiconductor device a protective cladding of the semiconductor chip, wherein the housing of the semiconductor component on one side through the electrically insulating layer with the Solder balls is limited.

Ein Aspekt der Erfindung gem. 4 kann darin gesehen werden, dass ein leitfähiger Verbindungsträger 402 vorgesehen ist, welcher einerseits direkt mit einem oder mehreren Halbleiterchips 401 gekoppelt ist und andererseits mit Lotkugeln 405 verbunden ist, welche in Durchbrüchen einer auf dem Verbindungsträger angeordneten elektrisch isolierenden Schicht 404 angeordnet sind, damit das Halbleiterbauelement mittels dieser Lotkugeln beispielsweise auf einer übergeordneten Leiterplatte montiert werden kann.An aspect of the invention gem. 4 can be seen in that a conductive connection carrier 402 is provided, which on the one hand directly with one or more semiconductor chips 401 coupled and on the other hand with solder balls 405 which is connected in openings of an electrically insulating layer arranged on the connection carrier 404 are arranged so that the semiconductor device can be mounted by means of these solder balls, for example, on a parent circuit board.

Gemäß einem Aspekt der Erfindung kann ein Vorteil gegenüber dem 1 dargestellten Halbleiterbauelement darin gesehen werden, dass die Erfindung wegen des BGA Anschluss-Schemas für hochintegrierte Halbleiterbauelemente 200, 300, wie sie beispielsweise in 2 oder 3 dargestellt sind, verwendet werden kann. Dabei wird das kostenintensive Substrat durch einen Verbindungsträger ersetzt.According to one aspect of the invention, an advantage over the 1 be seen that the invention because of the BGA connection scheme for highly integrated semiconductor devices 200 . 300 as they are for example in 2 or 3 are shown, can be used. The cost-intensive substrate is replaced by a connection carrier.

Gemäß einem Teil-Aspekt der Erfindung kann zudem das sequentielle und damit zeitintensive Drahtbonden gegenüber den in 2 und 3 dargestellten Halbleiterbauelementen durch einen Verfahren ersetzt werden, bei welchem alle Verbindungen zwischen Halbleiterchip und Verbindungsträger in wenigen Fertigungsschritten parallel hergestellt werden.In addition, according to a part aspect of the invention, the sequential and thus time-consuming wire bonding can be compared with those in 2 and 3 can be replaced by a method in which all connections between the semiconductor chip and the connection carrier are made in parallel in a few manufacturing steps.

Der Halbleiterchip kann ein Speicherchip oder ein anderer" Halbleiterchip sein. Als Speicherchip kommen grundsätzlich alle Halbleiterspeicher in Frage, z.B. Dynamic-RAM (DRAM), Flash-RRM, Conducting-bridge-RAM (CBRAM), Magnetic-RAM (MRAM), Ferroelektric-RAM (FeRAM), Phase-change-RAM (PCRAM).Of the Semiconductor chip may be a memory chip or another "semiconductor chip. As a memory chip come in principle all semiconductor memories in question, e.g. Dynamic RAM (DRAM), Flash RRM, Conducting Bridge RAM (CBRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), Phase-change RAM (PCRAM).

Es können mehrere gleichartige oder unterschiedliche Halbleiterchips nebeneinander auf einem Verbindungsträger und somit in einem Halbleiterbauelement angeordnet werden.It can several similar or different semiconductor chips next to each other on a connection carrier and thus be arranged in a semiconductor device.

Die elektrisch leitfähigen Elemente haben die Aufgabe, eine elektrische Verbindungen zwischen den Kontaktflächen des Halbleiterchips und dem Verbindungsträger herzustellen und zugleich einen bestimmten Abstand zwischen Halbleiterchip und Verbindungsträger zu gewährleisten, der notwendig ist, damit der Raum zwischen Halbleiterchip und Verbindungsträger später vollständig mit Pressmasse für die Schutz-Umhüllung gefüllt werden kann. Auf dem Halbleiterchip können weitere elektrisch leitfähige Elemente angeordnet sein, die allein für die Abstandshaltung zwischen Halbleiterchip und Verbindungsträger bestimmt sind, beispielsweise an den Außenkanten des Halbleiterchips.The electrically conductive Elements have the task of making electrical connections between the contact surfaces of the semiconductor chip and the connection carrier and at the same time to ensure a certain distance between the semiconductor chip and the connection carrier, which is necessary so that the space between the semiconductor chip and connecting carrier later completely with Press mass for the protection cladding filled can be. On the semiconductor chip can be further electrically conductive elements be arranged alone for determines the distance between the semiconductor chip and connection carrier are, for example, on the outer edges of the semiconductor chip.

Die elektrisch leitfähigen Elemente können aus Metall hergestellt werden. Beispielsweise können sie aus Gold (Au), Kupfer (Cu), Silber (Ag) oder Aluminium (Al) oder einer Legierung bestehen, die überwiegend eines der genannten Metalle enthält.The electrically conductive Elements can be out Metal to be made. For example, they can be made of gold (Au), copper (Cu), silver (Ag) or aluminum (Al) or an alloy, the predominantly contains one of the metals mentioned.

Die elektrisch leitfähigen Elemente können, sofern sie aus Metall bestehen, auf dem Halbleiterchip gebildet werden, indem auf den Kontaktflächen des Halbleiterchips Bondkontakte mittels Drahtbonden hergestellt werden und der Bonddraht am Bondkontakt abgetrennt wird. Dieses Verfahren kann für eine Kontaktfläche des Halbleiterchips mehrfach wiederholt werden, so dass mehrere Bondkontakte übereinander erzeugt werden.The electrically conductive Elements can, provided they are made of metal, are formed on the semiconductor chip, on the contact surfaces of the Semiconductor chips Bond contacts are produced by wire bonding and the bonding wire is cut off at the bonding contact. This method can for one contact area of the semiconductor chip are repeated several times, so that several Bond contacts one above the other be generated.

Ein weiteres Verfahren zur Herstellung der elektrisch leitfähigen Elemente besteht in folgenden Schritten:

  • – ganzflächiges Aufbringen einer dünnen metallischen Schicht, z.B. mittels Zerstäubung (PVD) oder Abscheidung aus der Gasphase (CVD),
  • – Strukturierung der dünnen metallischen Schicht durch photolithografische Schritte (Aufbringen, Belichten und Entwickeln von Photolack) und nachfolgendes Ätzen; z.B. Plasma-Ätzen oder Nass-Ätzen und anschließende Entfernung des Photolackes
  • – Aufbringen eines Metalls, beispielsweise mittels elektrogalvanischer Abscheidung bis zur gewünschten Größe der elektrisch leitfähigen Elemente.
Another method for producing the electrically conductive elements consists of the following steps:
  • Full-surface application of a thin metallic layer, eg by means of sputtering (PVD) or vapor deposition (CVD),
  • - structuring of the thin metallic layer by photolithographic steps (application, exposure and development of photoresist) and subsequent etching; eg plasma etching or wet etching and subsequent removal of the photoresist
  • - Applying a metal, for example by means of electro-galvanic deposition to the desired size of the electrically conductive elements.

In einer anderen Ausgestaltung der Erfindung können die elektrisch leitfähigen Elemente aus einem leitfähigen Kunstharz oder leitfähigem Polymer gebildet sein. Zum Erreichen der geforderten Leitfähigkeit ist der Kunstharz oder Polymer durchgängig, also im vollen Volumen, mit leitfähigen Partikeln angereichert.In In another embodiment of the invention, the electrically conductive elements from a conductive Synthetic resin or conductive Polymer be formed. To achieve the required conductivity is the synthetic resin or polymer throughout, ie in full volume, with conductive Enriched particles.

Diese elektrisch leitfähigen Elemente können aus elektrisch leitfähigem Kunstharz oder elektrisch leitfähigem Polymer mittels Schablonen-Siebruckverfahren oder im Dispersionsverfahren aufgebracht werden. Anschließend werden die aufgebrachten Strukturen verfestigt, beispielsweise durch eine Wärmebehandlung oder ultraviolettes Licht.These electrically conductive Elements can made of electrically conductive Synthetic resin or electrically conductive Polymer by stencil screen printing or in the dispersion process be applied. Subsequently the applied structures are solidified, for example by a heat treatment or ultraviolet light.

Ein weiteres Verfahren zur Herstellung der elektrisch leitfähigen Elemente besteht in folgenden Schritten:

  • – ganzflächiges Aufbringen einer Folie aus leitfähigem Kunststoff oder leitfähigem Polymer auf die Oberfläche des Halbleiterchips
  • – Strukturierung der leitfähigen Folie durch photolithografische Schritte (Aufbringen, Belichten und Entwickeln von Photolack) und nachfolgendes Ätzen; z.B. Plasma-Ätzen oder Nass-Ätzen
Another method for producing the electrically conductive elements consists of the following steps:
  • - Full-surface application of a film of conductive plastic or conductive polymer on the surface of the semiconductor chip
  • - structuring of the conductive film by photolithographic steps (application, exposure and development of photoresist) and subsequent etching; eg plasma etching or wet etching

Gemäß einer Ausgestaltung der Erfindung ist der elektrisch leitfähige Verbindungsträger aus Metall gebildet.According to one embodiment of the invention, the electrically conductive connection carrier is made Metal formed.

Als Metall kommen in Frage vorzugsweise Silber (Ag), Kupfer (Cu) oder Aluminium (Al) oder einer Legierung, die überwiegend eines der genannten Metalle enthält.When Metal are preferably silver (Ag), copper (Cu) or Aluminum (Al) or an alloy that is predominantly one of the metals mentioned contains.

Das thermische Ausdehnungsverhalten der Kombination von Halbleiterchip und metallischem Verbindungsträger ist wesentlich günstiger als das Ausdehnungsverhalten der Kombination von Halbleiterchip und Substrat gemäß dem Stand der Technik, was zu einer verbesserten Zuverlässigkeit des Halbleiterbauelementes führt.The thermal expansion behavior of the combination of semiconductor chip and metallic connection carrier is much cheaper as the expansion behavior of the combination of semiconductor chip and substrate according to the state technology, resulting in improved reliability of the semiconductor device leads.

Der Verbindungsträger wird als ein vorgefertigtes Teil für die Montage des Halbleiterbauelementes verwendet.Of the connection support is considered a prefabricated part for the mounting of the semiconductor device used.

Die Kontaktierung zwischen dem Verbindungsträger und den elektrisch leitfähigen Elementen, soweit diese aus Metall bestehen, erfolgt mittels Ultraschall-Bonden.The Contacting between the connection carrier and the electrically conductive elements, if they are made of metal, takes place by means of ultrasonic bonding.

Die Kontaktierung zwischen dem Verbindungsträger und den elektrisch leitfähigen Elementen, soweit diese aus leitfähi gem Kunststoff oder leitfähigem Polymer bestehen, erfolgt mittels elektrisch leitfähigem Kleber.The Contacting between the connection carrier and the electrically conductive elements, insofar as they are made of conductive material Plastic or conductive Polymer exist, by means of electrically conductive adhesive.

Gemäß einer Ausgestaltung der Erfindung kann die elektrisch isolierende Schicht aus Kunstharz gebildet sein.According to one Embodiment of the invention, the electrically insulating layer be formed of synthetic resin.

Die elektrisch isolierende Schicht kann in folgenden Schritten hergestellt werden:

  • – ganzflächiges Aufbringen eines flüssigen Kunstharzes auf den Verbindungsträger, beispielsweise im Schleuder- oder Sprühverfahren und anschließendes dem Aushärten des Harzes
  • – Strukturierung der Harzschicht durch photolithografische Schritte (Aufbringen, Belichten und Entwickeln von Photolack) und nachfolgendes Ätzen; z.B. Plasma-Ätzen oder Nass-Ätzen und anschließende Entfernung des Photolackes
The electrically insulating layer can be produced in the following steps:
  • - Whole-area application of a liquid synthetic resin on the connection carrier, for example in the spin or spray process and then the curing of the resin
  • - structuring of the resin layer by photolithographic steps (application, exposure and development of photoresist) and subsequent etching; eg plasma etching or wet etching and subsequent removal of the photoresist

Die elektrisch isolierende Schicht kann in einer anderen Ausgestaltung der Erfindungsmeldung als ein vorgefertigtes Teil für die Montage des Halbleiterbauelementes verwendet werden, welches bereits die Durchbrüche für die Lotkugeln aufweist. In diesem Fall besteht die elektrisch isolierende Schicht aus Kunstharz, welches aus mechanischen Gründen mit Glasfasern verstärkt ist. Die elektrisch isolierende Schicht wird auf den Verbindungsträger durch Kleben aufgebracht.The electrically insulating layer may be in another embodiment the invention disclosure as a prefabricated part for assembly be used of the semiconductor device, which already the breakthroughs for the Having solder balls. In this case, there is the electrically insulating Layer of synthetic resin, which for mechanical reasons with Reinforced glass fibers is. The electrically insulating layer is passed through to the connection carrier Adhesive applied.

Dazu kann die elektrisch isolierende Schicht in der Vorfertigung einseitig mit einer klebenden Beschichtung versehen werden. Alternativ dazu kann zwischen der elektrisch isolierenden Schicht und dem Verbindungsträger eine Klebefolie verwendet werden.To the electrically insulating layer in the prefabrication can be one-sided be provided with an adhesive coating. Alternatively can between the electrically insulating layer and the connection carrier a Adhesive film can be used.

Gemäß einer anderen Ausgestaltung der Erfindung ist die Schutz-Umhüllung aus Epoxidharz-Pressmasse gebildet, die Füllstoffe zur Angleichung der thermischen Ausdehnungskoeffizienten zwischen Halbleiterchip und Epoxidharz-Pressmasse enthält.According to one Another embodiment of the invention, the protective enclosure is made Epoxy resin molding compound formed, the fillers to approximate the coefficient of thermal expansion between the semiconductor chip and Epoxy resin molding compound contains.

Ein Halbleiterbauelement wird gemäß einem Aspekt der Erfindung hergestellt, indem auf den Kontaktflächen des Halbleiterchips elektrisch leitfähige Elemente angeordnet werden und diese mit dem Verbindungsträger kontaktiert werden wird und die Anordnung von Halbleiterchip, elektrisch leitfähigen Elementen und Verbindungsträger mit einer Schutz-Umhüllung versehen wird, welche die Außenseite des Verbindungsträgers freilässt. Auf dieser Außenseite des Verbindungsträgers wird eine elektrisch isolierende Schicht aufgebracht, die Durchbrüche enthält, in denen Lotkugeln angeordnet und elektrisch leitend mit dem Verbindungsträger verbunden werden. Die Lotkugeln dienen der elektrischen und mechanischen Verbindung des Halbleiterbauelementes mit einem übergeordneten System, beispielsweise der Leiterplatte einer elektronischen Baugruppe.One Semiconductor device is according to one aspect produced by the invention on the contact surfaces of the Semiconductor chips electrically conductive elements be arranged and contacted with the connection carrier will be and the arrangement of semiconductor chip, electrically conductive elements and connecting carrier with a protective cladding which is the outside of the connection carrier leaves free. On this outside of the connecting beam an electrically insulating layer is applied which contains openings in which Lotkugeln arranged and electrically conductively connected to the connection carrier become. The solder balls serve the electrical and mechanical connection the semiconductor device with a higher-level system, for example the circuit board of an electronic module.

Die Herstellung eines Halbleiterbauelementes kann sowohl einzeln als auch im Verbund erfolgen. Bei Verbundfertigung sind Verbindungsträger und elektrisch isolierende Schicht sind so beschaffen, dass mehrere matrixartig nebeneinander angeordnete Halbleiterchips in einem Arbeitsgang jeweils gemeinsam bearbeitet werden und erst nach dem Herstellen der Schutz-Umhüllung, dem Aufbringen der elektrisch isolierenden Schicht und dem Anordnen der Lotkugeln in einzelne Halbleiterbauelemente vereinzelt werden.The Production of a semiconductor device may be both individually also in combination. In compound production are connection carrier and electrically insulating layer are such that several matrix-like juxtaposed semiconductor chips in one operation each be processed together and only after the manufacture the protection cladding that Applying the electrically insulating layer and arranging the solder balls are separated into individual semiconductor devices.

Ausführungsbeispiele der Erfindung sind in den Figuren dargestellt und werden im Folgenden näher erläutert. In den Figuren werden, soweit sinnvoll, gleiche oder ähnliche Elemente mit identischen Bezugszeichen versehen. Die Figuren sind schematisch und nicht unbedingt maßstabsgetreu.embodiments The invention are illustrated in the figures and will be explained in more detail below. In the characters are, as far as appropriate, the same or similar Elements provided with identical reference numerals. The figures are schematic and not necessarily true to scale.

Es zeigenIt demonstrate

1 eine Querschnittsansicht eines Halbleiterbauelements gemäß dem Stand der Technik; 1 a cross-sectional view of a semiconductor device according to the prior art;

2 eine Querschnittsansicht eines Halbleiterbauelements gemäß dem Stand der Technik; 2 a cross-sectional view of a semiconductor device according to the prior art;

3 eine Querschnittsansicht eines Halbleiterbauelements gemäß dem Stand der Technik; 3 a cross-sectional view of a semiconductor device according to the prior art;

4 eine Querschnittsansicht eines Halbleiterbauelements gemäß einem Ausführungsbeispiel der Erfindung; 4 a cross-sectional view of a half ladder element according to an embodiment of the invention;

5 bis 10 den Ablauf der Herstellung eines Halbleiterbauelementes gemäß einem Ausführungsbeispiel dieser Erfindung. 5 to 10 the sequence of manufacturing a semiconductor device according to an embodiment of this invention.

1 zeigt den Aufbau eines Halbleiterbauelementes 100 mit Lead Frame gemäß dem Stand der Technik. Ein Halbleiterchip 101 ist auf einem metallischen Lead Frame 102 aufgebracht. Die Kontaktflächen des Halbleiterchips 101 sind mittels Drahtbondverbindungen 103 mit den zugeordneten Kontaktfingern des Lead Frame 102 verbunden. Der Halbleiterchip 101 und der Lead Frame 102 sind in einem Halbleiterchip-Gehäuse 105 angeordnet. Der Lead Frame 102 verläuft vom Inneren des Gehäuses 105 nach außen in Form von metallischen Anschlussstiften 106, die sich an den Seiten des Halbleiterchip-Gehäuses 105 befinden. 1 shows the structure of a semiconductor device 100 with lead frame according to the prior art. A semiconductor chip 101 is on a metallic lead frame 102 applied. The contact surfaces of the semiconductor chip 101 are by wire bonds 103 with the associated contact fingers of the lead frame 102 connected. The semiconductor chip 101 and the lead frame 102 are in a semiconductor chip package 105 arranged. The lead frame 102 runs from the inside of the case 105 to the outside in the form of metallic pins 106 located on the sides of the semiconductor chip housing 105 are located.

2 zeigt der Aufbau eines BGA-Halbleiterbauelements 200 gemäß dem Stand der Technik. Ein Halbleiterchip 201 ist mit seiner aktiven Seite nach oben auf einem Substrat 202 aufgebracht und mittels Drahtbondverbindungen 203 elektrisch mit dem Substrat 202 verbunden. Die Unterseite des Substrates 202 enthält Kontaktflächen, auf denen die Lotkugeln 204 angeordnet sind. Der Halbleiterchip 201 ist in einem Gehäuse 205 angeordnet, welches auf einer Seite durch das Substrat 202 begrenzt wird. 2 shows the construction of a BGA semiconductor device 200 according to the prior art. A semiconductor chip 201 is with its active side up on a substrate 202 applied and by wire bonds 203 electrically with the substrate 202 connected. The underside of the substrate 202 contains contact surfaces on which the solder balls 204 are arranged. The semiconductor chip 201 is in a housing 205 arranged on one side by the substrate 202 is limited.

3 zeigt den Aufbau eines anderen BGA-Halbleiterbauelements 300 gemäß dem Stand der Technik. Der Halbleiterchip 301 ist mit seiner aktiven Seite nach unten mittels Lotbumps 303 elektrisch mit dem Substrat 302 verbunden. Die Unterseite des Substrates 302 enthält Kontaktflächen, auf denen Lotkugeln 304 angeordnet sind. Der Halbleiterchip 301 ist in einem Gehäuse 305 angeordnet, welches auf einer Seite durch das Substrat 302 begrenzt wird. 3 shows the construction of another BGA semiconductor device 300 according to the prior art. The semiconductor chip 301 is with its active side down using solder bumps 303 electrically with the substrate 302 connected. The underside of the substrate 302 contains contact surfaces on which solder balls 304 are arranged. The semiconductor chip 301 is in a housing 305 arranged on one side by the substrate 302 is limited.

4 zeigt ein Halbleiterbauelement 400 gemäß einem Ausführungsbeispiel der Erfindung. 4 shows a semiconductor device 400 according to an embodiment of the invention.

Das Halbleiterbauelement 400 weist mindestens einen Halbleiterchip 401 auf, der Kontaktflächen 409 aufweist, die in einem vorgegebenen geometrischen Raster auf dem Halbleiterchip 401 angeordnet sind. Die Kontaktflächen des Halbleiterchips 401 sind durch das Layout des Halbleiterchips 401 vorgegeben. Sie können jedoch alternativ mittels einer Umverdrahtungsebene 407, bestehend aus einer Kombination von Isolierschichten und strukturierten Leiterzügen, anders angeordnet werden.The semiconductor device 400 has at least one semiconductor chip 401 on, the contact surfaces 409 having, in a predetermined geometric grid on the semiconductor chip 401 are arranged. The contact surfaces of the semiconductor chip 401 are due to the layout of the semiconductor chip 401 specified. However, you can alternatively use a redistribution layer 407 consisting of a combination of insulating layers and structured conductor tracks, arranged differently.

Das Halbleiterbauelement 400 weist einen elektrisch leitfähigen Verbindungsträger 402 auf, wobei der Verbindungsträger 402 Kontaktfinger aufweist, die entsprechend dem geometrischen Raster der Kontaktflächen des Halbleiterchips 401 angeordnet sind, sowie mehrere elektrisch leitfähige Elemente 403, die zwischen einem Kontaktfinger des Verbindungsträgers 402 und einer Kontaktfläche des Halbleiterchips 401 angeordnet sind und eine elektrische Verbindung herstellen und/oder der Abstandshaltung zwischen Halbleiterchip 401 und Verbindungsträger 402 dienen. Auf dem Verbindungsträger 402 (anders ausgedrückt: auf der dem Halbleiterchip gegenüberliegenden Seite des Verbindungsträgers) ist eine elektrisch isolierende Schicht (auch bezeichnet als Isolierschicht) 404 mit Durchbrüchen 907 angebracht, die zur Aufnahme der Lotkugeln 405 dienen, wobei die Lotkugeln 405 mit dem Verbindungsträger 402 elektrisch leitend verbunden sind. Das Gehäuse des Halbleiterbauelementes 400 weist eine formschlüssige Schutz-Umhül lung 406 auf, wobei die Isolierschicht 404 mit den Lotkugeln 405 die Begrenzung des Halbleiterbauelementes 400 auf einer Seite darstellt.The semiconductor device 400 has an electrically conductive connection carrier 402 on, with the connection carrier 402 Contact finger, which corresponds to the geometric grid of the contact surfaces of the semiconductor chip 401 are arranged, and a plurality of electrically conductive elements 403 between a contact finger of the connection carrier 402 and a contact surface of the semiconductor chip 401 are arranged and establish an electrical connection and / or the spacing between the semiconductor chip 401 and connecting carrier 402 serve. On the connection carrier 402 (in other words, on the side opposite the semiconductor chip side of the connection carrier) is an electrically insulating layer (also referred to as insulating layer) 404 with breakthroughs 907 attached to the for receiving the solder balls 405 serve, with the solder balls 405 with the connection carrier 402 are electrically connected. The housing of the semiconductor device 400 has a positive protective Umhül development 406 on, with the insulating layer 404 with the solder balls 405 the limitation of the semiconductor device 400 represents on one side.

Die Lotkugeln 405 dienen der elektrischen und mechanischen Verbindung des Halbleiterbauelementes 400 mit einem übergeordneten System, beispielsweise der Leiterplatte einer elektronischen Baugruppe.The solder balls 405 serve the electrical and mechanical connection of the semiconductor device 400 with a higher-level system, for example the printed circuit board of an electronic module.

Die Herstellung eines Halbleiterbauelementes 400 kann auch im Verbund erfolgen: Verbindungsträger 402 und elektrisch isolierende Schicht 404 sind in diesem Fall so beschaffen, dass mehrere matrixartig nebeneinander angeordnete Halbleiterchips 401 in einem Arbeitsgang jeweils gemeinsam bearbeitet werden und erst nach dem Herstellen der Schutz-Umhüllung 406 in einzelne Halbleiterbauelemente 400 vereinzelt werden.The production of a semiconductor device 400 can also be done in combination: connection carrier 402 and electrically insulating layer 404 are in this case such that a plurality of semiconductor chips arranged next to one another in the form of a matrix 401 be processed together in one operation and only after the production of the protective cover 406 into individual semiconductor components 400 to be isolated.

5 zeigt einen Halbleiterchip 501 auf welchem direkt oder über eine Umverdrahtungsebene 502 die Kontaktflächen des Halbleiterchips angeordnet sind. 5 shows a semiconductor chip 501 on which directly or via a rewiring level 502 the contact surfaces of the semiconductor chip are arranged.

6 zeigt den Halbleiterchip 601 auf welchem direkt oder über eine Umverdrahtungsebene 602 elektrisch leitfähigen Elementen 603 auf den Kontaktflächen des Halbleiterchips 601 aufgebracht wurden. 6 shows the semiconductor chip 601 on which directly or via a rewiring level 602 electrically conductive elements 603 on the contact surfaces of the semiconductor chip 601 were applied.

7 zeigt den Halbleiterchip 701 mit der Umverdrahtungsebene 702 nach dem Aufbringen eines elektrisch leitfähigen Verbindungsträgers 704, der mit den elektrisch leitfähigen Elementen 703 kontaktiert wird. 7 shows the semiconductor chip 701 with the redistribution layer 702 after the application of an electrically conductive connection carrier 704 that with the electrically conductive elements 703 will be contacted.

Danach werden, wie in 8 dargestellt, der Halbleiterchip 801 mit der Umverdrahtungsebene 802, die elektrisch leitfähigen Elemente 803 und der Verbindungsträger 804 von einer Schutz-Umhüllung 805 eingeschlossen, wobei die vom Halbleiterchip abgewandte Seite des Verbindungsträgers 804 frei bleibt. Die Nachfolgend wird gemäß 9 auf die frei gebliebene Seite des Verbindungsträgers 904 der Anordnung des Halbleiterchips 901, der Umverdrahtungsebene 902, den elektrisch leitfähigen Elementen 903 und dem Verbindungsträger 904, eingeschlossen von der Schutz-Umhüllung 905, eine elektrisch isolierende Schicht 906 aufgebracht, in welche Durchbrüche 907 eingebracht werden. Alternative kann eine elektrisch isolierende Schicht 904 aufgebracht werden, die bereits Durchbrüche 907 enthält.After that, as in 8th shown, the semiconductor chip 801 with the redistribution layer 802 , the electrically conductive elements 803 and the connection carrier 804 from a shelter cladding 805 including, from the semiconductor chip opposite side of the connection carrier 804 remains free. The following is according to 9 on the free side of the connection carrier 904 the arrangement of the semiconductor chip 901 , the rewiring level 902 , the electrically conductive elements 903 and the connection carrier 904 Included from the shelter cladding 905 , an electrically insulating layer 906 applied, in which breakthroughs 907 be introduced. Alternative may be an electrically insulating layer 904 be applied, already breakthroughs 907 contains.

Danach werden gemäß 10 auf die Anordnung des Halbleiterchips 1001, der Umverdrahtungsebene 1002, den elektrisch leitfähigen Elementen 1003 und dem Verbindungsträger 1004, eingeschlossen von der Schutz-Umhüllung 1005, eine elektrisch isolierende Schicht 1006 aufgebracht, in deren Durchbrüchen 907 die Lotkugeln 1008 angeordnet und mit dem Verbindungsträger 1004 elektrisch kontaktiert werden.After that, according to 10 on the arrangement of the semiconductor chip 1001 , the rewiring level 1002 , the electrically conductive elements 1003 and the connection carrier 1004 Included from the shelter cladding 1005 , an electrically insulating layer 1006 applied, in their breakthroughs 907 the solder balls 1008 arranged and with the connection carrier 1004 be contacted electrically.

11

100100
Halbleiterbauelement mit VerbindungsträgerSemiconductor device with connection carrier
101101
HalbleiterchipSemiconductor chip
102102
Lead Framelead frame
103103
DrahtbondverbindungenWire bonds
104104
Verbindungsträger-KontaktfingerConnection carrier contact fingers
105105
Gehäusecasing
106106
Verbindungsträger-AnschlussstifteConnection support pins

22

200200
BGA-HalbleiterbauelementBGA semiconductor device
201201
HalbleiterchipSemiconductor chip
202202
Substratsubstratum
203203
DrahtbondverbindungenWire bonds
204204
Lotkugelnsolder balls
205205
Gehäusecasing

33

300300
BGA-HalbleiterbauelementBGA semiconductor device
301301
HalbleiterchipSemiconductor chip
302302
Substratsubstratum
303303
Lotbumpssolder bumps
304304
Lotkugelnsolder balls
305305
Gehäusecasing

44

400400
HalbleiterbauelementSemiconductor device
401401
HalbleiterchipSemiconductor chip
402402
Verbindungsträger-KontaktfingerConnection carrier contact fingers
403403
elektrisch leitfähige Elementeelectrical conductive elements
404404
elektrisch isolierende Schichtelectrical insulating layer
405405
Lotkugelnsolder balls
406406
Schutz-UmhüllungProtective sheath
407407
Passivierungsschicht oder Umverdrahtungsebenepassivation layer or redistribution level
409409
Kontaktflächen des HalbleiterchipsContact surfaces of the Semiconductor chips

55

501501
HalbleiterchipSemiconductor chip
502502
Passivierungsschicht oder Umverdrahtungsebenepassivation layer or redistribution level

66

601601
HalbleiterchipSemiconductor chip
602602
Passivierungsschicht oder Umverdrahtungsebenepassivation layer or redistribution level
603603
elektrisch leitfähige Elementeelectrical conductive elements

77

701701
HalbleiterchipSemiconductor chip
702702
Passivierungsschicht oder Umverdrahtungsebenepassivation layer or redistribution level
703703
elektrisch leitfähige Elementeelectrical conductive elements
704704
Verbindungsträger-KontaktfingerConnection carrier contact fingers

88th

801801
HalbleiterchipSemiconductor chip
802802
Passivierungsschicht oder Umverdrahtungsebenepassivation layer or redistribution level
803803
elektrisch leitfähige Elementeelectrical conductive elements
804804
Verbindungsträger-KontaktfingerConnection carrier contact fingers
805805
Schutz-UmhüllungProtective sheath

99

901901
HalbleiterchipSemiconductor chip
902902
Passivierungsschicht oder Umverdrahtungsebenepassivation layer or redistribution level
903903
elektrisch leitfähige Elementeelectrical conductive elements
904904
Verbindungsträger-KontaktfingerConnection carrier contact fingers
905905
Schutz-UmhüllungProtective sheath
906906
elektrisch isolierende Schichtelectrical insulating layer
907907
Durchbrüchebreakthroughs

1010

10011001
HalbleiterchipSemiconductor chip
10021002
Passivierungsschicht oder Umverdrahtungsebenepassivation layer or redistribution level
10031003
elektrisch leitfähige Elementeelectrical conductive elements
10041004
Verbindungsträger-KontaktfingerConnection carrier contact fingers
10051005
Schutz-UmhüllungProtective sheath
10061006
elektrisch isolierende Schichtelectrical insulating layer
10081008
Lotkugelnsolder balls
10091009
Kontaktflächen des HalbleiterchipsContact surfaces of the Semiconductor chips

Claims (19)

Halbleiterbauelement, • mit mindestens einem Halbleiterchip (401), welcher Kontaktflächen (409) aufweist, • mit einem elektrisch leitfähigen Verbindungsträger (402), welcher Kontaktfinger aufweist (402), die entsprechend den Kontaktflächen (409) des Halbleiterchips (401) angeordnet sind, • mit mehreren elektrisch leitfähigen Elementen (403), die zwischen einem Kontaktfinger des Verbindungsträgers (402) und einer Kontaktfläche (409) des Halbleiterchips (401) angeordnet sind und eine elektrische Verbindung sowie eine mechanische Abstandshaltung herstellen, • mit einer auf dem Verbindungsträger (402) aufgebrachten elektrisch isolierenden Schicht (404) mit Durchbrüchen (907), • mit Lotkugeln (405), die in den Durchbrüchen (907) der elektrisch isolierenden Schicht (404) angeordnet sind und mit dem Verbindungsträger (402) elektrisch leitend verbunden sind, • mit einer Schutz-Umhüllung (406) des Halbleiterchips (401).Semiconductor component, with at least one semiconductor chip ( 401 ), which contact surfaces ( 409 ), with an electrically conductive connection carrier ( 402 ), which has contact fingers ( 402 ) corresponding to the contact surfaces ( 409 ) of the semiconductor chip ( 401 ), with a plurality of electrically conductive elements ( 403 ), which between a contact finger of the connection carrier ( 402 ) and a contact surface ( 409 ) of the semiconductor chip ( 401 ) are arranged and produce an electrical connection and a mechanical spacing, • with one on the connection carrier ( 402 ) applied electrically insulating layer ( 404 ) with breakthroughs ( 907 ), • with solder balls ( 405 ) in the breakthroughs ( 907 ) of the electrically insulating layer ( 404 ) are arranged and with the connection carrier ( 402 ) are electrically conductively connected, • with a protective enclosure ( 406 ) of the semiconductor chip ( 401 ). Halbleiterbauelement gemäß Anspruch 1, wobei der Halbleiterchip (401) als Speicherchip ausgebildet ist.Semiconductor component according to claim 1, wherein the semiconductor chip ( 401 ) is designed as a memory chip. Halbleiterbauelement gemäß einem der Ansprüche 1 bis 2, wobei die elektrisch leitfähigen Elemente (403) aus Metall gebildet sind.Semiconductor component according to one of claims 1 to 2, wherein the electrically conductive elements ( 403 ) are formed of metal. Halbleiterbauelement gemäß Anspruch 3, wobei die elektrisch leitfähigen Elemente (403) aus den Metallen Gold oder Silber oder Kupfer oder Aluminium oder aus einer Legierung mit einem dieser Metalle bestehen.Semiconductor component according to claim 3, wherein the electrically conductive elements ( 403 ) consist of the metals gold or silver or copper or aluminum or of an alloy with one of these metals. Halbleiterbauelement gemäß einem der Ansprüche 1 bis 2, wobei die elektrisch leitfähigen Elemente (403) aus leitfähigem Kunstharz oder Polymer gebildet sind.Semiconductor component according to one of claims 1 to 2, wherein the electrically conductive elements ( 403 ) are formed of conductive synthetic resin or polymer. Halbleiterbauelement gemäß einem der Ansprüche 3 bis 5, mit weiteren elektrisch leitfähigen Elementen (403), welche zwischen Verbindungsträger (402) und Halbleiterchip (401) angeordnet sind und keine elektrische Verbindung, sondern allein eine mechanische Abstandshaltung herstellen.Semiconductor component according to one of Claims 3 to 5, with further electrically conductive elements ( 403 ), which between connecting carrier ( 402 ) and semiconductor chip ( 401 ) are arranged and produce no electrical connection, but only a mechanical spacing. Halbleiterbauelement gemäß einem der Ansprüche 1 bis 6, wobei der elektrisch leitfähige Verbindungsträger (402) aus Metall gebildet ist.Semiconductor component according to one of claims 1 to 6, wherein the electrically conductive connection carrier ( 402 ) is formed of metal. Halbleiterbauelement gemäß Anspruch 7, wobei der elektrisch leitfähige Verbindungsträger (402) aus Gold oder Silber oder Kupfer oder Aluminium oder aus einer Legierung mit einem dieser Metalle besteht.Semiconductor component according to claim 7, wherein the electrically conductive connection carrier ( 402 ) consists of gold or silver or copper or aluminum or of an alloy with one of these metals. Halbleiterbauelement gemäß einem der Ansprüche 1 bis 8, wobei die elektrisch isolierende Schicht (404) aus reinem oder glasfaserverstärktem Kunstharz gebildet ist.Semiconductor component according to one of claims 1 to 8, wherein the electrically insulating layer ( 404 ) is formed of pure or glass-reinforced synthetic resin. verfahren zum Herstellen eines Halbleiterbauelementes mit mindestens einem Halbleiterchip (401), welcher Kontaktflächen (409) aufweist, mit einem elektrisch leitfähigen Verbindungsträger (402), welcher Kontaktfinger aufweist (402), die entsprechend den Kontaktflächen (409) des Halbleiterchips (401) angeordnet sind, • mit mehreren elektrisch leitfähigen Elementen (403), die zwischen einem Kontaktfinger des Verbindungsträgers (402) und einer Kontaktfläche (409) des Halblei terchips (401) angeordnet sind und eine elektrische Verbindung sowie eine mechanische Abstandshaltung herstellen, • mit einer auf dem Verbindungsträger (402) aufgebrachten elektrisch isolierenden Schicht (404) mit Durchbrüchen (907), • mit Lotkugeln (405), die in den Durchbrüchen (907) der elektrisch isolierenden Schicht (404) angeordnet sind und mit dem Verbindungsträger (402) elektrisch leitend verbunden sind, • mit einer Schutz-Umhüllung (406) des Halbleiterchips (401), wobei – auf den Kontaktflächen (409) des Halbleiterchips (401) die elektrisch leitenden Elemente (403) gebildet werden – der Halbleiterchip (401) auf dem Verbindungsträger (402) angeordnet wird, – die Kontaktfinger des Verbindungsträgers (402) mit den elektrisch leitenden Elementen (403) verbunden werden, – der Halbleiterchip, mit den elektrisch leitenden Elementen (403) und dem Verbindungsträgers (402) mit einer Schutz-Umhüllung (406) umgeben wird, die die vom Halbleiterchip (401) angewandte Seite des Verbindungsträgers (402) freilässt – auf dem Verbindungsträger (402) eine elektrisch isolierende Schicht (404) angeordnet wird, – die Lotkugeln (405) in den Durchbrüchen (907) der elektrisch isolierenden Schicht (404) angeordnet und elektrisch leitend mit dem Verbindungsträger (402) verbunden werden.Method for producing a semiconductor component with at least one semiconductor chip ( 401 ), which contact surfaces ( 409 ), with an electrically conductive connection carrier ( 402 ), which has contact fingers ( 402 ) corresponding to the contact surfaces ( 409 ) of the semiconductor chip ( 401 ), with a plurality of electrically conductive elements ( 403 ), which between a contact finger of the connection carrier ( 402 ) and a contact surface ( 409 ) of the semiconductor chip ( 401 ) are arranged and produce an electrical connection and a mechanical spacing, • with one on the connection carrier ( 402 ) applied electrically insulating layer ( 404 ) with breakthroughs ( 907 ), • with solder balls ( 405 ) in the breakthroughs ( 907 ) of the electrically insulating layer ( 404 ) are arranged and with the connection carrier ( 402 ) are electrically conductively connected, • with a protective enclosure ( 406 ) of the semiconductor chip ( 401 ), whereby - on the contact surfaces ( 409 ) of the semiconductor chip ( 401 ) the electrically conductive elements ( 403 ) - the semiconductor chip ( 401 ) on the connection carrier ( 402 ), - the contact fingers of the connection carrier ( 402 ) with the electrically conductive elements ( 403 ), - the semiconductor chip, with the electrically conductive elements ( 403 ) and the connection carrier ( 402 ) with a protective sheath ( 406 ) surrounded by the semiconductor chip ( 401 ) applied side of the connection carrier ( 402 ) - on the connection carrier ( 402 ) an electrically insulating layer ( 404 ), - the solder balls ( 405 ) in the breakthroughs ( 907 ) of the electrically insulating layer ( 404 ) and electrically conductive with the connection carrier ( 402 ) get connected. Verfahren gemäß Anspruch 10, wobei die elektrisch leitenden Elemente (403) auf der Kontaktfläche (409) des Halbleiterchips (401) durch Drahtbonden und nachfolgendes Abtrennen des Drahtes am Bondkontakt hergestellt werden.Method according to claim 10, wherein the electrically conductive elements ( 403 ) on the contact surface ( 409 ) of the semiconductor chip ( 401 ) by wire Bonding and subsequent separation of the wire are made on the bonding contact. Verfahren gemäß Anspruch 11, wobei das Drahtbonden für jede Kontaktfläche (409) ein- oder mehrmals wiederholt wird.Method according to claim 11, wherein the wire bonding for each contact surface ( 409 ) is repeated one or more times. verfahren gemäß Anspruch 10, wobei die elektrisch leitenden Elemente (403) durch eine ganzflächige Metallisierung des Halbleiterchips (401), eine photolithografische Strukturierung und eine galvanische Verstärkung der metallischen Strukturen hergestellt werden.Method according to claim 10, wherein the electrically conductive elements ( 403 ) by a whole-area metallization of the semiconductor chip ( 401 ), a photolithographic patterning and a galvanic reinforcement of the metallic structures are produced. Verfahren gemäß Anspruch 10, wobei die elektrisch leitenden Elemente (403) durch das Aufbringen von leitfähigen Kunstharz oder Polymeren mittels Siebdruck- oder Dispersionsverfahren strukturiert und anschließend verfestigt werden.Method according to claim 10, wherein the electrically conductive elements ( 403 ) are structured by the application of conductive synthetic resin or polymers by screen printing or dispersion method and then solidified. Verfahren gemäß Anspruch 10, wobei die elektrisch leitenden Elemente (403) durch das ganzflächige Aufkleben einer leitfähigen Folie aus Kunststoff und deren nachfolgender photolithografischer Strukturierung hergestellt werden.Method according to claim 10, wherein the electrically conductive elements ( 403 ) are produced by the entire surface sticking of a conductive plastic film and its subsequent photolithographic patterning. Verfahren gemäß einem der Ansprüche 10 bis 14, wobei die elektrisch leitenden Elemente (403) mittels Ultraschall-Bonden mit dem Verbindungsträger (402) verbunden werden.Method according to one of claims 10 to 14, wherein the electrically conductive elements ( 403 ) by means of ultrasonic bonding with the connection carrier ( 402 ) get connected. Verfahren gemäß einem der Ansprüche 15 bis 16, wobei die elektrisch leitenden Elemente (403) mittels elektrisch leitfähigem Kleber mit dem Verbindungsträger (402) kontaktiert werden.Method according to one of claims 15 to 16, wherein the electrically conductive elements ( 403 ) by means of electrically conductive adhesive with the connection carrier ( 402 ) are contacted. Verfahren gemäß einem der Ansprüche 10 bis 17, wobei die elektrisch isolierende Schicht (404) mittels Schleuder- oder Sprühverfahren auf den Verbindungsträger (402) aufgebracht wird und die Durchbrüche (907) für die Lotkugeln (405) mittels photolithografischer Strukturierung gebildet werden.Method according to one of claims 10 to 17, wherein the electrically insulating layer ( 404 ) by means of spin or spray method on the connection carrier ( 402 ) and the breakthroughs ( 907 ) for the solder balls ( 405 ) are formed by photolithographic structuring. Verfahren gemäß einem der Ansprüche 10 bis 17, wobei die elektrisch isolierende Schicht (404) mit vorhandenen Durchbrüchen (907) auf den Verbindungsträger (402) aufgeklebt wird.Method according to one of claims 10 to 17, wherein the electrically insulating layer ( 404 ) with existing breakthroughs ( 907 ) on the connection carrier ( 402 ) is glued.
DE102006006825A 2006-02-14 2006-02-14 Semiconductor component e.g. ball grid array semiconductor component, has semiconductor chip with protective casing, and soldering ball arranged in recess of electrical insulating layer and connected with connecting carrier Ceased DE102006006825A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102006006825A DE102006006825A1 (en) 2006-02-14 2006-02-14 Semiconductor component e.g. ball grid array semiconductor component, has semiconductor chip with protective casing, and soldering ball arranged in recess of electrical insulating layer and connected with connecting carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102006006825A DE102006006825A1 (en) 2006-02-14 2006-02-14 Semiconductor component e.g. ball grid array semiconductor component, has semiconductor chip with protective casing, and soldering ball arranged in recess of electrical insulating layer and connected with connecting carrier

Publications (1)

Publication Number Publication Date
DE102006006825A1 true DE102006006825A1 (en) 2007-08-23

Family

ID=38288696

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102006006825A Ceased DE102006006825A1 (en) 2006-02-14 2006-02-14 Semiconductor component e.g. ball grid array semiconductor component, has semiconductor chip with protective casing, and soldering ball arranged in recess of electrical insulating layer and connected with connecting carrier

Country Status (1)

Country Link
DE (1) DE102006006825A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012006403A1 (en) * 2010-07-08 2012-01-12 Tessera, Inc. Microelectronic package with dual or multiple - etched flip -chip connectors and corresponding manufacturing method
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8884448B2 (en) 2007-09-28 2014-11-11 Tessera, Inc. Flip chip interconnection with double post
US9030001B2 (en) 2010-07-27 2015-05-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10535626B2 (en) 2015-07-10 2020-01-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US11973056B2 (en) 2022-12-22 2024-04-30 Adeia Semiconductor Technologies Llc Methods for low temperature bonding using nanoparticles

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19702014A1 (en) * 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chip module and method for producing a chip module
EP1189279A1 (en) * 2000-03-13 2002-03-20 Dai Nippon Printing Co., Ltd. Resin-sealed semiconductor device, circuit member used for the device, and method of manufacturing the circuit member
DE10224124A1 (en) * 2002-05-29 2003-12-18 Infineon Technologies Ag Electronic component with external surface contacts and process for its production
DE10240461A9 (en) * 2002-08-29 2004-09-09 Infineon Technologies Ag Universal housing for an electronic component with a semiconductor chip and method for its production

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19702014A1 (en) * 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chip module and method for producing a chip module
EP1189279A1 (en) * 2000-03-13 2002-03-20 Dai Nippon Printing Co., Ltd. Resin-sealed semiconductor device, circuit member used for the device, and method of manufacturing the circuit member
DE10224124A1 (en) * 2002-05-29 2003-12-18 Infineon Technologies Ag Electronic component with external surface contacts and process for its production
DE10240461A9 (en) * 2002-08-29 2004-09-09 Infineon Technologies Ag Universal housing for an electronic component with a semiconductor chip and method for its production

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8884448B2 (en) 2007-09-28 2014-11-11 Tessera, Inc. Flip chip interconnection with double post
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8723318B2 (en) 2010-07-08 2014-05-13 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
WO2012006403A1 (en) * 2010-07-08 2012-01-12 Tessera, Inc. Microelectronic package with dual or multiple - etched flip -chip connectors and corresponding manufacturing method
US9397063B2 (en) 2010-07-27 2016-07-19 Tessera, Inc. Microelectronic packages with nanoparticle joining
US9030001B2 (en) 2010-07-27 2015-05-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US9496236B2 (en) 2010-12-10 2016-11-15 Tessera, Inc. Interconnect structure
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9818713B2 (en) 2015-07-10 2017-11-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10535626B2 (en) 2015-07-10 2020-01-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10892246B2 (en) 2015-07-10 2021-01-12 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US11710718B2 (en) 2015-07-10 2023-07-25 Adeia Semiconductor Technologies Llc Structures and methods for low temperature bonding using nanoparticles
US11973056B2 (en) 2022-12-22 2024-04-30 Adeia Semiconductor Technologies Llc Methods for low temperature bonding using nanoparticles

Similar Documents

Publication Publication Date Title
DE10333841B4 (en) A method of producing a benefit having semiconductor device locations arranged in rows and columns and methods of making a semiconductor device
DE10201781B4 (en) High frequency power device and high frequency power module and method of making the same
DE102006037538B4 (en) Electronic component, electronic component stack and method for their production and use of a bead placement machine for carrying out a method for producing an electronic component or component stack
DE10045043B4 (en) Semiconductor component and method for its production
DE10259221B4 (en) Electronic component comprising a stack of semiconductor chips and method of making the same
DE112013007312B4 (en) FIRST HOUSED AND LATER ETCHED THREE-DIMENSIONAL FLIP-CHIP SYSTEM-IN-PACKAGE STRUCTURE AND PROCESS FOR THEIR PRODUCTION
DE10234951B4 (en) Process for the production of semiconductor circuit modules
DE102005043557B4 (en) Method for producing a semiconductor device with through contacts between top side and rear side
DE102006032073B4 (en) Electrically conductive composite of a component and a carrier plate
DE102007002707A1 (en) System in package module
DE102013104721A1 (en) System and method for improved low pitch connection
DE19821715A1 (en) Housing with a circuit component
DE102004034397A1 (en) An image sensor module and method of manufacturing a wafer plane package
DE102005041451A1 (en) USB interface plug in electronic unit has moulded housing with electronic components including multiple layer connections through lead frame integrated in connector
WO2005041295A2 (en) Semiconductor module provided with contacts extending through the housing
DE10251530A1 (en) Stack arrangement for FBGA memory module, has encapsulation at central region of each memory chip, constituting spacer between chips, and metallization connected to carrier substrate
EP1620893B1 (en) Method for the manufacture of a panel and method for the manufacture of electronic components comprising stacked semiconductor chips from the panel
DE102005046737A1 (en) Component with chip through contacts
DE102006006825A1 (en) Semiconductor component e.g. ball grid array semiconductor component, has semiconductor chip with protective casing, and soldering ball arranged in recess of electrical insulating layer and connected with connecting carrier
DE10031951A1 (en) Multiple chip semiconducting module has adhesive layers with openings coinciding with contact points, conducting bodies for connecting between first and second chip contact points
DE10334575B4 (en) Electronic component and use and method for producing the same
DE10144467B4 (en) Electronic sensor component and method for its production
DE10124970B4 (en) Electronic component with a semiconductor chip on a semiconductor chip connection plate, system carrier and method for the production thereof
DE10136655C1 (en) Multichip module in COB design, in particular CompactFlash card with high storage capacity and method for producing the same
DE10250634B4 (en) Semiconductor structure with compliant interconnecting element and method of making the same

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection