DE102006026949A1 - Resistive switching memory e.g. phase change random access memory, component, has nano wire transistor or nano tube- or nano fiber-access-transistor, having transistor-gate-area, which is part of word-line - Google Patents

Abstract

The component (1) has a nano wire transistor (4) or nano tube- or nano fiber-access-transistor, having a transistor-gate-area , which is a part of a word-line. A contact surface between the nano wire-or nano tube or a nano fiber-access-transistor and a switching active material (2) of the component exhibit a specific width and/or the length and/or a diameter. The active material directly contacts to a nano wire or a nano tube or nano fiber of the transistor, and a capacitive unit is provided for storing of data. An independent claim is also included for a method for manufacturing a memory-component.

Description

Background of the invention

The The invention relates to a memory device, in particular a resistive switching memory device such as e.g. a phase change memory with random access ("PCRAM") with a transistor. Furthermore, the invention relates to a method for manufacturing a memory device.

at usual Memory devices, in particular conventional semiconductor memory devices a distinction is made between so-called function memory components (e.g. PLRs, PALs, etc.), and so-called table storage devices, e.g. ROM devices (ROM = Read Only Memory - in particular PROMs, EPROMs, EEPROMs, flash memory, etc.), and RAM devices (RAM = Random Access Memory - in particular DRAMs and SRAMs).

One RAM device is a memory for storing data under a predetermined address, and later reading the data below this address. For SRAMs (Static Random Access Memory) the individual memory cells e.g. out of a few, for example 6 Transistors, and so-called DRAMs (DRAM = dynamic random access memory) I. A. only from a single, appropriately controlled capacitive Element.

Of others are - since newer - too so-called "resistive" or "resistive switching "memory components known, e.g. so-called phase change memory with random access or Phase Change Random Access Memories ("PCRAMs"), Conductive Bridging Memory with Random Access Random Access Memories ("CBRAMs"), etc., etc.

For "resistive" or "resistive switching "memory devices becomes a - e.g. arranged between two corresponding electrodes - "active" or "switching active" material by appropriate switching operations in one more or less conductive State (for example, where the more conductive state of a stored, logical "one" corresponds, and the less conductive State of a stored, logical "zero", or vice versa).

at Phase change random access memories (PCRAMs) may be used as a "switching active" material, for example corresponding chalcogenide or a chalcogenide compound material (e.g., a Ge-Sb-Te ("GST") or Ag-In-Sb-Te compound material, etc.) Chalcogenide compound material can be transformed into an amorphous, i.e. relatively weakly conductive, or a crystalline, i. relatively strong conductive, condition (for example, the relatively highly conductive state a stored, logical "one" can correspond, and the relatively weak conductive State of a stored, logical "zero", or vice versa.) Phase change memory cells are e.g. from G. Wicker: "Nonvolatile, High Density, High Performance Phase Change Memory ", SPIE Conference on Electronics and Structures for MEMS, Vol. 3891, Queensland, 2, 1999 known as well as e.g. from Y.N. Hwang et. al .: "Completely CMOS Compatible Phase Change Nonvolatile RAM Using NMOS Cell Transistors, IEEE Proceedings of the Nonvolatile Semiconductor Memory Workshop, Monterey, 91, 2003, S. Lai et. al .: "OUM-a 180nm nonvolatile memory cell element technology for stand alone and embedded applications ", IEDM 2001, Y. Ha et. al .: "An edge contact type cell for phase change RAM featuring very low power consumption ", VLSI 2003, H. Horii et. al .: "A novel cell technology using N-doped films for phase change RAM ", VLSI 2003, Y. Hwang et. al .: "Full integration and reliability evaluation of phase-change RAM based on 0.24μm CMOS technologies ", VLSI 2003, and S. Ahn et. al .: "Highly Manufacturable High Density Phase Change Memory of 64Mb and beyond ", IEDM 2004, etc.

at the o.g. Conductive Bridging Random Access Memory (CBRRMs) the storage of data is achieved by using a switching operation which is based on a statistical bridging by several metal-rich Deposits in the "switching active" material based. By applying a write pulse (positive pulse) to two corresponding Electrodes in contact with the "switching active" material The deposits in the volume continue to grow until they touch each other a conductive bridge (conductive bridging) is formed by the "switching-active" material, what a state of high conductivity the corresponding CBRAM memory cell leads. By applying a negative Pulse to the corresponding electrodes, this process again reversed which causes the CBRAM memory cell to go back to its original state Low conductivity state can be brought. Such memory devices are e.g. described in Y. Hirose, H. Hirose, J. Appl. Phys. 47, 2767 (1975), T. Kawaguchi et. al., "Optical, electrical and structural properties of amorphous Ag-Ge-S and Ag-Ge films and comparison of photoinduced and thermally induced phenomena of both systems ", J. Appl. Phys. 79 (12), 9096, 1996, M. Kawasaki et. al., "Ionic conductivity of Agx (GeSe3) 1-x (0 <x0.571) glasses, "Solid State Ionics 123, 259, 1999, etc.

Similar to the above-mentioned PCRAMs, a corresponding chalcogenide or a chalcogenide can be used for CBRAM memory cells connection can be used as a "switching-active" material (eg GeSe, GeS, AgSe, CuS, etc.).

in the Case of PCRAMs must be in order for a corresponding PCRAM memory cell Change from the o.g. amorphous, i. relatively weak conductive state of the switching active material in the o.g. crystalline, i. relative highly conductive State of the switching active material to achieve a corresponding relatively high heating current pulse are applied to the electrodes, where the heating-current pulse causes that the switching active material over the crystallization temperature is heated up, and crystallized ( "Write").

Vice versa can be a state change of the switching active material of the crystalline, i.e. relatively strong conductive State in the amorphous, i. relatively weak conductive state e.g. be achieved in that - again by means of a corresponding (relatively high) heating current pulse - the switching active Material over heated up the melting temperature, and then by fast cooling down is "quenched" into an amorphous state ("erase").

typically, the o.g. erasable or write-heating pulses over corresponding source lines and bit lines are supplied, and corresponding FET or bipolar access transistors, the corresponding memory cells are assigned, and over corresponding word lines are controlled.

There as stated above, relatively high extinguishing or write-heating pulses may be required are relatively large (Wide) access transistors necessary, resulting in relatively large memory devices leads. Out this and other reasons there is a need for that present invention.

Short summary of invention

According to one Aspect of the invention, a memory device is provided, which includes at least one nanowire or nanotube or nanofiber access transistor having. Advantageously, the nanowire or nanotube contact or nanofiber access transistor directly a switching active material of the memory device. According to another Aspect, a memory device has at least one nanowire or nanotube or nanofiber transistor with a vertically arranged nanowire or nanotube or nanofiber. The memory component is advantageous a resistively switching memory device, for example a phase change memory with random access, or a Conductive Bridging Memory with random access.

Short description of several Views of the drawing

The Enclosed drawing is included to further understand the to enable the present invention and is incorporated in the description and constitutes a part thereof. The drawing illustrates embodiments of the present invention Invention and serves, along with the description principles to explain the invention. Other embodiments of the present invention and many desired advantages of the present invention be perfectly clear as they are accurate with reference to the following Description to be better understood.

1a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

1b shows a view of the in 1a shown memory device from above.

2a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

2 B shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

2c shows a view of the in 2 B shown memory device from above.

3a shows a schematic cross-sectional view of a memory array area of a partially fabricated memory device according to an embodiment of the present invention.

3b shows a view of the in 3a shown memory device from above.

3c shows a schematic cross-sectional view of an edge region of the in 3a shown memory component.

4a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

4b shows a view of the in 4a shown memory device from above.

4c shows a schematic cross-sectional view of an edge region of the in 4a shown Memory device.

5a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

5b shows a view of the in 5a shown memory device from above.

5c shows a schematic cross-sectional view of an edge region of the in 5a shown memory component.

6 shows a schematic cross-sectional view of an edge region of a partially fabricated memory device according to an embodiment of the present invention.

7a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

7b shows a view of the in 7a shown memory device from above.

7c shows a schematic cross-sectional view of an edge region of the in 7a shown memory component.

8a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

8b shows a view of the in 8a shown memory device from above.

8c shows a schematic cross-sectional view of an edge region of the in 8a shown memory component.

9a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

9b shows a view of the in 9a shown memory device from above.

9c shows a schematic cross-sectional view of an edge region of the in 9a shown memory component.

10a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

10b shows a view of the in 10a shown memory device from above.

10c shows a schematic cross-sectional view of an edge region of the in 10a shown memory component.

10d shows a schematic cross-sectional view of the memory array area of the in 10a shown memory component.

11a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

11b shows a view of the in 11a shown memory device from above.

12a shows a schematic cross-sectional view of a memory array region of a partially fabricated memory device according to an embodiment of the present invention.

12b shows a view of the in 12a shown memory device from above.

12c shows a schematic cross-sectional view of the memory array area of the in 12a shown memory component.

Detailed description of the invention

In The following detailed description will be made with reference to the accompanying drawings taken, which forms part of it, and in the example special embodiments are shown, in which the invention can be realized. In this context, the directional information used Terminology such as "top", "bottom", "front", "back", etc. with reference used on the orientation of the described figure (s). Because elements the embodiments of the present invention in a variety of orientations can be arranged will be the direction information used terminology for illustration only, and is in no way limiting. It is understood that other embodiments can be used and changes made in the structure or other changes can be without departing from the scope of the invention. The following exact description should not be in a limiting sense and the scope of the present invention is attached by the claims Are defined.

1a shows a schematic cross section View of a memory array area of a partially manufactured memory device 1 according to an embodiment of the present invention.

The memory device 1 is preferably a "resistive" or "resistively switching" memory device, in particular a phase change memory device with random access ("PCRAM").

The "resistive switching" memory device 1 Like conventional "resistively switching" memory devices, it has an "active" or "switching active" material 2 which is set in a more or less conductive state by corresponding switching processes (where, for example, the more conductive state may correspond to a stored logical "1", and the less conductive state may correspond to a stored logical "0", or vice versa).

As a "active" material 2 For example, a corresponding chalcogenide or chalcogenide compound material may be used (here, for example, a Ge-Sb-Te ("GST") compound material (or, for example, an Ag-In-Sb-Te compound material, etc.). The chalcogenide compound material is adapted to be brought into an amorphous, ie relatively weakly conductive, or a crystalline, ie relatively strongly conductive state.

As in 1 is shown, and as will be described in more detail below, is the "switching active" material 2 unlike conventional phase change memory devices with random access ("PCRAM"), not between two corresponding electrodes, but between one electrode 3 , and a nanowire or nanowire transistor 4 ,

To a change from the above-mentioned amorphous, ie relatively weakly conductive state of the switching active material 2 to the above-mentioned crystalline, ie relatively strong conductive state of the switching active material 2 to reach, is to the switching active material 2 a corresponding heating-current pulse applied, wherein the heating-current pulse causes the switching-active material 2 is heated beyond the crystallization temperature and crystallized ("writing").

Conversely, a change of state of the switching active material 2 from the crystalline, ie relatively strongly conductive state, to the amorphous, ie relatively weakly conductive state, for example achieved by - again by a corresponding heating current pulse - the switching active material 2 is heated above the melting temperature and then "quenched" by rapid cooling to an amorphous state ("quenching").

As described in more detail below, and as in 1a 2, the above-mentioned erase or write-heating current pulses are via respective source lines 5 fed, and via the above nanowire transistors 4 (In particular corresponding npn-doped regions 4a the transistors 4 ), which are in direct contact with the switching active material 2 stand.

From the switching active material 2 from the corresponding erase or write-heating current flows through the above-mentioned electrodes 3 (which also in direct contact with the switching active material 2 and corresponding bit lines (not shown) connecting the electrodes 3 to contact.

As also described in more detail below, the npn-doped regions mentioned above are 4a the transistors 4 of corresponding transistor gate regions 4b which also act as word lines.

The nanowire transistors 4 are formed in a vertical direction. The nanowire transistors 4 act as "access transistors", and because of the direct contact between the npn-doped regions 4a , and the switching active material 2 - in addition as electrodes.

As in 1b is the contact area between a corresponding npn-doped region 4a , and a corresponding switching active material 2 relatively small, resulting in a relatively high current density in the switching active material 2 leads.

Whether a corresponding transistor 4 is in a conductive state (in which an erase or write-heating current from a corresponding source line 5 through a corresponding npn-doped transistor region 4a to the associated switching active material 2 can flow) or a non-conductive state (which prevents an erase or write-heating current from a corresponding source line 5 through a corresponding npn-doped transistor region 4a to the associated switching active material 2 can flow), or not, is determined by the state of the above word lines / transistor gate areas 4b certainly.

As in 1b (and for example also in 2c ), the above-mentioned source lines are running 5 (and for example, the above-mentioned bit lines, which are the electrodes 3 contact) in a direction A through the memory device 1 which is perpendicular to a direction B in which the word lines 4b through the Speicherbauele ment 1 to run.

Thus, a corresponding switching active material 2 to be selected for writing / deleting by the corresponding associated word line 4b is activated, and to the corresponding source line 5 an erase or write heating current pulse is applied.

Relegated to 1a , are the source lines 5 through appropriate STI areas 6 isolated from each other (STI = shallow trench isolation).

For the above electrodes 3 For example, TiN may be used, or for example, W, Ti, Ta, or, for example, Cu, Ag, Au, Zn, etc. or, for example, WN, TaN, NbN, ZrN, HfN, or, for example, TiSiN, TaSiN, TiAlN , etc. or any other usable material.

Associated pairs of switching active material 2 / electrodes 3 are from adjacent pairs of switching active material 2 / electrodes 3 isolated by useable insulating material, for example SiO ₂ (not shown).

The following is an example of a method of manufacturing the in 1a and 1b shown memory component 1 described in more detail.

First, as in 2a and, as with conventional phase change memory ("PCRAM") random access memory devices, the above STI ranges 6 in a corresponding silicon substrate 7 educated. The STI areas 6 are both in a memory array area of the memory device 1 (in 2a shown), as well as in an edge region of the memory device 1 (Not shown).

As in 2c is shown, the STI areas extend 6 in the above direction A, ie, parallel to the source lines 5 (the one after the STI areas 6 are formed, see description below).

After creating the STI areas 6 and, as is the case for conventional phase change memory ("PCRAM") random access memory devices, in the aforementioned edge area of the memory device 1 corresponding transistors 8th for controlling, for example, the above-mentioned word lines 4b , and / or the above-mentioned source lines 5 (or more precisely, parts of corresponding transistors 8th ) are formed.

Thereupon, as in 2 B using a corresponding salicidation (salicidation) process and as is the case with conventional phase change memory ("PCRAM") random access memory devices, in the above-mentioned memory array portion of the memory device 1 the above source lines 5 (and, for example, corresponding sources / drains, and gates in the above-mentioned edge region of the memory device 1 , for example, sources / drains 5a , and Gates 5b the above-mentioned peripheral transistors 8th ). In the course of the above-mentioned salicidation process, a corresponding self-aligned silicidation takes place, resulting in a reaction of, for example, cobalt (or for example nickel, titanium, etc.) with that in the abovementioned substrate 7 existing silicon leads, for example, the above-mentioned source lines 5 (and the above sources / drains 5a , and Gates 5b ) be formed. Optionally, then, portions of the areas subject to the aforementioned salicidation process (for example, areas where no contacts are to be made) may be covered with a corresponding varnish.

In a subsequent step, and as in the 3a and 3c (as is the case with conventional phase-change memory ("PCRAM") random access memory devices), both on the memory array area and the edge area of the memory device 1 corresponding insulating layers are deposited, for example, first a SiN layer 9 , and then an SiO ₂ layer 10 which, for example, the above-mentioned source lines 5 , and the STI areas 6 cover. In this case, for example, corresponding ILD (inter level dielectric) - deposition methods can be used. After depositing the above SiN and / or SiO ₂ layers 9 . 10 a corresponding polishing can take place. The SiO ₂ layer 10 has, for example, a height between 200 nm and 600 nm, for example between 300 nm and 500 nm, and the SiN layer 9 for example, a height between 5 nm and 50 nm, for example between 10 nm and 30 nm.

After depositing the above SiN and SiO ₂ layers 9 . 10 be in a subsequent step, and as in the 4a and 4c (as is the case with conventional phase change memory ("PCRAM") random access memory devices) on both the memory array area and the edge area of the memory device 1 a corresponding etch-stop layer 11 , and another insulating layer 12 deposited, for example, first a SiC layer 11 as an etch stop layer 11 (For example, the above-mentioned SiO ₂ layer 10 covers), and then a SiO ₂ layer 12 as a further insulating layer 12 (For example, the above-mentioned SiC layer 11 covers). The SiC layer 11 has to For example, a height between 5 nm and 50 nm, for example between 10 nm and 30 nm, and the SiO ₂ layer 12 for example, a height between 100 nm and 400 nm, for example between 150 nm and 250 nm.

After depositing the above SiC and SiO ₂ layers 11 . 12 be in a subsequent step, and as in 5c (as is the case with conventional phase change memory ("PCRAM") random access memory devices) in the edge area of the memory device 1 (but not in the memory array area, see 5a and 5b ) corresponding contact holes 13 formed, preferably using corresponding contact lithography and etching processes, for example, including a 4-step etching, for example, a corresponding SiO ₂ / SiC / SiO ₂ / SiN etching process. As in 5c shown, the contact holes extend 13 all through the above layers 9 . 10 . 11 . 12 so that the above sources / drains 5a the above-mentioned peripheral transistors 8th be disclosed.

In a subsequent step, and as in 6 (as is the case with conventional phase change memory ("PCRAM") random access memory devices) in the edge area of the memory device 1 in the contact holes 13 a liner 14 deposited, for example, Ti / TiN, the - in one direction down - the above sources / drains 5a the above-mentioned peripheral transistors 8th contacted, as well as - in a lateral direction - the above layers 9 . 10 . 11 . 12 , Thereupon, as well as in 6 shown the contact holes 13 with a corresponding filler 15 filled, for example tungsten. Subsequently, a corresponding polishing process is carried out, for example a corresponding CMP (chemical mechanical polishing) process.

After performing the polishing process is in a subsequent step, and as in the 7a and 7c shown both on the memory array area of the memory device 1 (here: on the shift 12 which, for example, in 5a is shown) and the edge region of the memory device 1 (here: both on the above layer 12 , and the filler 15 ) another SiO ₂ layer 12a deposited. In this case, the SiO ₂ layer 12 increased in height, for example to a SiO ₂ layer 12b with a (total) height between, for example, 200 nm and 500 nm, for example between 250 nm and 350 nm (see for example 7a ).

After depositing the above-mentioned SiO ₂ layer 12a . 12b be in a subsequent step, and as in the 8a . 8b . 8c shown in the edge region of the memory device 1 (please refer 8c ) and in the memory array area (see 8a and 8b ) corresponding areas 20 etched, preferably using corresponding "metal 1" (= first metal layer) lithography and etching processes. In doing so, as in 8c shown in the edge region of the memory device 1 , above the filling material 15 (and thus over the sources / drains 5a the peripheral transistors 8th ) corresponding trenches entirely through the above-mentioned SiO ₂ layer 12a formed through, so that the filling material 15 is disclosed. Furthermore, as in the 8a . 8b shown in the memory array area of the memory device 1 in areas 20 where the above word lines / transistor gate areas 4b to be formed later (see for example 1a ), the above-mentioned SiO ₂ layer 12b etched, leaving the above-mentioned etching stop layer 11 (Here, for example, the above-mentioned SiC layer 11 ).

Like from the 8b As can be seen, the ranges extend 20 etched in the memory array area - as well as the word lines / transistor gate areas 4b which are to be formed later - in the above direction B entirely through the memory array region, ie perpendicular to the above-mentioned direction A, in which the source lines 5 through the memory device 1 run. In addition, adjacent areas etched in the memory array area extend 20 - like adjacent word lines / transistor gate areas 4b that are to be formed later - parallel to each other.

The areas etched in the memory array area 20 can - like the later to be formed word lines / transistor gate areas 4b Have a width of, for example, 3 F (where F represents the minimum feature size, for example between 40 nm and 80 nm, for example between 50 nm and 70 nm, for example 65 nm). The distance between two adjacent areas etched in the memory array area 20 can - like the distance between two adjacent word lines / transistor gate areas 4b to be formed later - for example, be about 1F.

Like from the 8a and 8b As can be seen, when the above-mentioned metal 1 lithography and etching processes are carried out, areas remain 21 directly above the above source lines 5 - more precisely, areas 21 where the above transistors 4 (More specifically, the npn-doped transistor regions 4a , please refer 1a ) are later to form - stand. The areas 21 For example, they may have substantially rectangular or square cross sections, and may have, for example, a width and length of, for example, 1F sen. Furthermore, the distance between adjacent areas 21 for example also be 1F.

After performing the above-mentioned metal 1 lithography and etching processes, in a subsequent step, and as in the 9a . 9b . 9c shown in the edge region of the memory device 1 (please refer 9c ) and in the memory array area (see 9a and 9b ) the etched areas 20 (please refer 8a . 8b . 8c ) filled. For this purpose, first a TaN-Ta barrier or barrier 31 in the etched areas 20 deposited (for example in the edge region of the memory device 1 , on the surface of the filling material 15 , and on sidewalls of the layer 12a (please refer 9c ), and in the storage array area, on the surface of the layer 11 , and on sidewalls of the layer 12b / the above areas 21 (please refer 9a )). Then, for example, using a corresponding sputtering process, Cu nuclei on the surface of the TaN / Ta barrier 31 deposited. After that, a corresponding metal 30 For example, Cu is electrochemically deposited, for example, by performing a corresponding Cu plating process. This will cause the above etched areas 20 completely with the above metal 30 (here: Cu) filled. Finally, a corresponding polishing process is performed, for example a CMP (chemical mechanical polishing) process. In summary, to form the above-mentioned word lines / gate regions 4b which are the above metal 30 as above with respect to the 7a to 9c explains a "damascene" process running.

After that, in a subsequent step, and as in the 10a . 10b . 10c . 10d a corresponding lithography and etching process is shown executed. For this purpose, in a first step, both the edge region of the memory component 1 (please refer 10c ) and the memory array area of the memory device 1 (please refer 10a . 10b ) with a corresponding paint 40 covered. Then the paint becomes 40 - in parts of the memory array area (see below), but not in the edge area - exposed (exposed to light, for example), and designed so that the paint 40 in exposed (exposed) areas 41 can be removed. As in 10b shown has the remaining - not removed - paint 40 in the memory array area, the form of stripes extending in the above-mentioned direction B through the entire memory array area (in parallel with the word lines / transistor gate areas) 4b , and perpendicular to the above-mentioned direction A, in which the source lines 5 through the memory device 1 run). As in 10b shown, the strips of paint remaining 40 in the memory array area, for example, have a width of, for example, about 2F. Furthermore, as in the 10b and 10d shown, the longitudinal center axes of the above-mentioned exposed areas 41 where the paint 40 was removed on the longitudinal center axes of the above ranges 21 , shown in 8a . 8b , centered, which were left standing, as the above, in terms of the 8a . 8b have been described (ie, centered with respect to the longitudinal center axes of the regions 21 where the above npn-doped transistor areas 4a , please refer 1a to be formed later).

Then, as in the 10a . 10b . 10d shown in the memory array area of the memory device 1 (but not in the border area, see 10c ) corresponding contact holes 50 designed, preferably - similar to those for forming the above contact holes 13 in the edge region used, and as with reference to 5c using a corresponding 4-step etching, for example a corresponding SiO ₂ / SiC / SiO ₂ / SiN etching process. As in the 10a . 10b . 10d shown, the contact holes extend 50 all through the above layers 9 . 10 . 11 . 12b (more precisely: the above, left-sided areas 21 ) - but not by the metal 30 since the above-mentioned copper metal and the TaN / Ta barrier 31 prevents etching of this - so that the above-mentioned source lines 5 be partially disclosed. Thus, an etching is performed with respect to the above-mentioned first metal layer, here: the transistor gate regions / word lines 4b self-aligning or self-aligned.

After performing the above-mentioned 4-step etching, the (remaining) varnish becomes 40 in both the memory array area and the edge area of the memory device 1 away.

Then, as in the 11a . 11b is shown, the above-mentioned (nanowire) npn-doped transistor regions 4a in the above contact holes 50 educated. For this purpose, in a first step, a catalyst 51 on the surface of the exposed, exposed portions of the source lines 5 deposited using, for example, an electro-less deposition process. The catalyst 51 For example, it may predominantly have a corresponding silicide-forming metal such as Ti, Pd, Pt, Au, Cu, Co, Cr, Hf, Ir, Mn, Mo, Ni, Rh, Ta, W, Zr, etc. Thereupon may be on the surface of the (exposed, exposed) parts of the source lines 5 deposited catalyst 51 to be heated so that its surface is reduced by coagulation. Thereby, as is clear from the description below, the contact area between the NPN-doped transistor regions to be formed yet 4a , and the switching active material 2 (also to be formed later), which further reduces the current density in the switching active material 2 further increased.

Then it is left using the above catalyst 51 in the contact holes 50 a corresponding nanowire / nanotube / nanofiber grow (for example a corresponding Si nanowire, as described, for example, in Cui, Y., Duan, X., Hu, J., Lieber, CM: J. Phys. Chem. B 2000, 103 , 5213, or any other useful nanowire / nanotube / nanofiber, for example a corresponding carbon nanowire / nanotube / nanofiber, etc.), so that eventually the npn-doped transistor regions mentioned above 4a be formed. As in 11a to see, the catalyst remains 51 (not in 11b shown), while the corresponding nanowire / nanotube / nanofiber grows growing at its tip. As in further 11a shown remains between the nanowire / nanotube / nanofiber and the above layers 9 . 10 . 11 / the above barrier 31 a free space. Furthermore - as in 11b shown - the nanowire / nanotube / nanofiber have a cross-section which is substantially round. The diameter of the nanowire / nanotube / nanofiber may be relatively small, for example below 1F, for example between 0.1F and 1F, for example between 0.2F and 0.5F, etc.

According to 11a For example, a lower portion of the nanowire / nanotube / nanofiber may be n-doped (or alternatively: p-doped), a middle portion of the nanowire / nanotube / nanofiber may be p-doped (or alternatively n-doped), and an upper portion of the nanowire / nanotube / nanofiber may again be n-doped (or alternatively: p-doped). The corresponding doping of the nanowire / nanotube / nanofiber can be achieved, for example, by adding corresponding gases into the atmosphere during the growth of the nanowire / nanotube / nanofiber. For example, while the above-mentioned lower portion of the nanowire / nanotube / nanofiber grows, for example, PH _{3 may} be added to the atmosphere so that a corresponding n-type doping of the lower portion of the nanowire / nanotube / nanofiber is achieved. Further, as the above-mentioned middle section of the nanowire / nanotube / nanofiber grows, for example, B ₂ H _{6 may} be added to the atmosphere so that a corresponding p-type doping of the middle section of the nanowire / nanotube / nanofiber is achieved. Finally, during the upper portion of the nanowire / nanotube / nanofibre is growing, PH ₃ is added to the atmosphere again, so that a corresponding n-type doping of the upper section of the nanowire / nanotube / nanofibre is achieved.

After forming the nanowire / nanotube / nanofiber becomes, as in the 12a . 12b . 12c shown the gate oxide of the transistors 4 formed, for example, by conformal deposition of SiO ₂ i) in the above-mentioned free space between the nanowire / nanotube / nanofiber, and the layers 9 . 10 . 11 / the barrier 31 , and ii) above the metal 30 (here: Cu) / above the barrier 31 (see for example the in the 12a . 12b . 12c shown SiO ₂ layer 60 ). In this case, (for example for the above-mentioned step i)), for example, a corresponding thermal SiO ₂ deposition process can be used, and / or (in particular for the above-mentioned step ii)), for example a corresponding CVD (chemical vapor deposition) or ALD - (Atomic layer deposition) method, etc. Then, a corresponding polishing method is carried out, for example, a corresponding CMP (chemical mechanical polishing) process, wherein the above-mentioned catalyst 51 on top of the nanowire / nanotube / nanofiber is removed.

Then, as in the 1a and 1b (as is the case with conventional phase change memory devices with random access ("PCRAM")) the "switching active" material 2 deposited, for example, the above-mentioned Ge-Sb-Te ("GST") compound material 2 (here: on the upper surface of the nanowire / nanotube / nanofiber, and the upper surface of the above SiO ₂ layer 60 , ie, in the whole memory array area). For separating the "switching-active" material 2 For example, a corresponding PVD (physical vapor deposition) process or, for example, a corresponding CVD (chemical vapor deposition) process can be used.

Then, as well as in the 1a and 1b (as is the case with conventional phase change memory devices with random access ("PCRAM")), the electrode 3 on the "switching active" material 2 deposited, ie on the whole memory array area. Thereafter, appropriate lithography and etching processes are performed to achieve that the electrode 3 and the "switching-active" material 2 - as in 1b for example, both have a substantially rectangular or square cross-section and, for example, have a width and length of, for example, about 1F.

As in 1a shown is the vertical axis of the "switching active" material 2 (and the electrode 3 ) on the vertical axis of the nanowire / nanotube / nanofiber (ie the npn-doped transistor areas 4a centered). The lower surface of the "switching active" material 2 contacts the top surface of the nanowire / nanotube / nanofiber (and the top surface of those parts of the SiO ₂ layer 60 surrounding the nanowire / nanotube / nanofiber).

Thereafter, the above-mentioned insulating material (not shown) is deposited, for example, SiO ₂ , the associated pairs of switching active material 2 / electrodes 3 from adjacent pairs of switching active material 2 / electrodes 3 isolated. Thereafter, a corresponding polishing process is performed, for example, a corresponding CMP (chemical mechanical polishing) process (such that the upper surface of the insulating material, and the electrode 3 to be polished).

Even though specific embodiments here are shown and described by those skilled in the art that many others and / or equivalent Implementations specific embodiments shown and described can replace without departing from the scope of the present invention. The application intends to be subject to change and variation of the specific embodiments discussed herein. For this reason, it is intended that the invention only by the requirements and equivalents this is limited.

1

memory device

2

switching active material

3

electrode

4

Nanowire transistor

4a

n-p-n-doped areas

4b

Transistor gate regions

5

Source lines

5a

Sources / drains

5b

Gates

6

STI regions

7

substratum

8th

transistor

9

SiN layer

10

SiO ₂ layer

11

SiC layer

12

SiO ₂ layer

12a

SiO ₂ layer

12b

SiO ₂ layer

13

vias

14

liner

15

filling material

20

etched areas

21

left standing areas

30

metal

31

Barrier

40

paint

41

exposed areas

50

vias

51

catalyst

60

SiO ₂ layer

Claims (26)

Memory device, with: at least one Nanowire or nanotube or nanofiber access transistor. A memory device according to claim 1, wherein the Memory device is a resistive switching memory device. Memory device according to claim 2, wherein the resistively switching memory device a phase change memory with random access. Memory device according to claim 2, wherein the resistive switching memory device is a conductive bridging memory with random access. A memory device according to claim 2, wherein the Nanowire or Nanotube or Nanofiber Access Transistor directly contacted a switching active material of the resistively switching memory device. A memory device according to claim 5, wherein a contact area between the nanowire or nanotube or nanofiber access transistor and the switching active material of the resistively switching memory device a width and / or a length and / or has a diameter smaller than 1F. A memory device according to claim 5, wherein a contact area between the nanowire or nanotube or nanofiber access transistor and the switching active material of the resistively switching memory device a width and / or a length and / or has a diameter between 0.1F and 1F. A memory device according to claim 5, wherein a contact area between the nanowire or nanotube or nanofiber access transistor and the switching active material of the resistively switching memory device a width and / or a length and / or has a diameter between 0.2F and 0.5F. A memory device according to claim 5, wherein the switching active material is a chalcogenide or a chalcogenide compound material. Memory device according to claim 9, wherein the switching active material comprises a GST connection material. Memory device with: at least one nanowire or nanotube or nanofiber transistor with a vertically arranged nanowire or a vertically arranged one Nanotube or a vertically arranged nanofiber. A memory device according to claim 11, wherein the memory device is a resistively switching memory device is. A memory device according to claim 12, wherein the resistively switching memory device a phase change memory with random access. A memory device according to claim 12, wherein the resistively switching memory device is a conducting bridging memory with random access. A memory device according to claim 12, wherein one end of the vertically arranged nanowire or vertical arranged nanotube or the vertically arranged nanofiber directly a switching active material of the resistive switching memory device contacted. Memory device according to claim 15, wherein the other end of the vertically arranged nanowire or vertical arranged nanotube or the vertically arranged nanofiber directly contacted a power line. A memory device according to claim 11, wherein the transistor in addition has a transistor gate region. A memory device according to claim 17, wherein the transistor gate region is part of a word line. Resistively switching memory device with: one Nanowire or nanotube or nanofiber transistor, the direct contacted a switching active material; and means for changing the state of a nanowire or nanotube or nanofiber transistor. Method of manufacturing a memory device, which has the steps: - Making a nanowire or a nanotube or nanofiber; and - Produce a switching active material, which directly the nanowire or contacted the nanotube or nanofiber. Method according to claim 20, wherein the nanowire or the nanotube or the nanofiber part a nanowire or nanotube or nanofiber transistor. Method according to claim 21, wherein the nanowire or nanotube or nanofiber transistor additionally has a transistor gate region, and wherein the manufacturing of the nanowire or nanotube or nanofiber with respect to self-aligning the transistor gate region. Memory device according to claim 1, which capacitive Has elements for storing data. The memory device of claim 23, wherein the memory device is a DRAM memory device. A memory device according to claim 1, wherein the Transistor is a Si nanowire transistor. A memory device according to claim 25, wherein the transistor comprises an n-p-n or p-n-p-doped nanowire.