DE102007062092A1 - Data holding test executing system for resistive switching memory device i.e. conductive bridging RAM memory device, has applies bias voltage to conductive bridging RAM memory cell of memory device, before or during data holding test - Google Patents

Abstract

The system applies a bias voltage to a conductive bridging RAM memory cell (1) of a resistive switching memory device that is to be tested, before or during a data holding test. The memory cell is switchable between a high impedance condition and a low impedance condition i.e. ON condition, where the system applies the bias voltage to the memory cell before and/or during application of test signals to the memory cell. An anode (3) of the memory cell is connected with a plate of the memory device or a selection transistor of the memory cell dependent on bias voltage conditions. An independent claim is also included for a method for executing a data holding test for resistive switching memory devices.

Description

Field of the invention

The The following statements concern the technical field the resistor based on electrical resistance or resistively switching Memory cells and a system and method for testing the Data retention in resistive switching memory cells, such. B. Programmable Metallization Memories (PMC) or Conductive Bridging Random Access Memories (CBRAM).

Background of the invention

CBRAMs are used for example in MN Kozicki, M. Yun, L. Hilt, A. Singh, "Applications of programmable resistance changes in metal-doped chalcogenides", Electrochemical Society Proc., Vol. 99-13 (1999), 298 , described. The memory cells in CBRAMs generally comprise a solid electrolyte material with programmable resistive switchability and are therefore also referred to as Programmable Metallization Memory Cells (PMC) memory cells. In the electrolyte material of a resistive switching memory cells are mobile ions of an active material, such. As silver (Ag), copper (Cu) or zinc (Zn), which is influenced by an externally applied electromagnetic field.

The Storage of different states in a PMC memory cell is based on the development or cancellation of a conductive path in the electrolyte material between electrodes of the memory cell the base of an applied electric field. In CBRAM memory cells For example, an electrically conductive path may be in the solid electrolyte material be generated by a positive voltage applied to the electrodes the memory cell is applied, wherein the memory cell has a low-resistance state shows.

Of the Programming process is reversible and can be in a deletion process with reverse polarity with negative voltage again be undone, making it possible is, between a low-impedance and a high-impedance memory state to switch the memory cell back and forth. The physical processes, associated with it, only occur from certain threshold voltages on, so that voltages below these thresholds for reading the Cell information can be used. With such resistance based storage techniques, it is thus possible Information in a resistive switching memory cell to store an electrical resistance value.

storage products are usually extensive reliability tests before the product is delivered to the customer. In the case non-volatile storage is the data retention the storage device in the reliability tests important criterion. The typical data retention such Products (eg NAND / NOR flash memory) are in the range of several Years (often> 10 Years). Thus, testing under normal conditions is not an option represents.

Therefore The present invention is generally directed to technical Solutions for data retention tests resistively switching Storage techniques used for the market of non-volatile Memory can be used. The proposed solutions are for example CBRAM memory devices or PMC memory device as well as other resistively switching memory techniques applicable to use a bipolar operating mode.

• – Die Bestimmung des Beschleunigungsfaktors ist kritisch,
• – die Extrapolation der Daten schließt mögliche Fehler ein,
• – der Temperaturbereich ist beschränkt, und
• – während des Tests können zusätzliche Fehlermodi ausgelöst werden.

A common approach to non-volatile memory data retention testing is the temperature-accelerated data retention test, which determines an activation factor. The accelerated data retention test is performed at elevated temperatures because data loss in the memory device increases with increasing temperature. From this, the data retention capability of the memory device is extrapolated for normal operating conditions. For example, the test is well established for flash memory, but has the following disadvantages:

• - The determination of the acceleration factor is critical,
• - the extrapolation of the data includes possible errors,
• - the temperature range is limited, and
• - Additional failure modes may be triggered during the test.

The The present invention is directed to the reduction or elimination directed one or more of the above disadvantages. This Target can by means of the objects of the independent Claims can be achieved. Further embodiments of the present invention are each by articles of the dependent claims.

Short description of the present invention

According to one The basic idea of the present invention is a system and a method for carrying out a data retention test for resistively switching memory devices provided, wherein a bias voltage is applied to the tested memory device.

The present invention contemplates the use of bias on the memory device to speed up the data retention test. Thereby, the present invention, an almost beliebi enable test speed. The present invention may further enable to perform a data retention test at normal room temperature without the need to increase the temperature for thermal activation. Since the data holding test according to the present invention can be performed at normal temperature, thermal effects on the memory device can be avoided. Thus, the aforementioned disadvantages of thermal activation can be avoided.

One The principle underlying the present invention consists in the realization that the bias is connected to one or more Memory cells of the resistive switching memory device applied becomes a suitable alternative equivalence of the time factor represents. Because the data management of a progressive switching between ON and OFF states of the resistively switching Memory cell depends, increases with the change of the respective electrical Charges through the use of a bias the energy to, which supplied to the memory cell for this purpose becomes.

The additional energy due to the applied bias voltage is introduced into the memory cell, the switching processes in accelerate the memory cell. This requires a data retention test at a resistive switching storage device not years or Last days but can be completed in minutes or even seconds become.

A Interruption of the conductive connection or the conductor track in the resistive switching memory device can be forced by the bias voltage become. This will make the active material in the solid electrolyte material the resistively switching memory cell by a pure electrical Diffusion mechanism moved to a location within the memory cell, where it is needed without causing heat damage must arise in the memory cell.

With a data retention test according to the present invention can other diffusion processes except diffusion of the active material in the solid electrolyte material of the memory cell be avoided. The test effect can be arbitrarily accelerated, and an acceleration factor of more than a million times can be reached. Furthermore, unwanted Effects on the tested memory device after a data retention test undone in accordance with the present invention which, as a rule, are tests in thermally induced diffusion processes not the case.

embodiments of the present invention

According to one Embodiment of the present invention will be a system and a method of performing a data retention test for resistive switching memory devices with a Created variety of memory cells, with a bias to at least one memory cell of the tested memory device is created. This bias voltage can be applied to the memory cell of the tested Memory device are applied before other test signals the respective memory cells of the tested memory device be created. In other words, the bias at the beginning of the Test procedure to one or more memory cells of the tested memory device be created. Thus, a bias-accelerated data retention test to memory cells of a resistively switching memory device be performed.

According to one Another embodiment of the present invention can the bias-accelerated data retention test in parallel on one entire memory array of the memory device performed become. Alternatively, the accelerated by bias Data retention test only for one or more parts of a memory field the tested memory device are performed. Also alternatively, the bias-accelerated data retention test only on individual cells of a memory array of the memory device be performed.

By Testing parts of a memory field or just individual cells a memory array of the storage device may increase the risk of due to the increased temperature load conditional influence other parts (analog circuit devices) of the memory device, which is tested, reduced or even avoided. This useful effect is for embedded storage device of Importance.

According to one In another embodiment, the accelerated by bias Data retention test according to the present invention with a variety of tested memory devices in parallel be performed.

at another embodiment of the present invention becomes a plurality of memory cells of the resistively switching memory device programmed a defined state before the respective memory cells be subjected to a bias voltage. To keep the data retention non-volatile and quasi non-volatile behavior To check for a bias voltage to the respective memory cells be created to get results in a desired timeframe to obtain.

Brief description of the drawings

The attached drawings serve to provide a better understanding to enable the present invention. Based on the attached Drawings become embodiments of the present invention explained. There are also other than those in the drawings illustrated embodiments of the present invention conceivable within the scope of the independent claims defined scope of protection. The illustrated in the drawings Embodiments of the present invention are therefore not restrictive interpret. So will the present Invention will become apparent from the accompanying drawings with application examples a CBRAM memory device, although the present Invention also to other types of resistive switching memory devices or applicable to volatile memory. The Elements The drawings are not necessarily to scale. Like reference numerals designate the same or similar Components.

1A shows a schematic cross-sectional view of a CBRAM memory cell in a low-resistance state (ON state).

1B shows a schematic cross-sectional view of a CBRAM memory cell in a high-impedance state (OFF state).

2 shows a circuit diagram for the contacting of a memory cell of a CBRAM memory device;

3 shows a circuit diagram for testing a CBRAM memory device according to another embodiment of the present invention;

4 shows a circuit diagram for testing a CBRAM memory device according to an embodiment of the present invention; and

5A and 5B show schematic diagrams showing the basic behavior of data retention in a CBRAM memory device in the data retention test.

Detailed description the drawings

Before describing individual embodiments of the system and method according to the invention for testing resistively switching memory devices, the basic structure of a CBJ (CBJ) memory cell, its switching mechanism, circuit types and response to applied voltage pulses will be described by way of example with reference to the attached 1A and 1B to be discribed. The CBRAM technique is explained here as an example of resistive storage techniques.

In the 1A and 1B in each case the structure of a CBJ memory cell is shown in a schematic cross section. 1A shows the schematic structure of a CBRAM memory cell 1 in an electrically highly conductive or low-resistance state (ON state). The CBRAM memory cell 1 has a layer 2 of a solid electrolyte material with resistive switching properties, e.g. A chalcogenide material which can be prepared from GeSe, GeS, SiSe, SiS and / or AgSe or Ag-S. The chalcogenide material further comprises a metallic material of ions having the required solubility and high mobility in the chalcogenide material, such as e.g. For example, Ag, Cu or Zn ions which have been diffused or doped into the chalcogenide material. As a result, the chalcogenide material layer shows 2 the property, called ladder bridges or paths 6 to build.

The CBRAM memory cell 1 also has two electrodes 3 and 4 on, the chalcogenide layer 2 be added and in electrical contact with this. The chalcogenide material layer 2 is in direct contact with both electrodes 3 and 4 while the two electrodes 3 and 4 have neither a direct electrical contact nor an interface with each other, so that the chalcogenide material layer 2 the two electrodes 3 . 4 separates each other. About the electrodes 3 and 4 may generate electrical current or voltage pulses to the chalcogenide material layer 2 be created. Further, the electrodes 3 . 4 each connected to metal lines or metal interconnects (not shown) to connect the CBRAM memory cell to other devices, e.g. As transistors or other CBRAM memory cells to connect.

The first electrode 3 also in direct contact with the chalcogenide material 2 can be made of the movable active material, such. Cu, Ag or Zn, to be used as an inner donor for the chalcogenide material layer 2 to serve. The second electrode 4 may be made of a semiconductive or metallic material that has neither significant solubility nor significant mobility in the chalcogenide material such that the material of the second electrode 4 neither appreciably in the chalcogenide material layer 2 still penetrates with this mixes. Therefore, the second electrode becomes 4 from an inert material, such. W, Ti, Ta, TiN, Pt or doped Si, TaN, AL.

The atoms of the metallic material in the chalcogenide material may be metal-rich deposits or conglomerates 5 form. This metal-free deposits 5 are cluster-like, amorphous or nanocrystalline aggregates in which the metallic material is enriched. The resistive memory circuit mechanism of the CBRAM memory cell 1 is essentially due to a variation in the concentration of the metallic material in the chalcogenide material layer 2 is included.

Based on a chalcogenide material layer 2 with variable amount of metallic atoms together with cluster-like amorphous or nanocrystalline aggregations 5 can provide a wide resistance switching behavior of the CBRAM memory cell 1 be achieved. The variation of the total amount of deposits 5 that are in the chalcogenide material layer 2 allow a rapid modification of the physical and in particular the electrical properties of the CBRAM memory cell 1 , The resistive switching mechanism is thus based on the statistical formation of conductor bridges or paths 6 consisting of several metal-rich deposits 5 within the chalcogenide material layer 2 consist.

For programming the memory cell 1 can the upper electrode 3 charged with a positive voltage, and the lower electrode 4 for example, with a programming voltage of opposite polarity. In the example shown, the upper electrode 3 charged with a positive voltage and the lower electrode 4 with a negative voltage. Thus, mobile metal ions from the upper electrode into the chalcogenide material layer 2 penetrate, and electrons from the lower electrode 4 ,

Due to the continued application of an electrical write pulse to the CBRAM memory cell 1 Using the programming voltage decreases the size and / or density of these deposits 5 continue until some may come into contact with each other. This allows conductor bridges or paths 6 through the entire chalcogenide material layer 2 through, resulting in a higher conductivity through a metallic connection between the two electrodes 3 and 4 the memory cell 1 leads. This process programs the memory cell 1 and creates a situation of high conductivity between the electrodes 3 and 4 , thus the high-conductivity or low-resistance state (ON state) of the memory cell 1 represents. This state can be maintained for a longer storage time, so that the non-volatility of the programming is guaranteed.

1B shows a schematic CBRAM memory cell in a weakly conductive or high-resistance state (OFF state). The programming of the memory cell described above 1 in a highly conductive or low-resistance state is reversible. For this purpose, voltages (erasure voltages) corresponding to the voltages of the in 1A shown programming process, to the electrodes 3 . 4 the memory cell 1 applied, wherein in the illustrated example, the upper electrode 3 charged with a negative voltage and the lower electrode 4 with a positive voltage. Thus, the mobile metal ions pass over the negatively charged upper electrode 3 from the chalcogenide material layer 2 pulled, and the electrons are passed over the positively charged lower electrode 4 from the chalcogenide material layer 2 drawn.

Extracting the mobile metal ions from the chalcogenide material layer 2 causes a reduction in the number and / or size of metal-rich deposits 5 in chalcogenide material. The electrical bridging of the chalcogenide material layer 2 is decreased when the distances between the deposits 5 be enlarged. This is how the isolated deposits stand 5 no longer in contact with each other and do not form an electrically conductive bridge 6 more through the previously highly conductive and low-resistance chalcogenide layer 2 , This process leads to a deletion of the memory cell 1 and creates a situation of low conductivity between the electrodes 3 and 4 indicating the weakly conductive or high-resistance state (OFF state) of the memory cell 1 represents.

BL

= Bitleitung

WL

= Wortleitung

PL

= Plate

MBL

= Master Bitleitung

MWL

= Master Wortleitung

CBJ

= Conductive Bridging Junction oder Speicherzelle

In the following description of the 2 to 4 the following abbreviations are used and indicated as reference numbers in the drawing:

BL

= Bit line

WL

= Word line

PL

= Plate

MBL

= Master bit line

MWL

= Master word line

CBJ

= Conductive bridging junction or memory cell

2 shows a circuit diagram for addressing a memory cell of a CBRAM memory device. As described above, an integrated CBRAM memory device is based on CBJ (CBJ = Conductive Bridging Junction) memory cells that can be switched between a first high-resistance state and a second low-resistance state. For this purpose, a plurality of CBJ memory cells may be arranged in a field represented by word lines WL, bit lines BL and a plate PL. A dashed square in 2 denotes a memory cell CBJ in connection with a transistor Tc, which serves as a selection and control device of the memory cell CBJ.

Each memory cell CBJ can be connected via a transistor Tc to a corresponding bit line BL and to the plate PL or vice versa, while the gate of the transistor Tc is connected to the corresponding word line WL. The anode of the memory cell CBJ can be connected to a plate PL or to the transistor Tc. Thus, the transistor Tc can serve as a selection and control device of the memory cell. Various control signals can be output to the memory cell CBJ via the word line WL. A program / erase signal may be from a program / erase generator 7 to program data into the memory cell CBJ or erase data from the memory cell CBJ in the manner described above, and a read / detect signal can be output from a read / detect generator 8th are output to read data from the memory cell CBJ / capture.

The 3 to 4 show various circuits configured to test a CBRAM memory device according to an embodiment of the present invention. In both embodiments, a memory cell CBJ is in one field 9 which is represented by word lines WL, bit lines BL and a PL plate. Each memory cell CBJ may be connected via a transistor Tc to a corresponding bit line BL and to the plate PL, while the gate of the transistor Tc is connected to the corresponding word line WL. The anode of the memory cell CBJ may be connected to the plate PL or to the transistor Tc, depending on the applied bias conditions. Thus, the transistor Tc can serve as a selection and control device of the memory cell. This field 9 , which is represented by word lines WL, bit lines BL and a PL and comprises a plurality of memory cells CBJ, may be used in a resistively switching memory device, such as e.g. B. a CBRAM memory device integrated.

3 FIG. 12 shows a schematic circuit diagram suitable for testing a CBRAM memory device according to an embodiment of the present invention. In this embodiment, a master word line MWL and a master bit line MBL are integrated in the CBRAM memory device to form a CBJ memory cell array 9 to address or to contact. Thus, individual bit lines can be activated separately or in parallel.

Furthermore, control logic may be provided to control data retention tests performed on the CBRAM memory device. A data holding test may be performed by activating the corresponding master bit line MBL and the corresponding master word line MWL. Thus, individual memory cells CBJ of the memory cell array 9 to be activated. Furthermore, a DC voltage source may be provided for supplying a DC voltage Vacc to the memory cell CBJ of the CBRAM memory device under data retention test.

This control logic and this DC voltage source can be in a common module 10 combined, as in 3 shown. Both the control logic and the DC voltage source may be located inside or outside the CBRAM memory device. Alternatively, the control logic may be disposed within or on a chip of the CBRAM memory device, and the DC voltage source may be disposed within or on a chip of the CBRAM memory device. The CBRAM memory device being tested may include additional pads for contact with an external control logic and / or an external DC power source.

The DC bias voltage Vacc may be supplied to the memory cells CBJ via the corresponding master bit line MBL to shorten the duration of the data retention test. In this case, the bias voltage applied to the memory cell CBJ during the data hold test may be calculated according to the following equation: V (CBJ) = V (plate) - Vacc - V (Tc) where V (CBJ) is the voltage applied to the memory cell during the data retention test, V (plate) is the plate voltage, Vacc is the DC bias supplied to the corresponding master bit line MBL for the memory cell being tested, and V ( Tc) is the voltage drop across the transistor Tc. However, the voltage drop V (Tc) at the transistor Tc can also be neglected for this calculation, since it is slightly opposite to the DC bias voltage Vacc.

Various control signals can be output to the memory cell CBJ via the master bit line MBL. For example, from the programmer / erase generator 12 a program / erase signal is output to program data into the memory cell CBJ or to erase the memory cell CBJ, and a sense amplifier 11 can be provided to read / capture data content from the memory cell CBJ via the corresponding bit line BL.

4 Fig. 12 shows a circuit diagram suitable for testing a CBRAM memory device according to another embodiment of the present invention. In the 4 illustrated embodiment corresponds to in 3 illustrated embodiment, apart from an additional connection between the control logic in the common seed module 10 and the plate PL of the CBRAM memory device, which is manufactured by, for example, vias, as shown in FIG 4 by circular contact points within the memory cell array 9 are shown. Since the PL plate is below the image plane of 4 is arranged over the vias or through holes, which in 4 represented by circular contact points, a connection between the control logic in the common module 10 and the plate PL of the CBRAM memory device. Furthermore, at the in 3 illustrated embodiment, the DC voltage source apply a DC bias voltage Vacc only on the master bit line MBL, while at the in 4 1, the DC voltage source can apply a DC bias voltage Vacc to both the master bitline MBL and the master wordline MWL.

At the in 4 In the illustrated embodiment, a master word line MWL and a master bit line MBL are integrated in the CBRAM memory device to form the array 9 of memory cells CBJ to address or contact. Thus, individual bit lines can be activated separately or in parallel. Furthermore, control logic may be provided to control data retention tests performed on the CBRAM memory device. A data holding test may be performed by activating the corresponding master bit line MBL and the corresponding master word line MWL. Thus, individual memory cells CBJ of the memory cell array 9 to be activated. Furthermore, a DC voltage source may be provided to provide a DC bias voltage Vacc to the memory cells CBJ of the tested CBRAM memory device. The control logic and the DC voltage source could be in a common module 10 combined, as in 4 shown.

According to the in 4 In the illustrated embodiment, the DC bias voltage Vacc may be supplied to the memory cells CBJ via the plate PL of the CBRAM memory device in order to shorten the duration of the data retention test. At this time, the voltage applied to the memory cell CBJ during the data hold test can be calculated according to the following equation: V (CBJ) = Vacc - V (MBL) - V (Tc) where V (CBJ) is the voltage supplied to the memory cell being tested, V (MBL) is the voltage of the corresponding master bit line MBL, Vacc is the DC bias applied to the PL of the memory cell being tested, and V ( Tc) is the voltage drop across the transistor Tc. However, the voltage drop V (Tc) at the transistor Tc can also be neglected for this calculation, since it is slightly opposite to the DC bias voltage Vacc.

Various control signals can be output to the memory cell CBJ via the master bit line MBL. For example, from a programmer / erase generator 12 a program / erase signal is output to program data into the memory cell CBJ or erase the memory cell CBJ, and a sense amplifier 11 can be provided to read / capture the data content via the corresponding bit line BL from the memory cell CBJ.

5A shows a schematic diagram showing the basic behavior of the data retention in a CBRAM memory device under data retention test. Therein, the time for data loss in a tested CBRAM memory cell is shown in dependence on the bias voltage applied to the CBRAM memory cell. The scheme of 5A shows three different lines. The upper line shows the loss of information (the hold time) of a CBRAM memory cell without bias, the middle line the loss of information in a CBRAM memory cell with a bias voltage Vacc1, and the lower line the information loss in a CBRAM memory cell exposed to a bias voltage Vacc2, where Vacc2> Vacc1.

From a comparison of the lines in 5A It can be seen that the data loss in a CBRAM memory cell depends on the bias voltage Vacc applied to the memory cell under test. The higher the bias voltage Vacc applied to the memory cell, the faster the loss of information or loss of data in the memory cell.

5B FIG. 12 is a schematic diagram showing experimental results during a data retention test on a CBRAM memory device. FIG. The diagram of 5B shows two different lines starting from the time of writing data into a CBRAM memory cell. The upper line shows the time for the loss of information (or the data hold time) of a CBRAM memory cell without the application of a bias voltage (Vacc = 0 mV), and the lower line shows the information loss (or data hold time) timing scheme of a CBRAM memory cell. which is exposed to a bias voltage Vacc = -36 mV.

Out 5B It can be seen that the time for data loss in a CBRAM memory cell clearly depends on the bias voltage Vacc applied to the memory cell in the data hold test. The higher the bias voltage applied to the memory cell, the faster data loss in the memory cell will occur. Thus, the holding time of the CBRAM memory cell by applying a corresponding bias voltage to the tested CBRAM memory cell. As a result, the duration of a data retention test on CBRAM memory devices can be performed in a shorter time, which reduces test time and cost.

The The present invention can be used both in a process and in be implemented in a system having one or more of those described above Features according to the invention. Even though the present invention in the context of non-volatile CBRAM memory devices has been described, it can also on other types of memory devices are used, e.g. B. on flash, PCRAM devices or on volatile memories.

Even though special constructions and arrangements were discussed, It should be made clear that this is only an explanation should. A person skilled in the art will recognize that other constructions and arrangements are used without departing from the scope of the present invention. It is for a specialist in the relevant Area obvious that the invention also for a Variety of other purposes can be applied.

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited non-patent literature

• MN Kozicki, M. Yun, L. Hilt, A. Singh, "Applications of programmable resistance changes in metal-doped chalcogenides", Electrochemical Society Proc., Vol. 99-13 (1999), 298 [0002]

Claims (40)

System for carrying out a data retention test for resistive switching memory devices with a Variety of memory cells (CBJ) operating between a first, high-impedance State and a second, low-impedance state are switchable the system being designed to be connected to at least one Memory cell (CBJ) of the memory device under test a bias voltage (Vacc) create. The system of claim 1, wherein the system is for is designed, the bias voltage (Vacc) to the at least one memory cell (CBJ) of the memory device to be tested during the Create data retention tests. System according to one of the preceding claims, the system being adapted to apply the bias voltage (Vacc) to the at least one memory cell (CBJ) of the memory device to be tested create before the data retention test. System according to one of the preceding claims, the system being designed to provide the bias voltage (Vacc) to the at least one memory cell (CBJ) of the memory device create before and / or during test signals to the at least a memory cell (CBJ) of the tested memory device is applied become. System according to one of the preceding claims, wherein an anode of the at least one memory cell (CBJ) depends from the used bias conditions with a plate (PL) the memory device or a selection transistor (Tc) of at least a memory cell (CBJ) is connected. A system according to any one of the preceding claims, wherein the plurality of memory cells (CBJ) are in a number of fields ( 9 ) are arranged with word lines (WL) and bit lines (BL) and a master bit line (MBL) is integrated in the memory device, wherein the master bit line (MBL) is designed to at least one field (MBL) 9 ) of memory cells (CBJ) and to activate individual bit lines (BL) in parallel therein. System according to the preceding claim, wherein a master word line (MWL) as well as a master bit line (MBL) are integrated in the memory device, which are designed to store at least one field ( 9 ) of the memory cells (CBJ) and to activate individual word lines (WL) and / or individual bit lines (BL) therein separately or in parallel. System according to one of the preceding claims, the system being adapted to a number of memory cells (CBJ) of the memory device to program to a defined state, before the respective memory cells with the bias voltage (Vacc) applied become. System according to one of claims 6 to 8, the system being designed to override the bias voltage (Vacc) the corresponding master bit line (MBL) to the at least one Memory cell (CBJ) create. A system according to any one of claims 6 to 9, wherein the system is adapted to apply the bias voltage (Vacc) according to the equation: V (CBJ) = V (plate) - Vacc - V (Tc) to the memory cell where V (CBJ) is the bias voltage applied to the memory cell (CBJ), V (plate) is the plate voltage of the memory device, Vacc is the bias voltage applied to the corresponding master bit line (MBL) which contacts the memory cell (CBJ) to be tested, and V (Tc) which is the voltage dropped across the selection transistor (Tc) of the memory cell (CBJ) to be tested. System according to one of the preceding claims, further comprising a DC voltage source for supplying a Bias voltage (Vacc) to the at least one memory cell (CBJ) of the Storage device comprises. A system according to the preceding claim, wherein the DC power source is designed to be different Bias voltages (Vacc1, Vacc2) to the memory cells (CBJ) of the memory device deliver. System according to one of the preceding claims, further comprising a control logic for controlling the data retention test, is performed on the memory device comprises. System according to the preceding claim, wherein the control logic and the DC voltage source are in a common module ( 10 ) are combined. A system according to the preceding claim, wherein the Control logic and the DC power source outside, inside and / or are arranged on a chip of the storage device. A system according to any one of claims 6 to 15, wherein the system is designed to have the appropriate Master bit line (MBL) various control signals to the memory cell (CBJ). A system according to the preceding claim, wherein the System is designed to provide a programming signal the memory cell (CBJ) to output data to the memory cell (CBJ) to program, and / or a clear signal to the Memory cell (CBJ) to output data in the memory cell (CBJ) to delete. A system according to any one of the preceding claims, wherein the system further comprises a sense amplifier ( 11 ) for reading out data from the memory cell (CBJ). System according to the preceding claims 13 to 18, wherein the system further comprises an electrical connection between the control logic and the plate (PL) of the memory device comprises. A system according to the preceding claim, wherein the System is designed so that the bias voltage (Vacc) over the plate (PL) of the memory device to the memory cells (CBJ) is created. A system according to the preceding claim, wherein the system is adapted to apply the bias voltage (Vacc) according to the equation: V (CBJ) = Vacc - V (MBL) - V (Tc) to the memory cell (CBJ), where V (CBJ) is the bias voltage applied to the memory cell (CBJ), V (MBL) is the voltage of the corresponding master bitline (MBL) containing the memory cell (CBJ) to be tested Vacc is the bias voltage applied to the plate (PL) of the memory cell (CBJ) to be tested, and V (Tc) is the voltage dropped across the selection transistor (Tc) of the memory cell (CBJ) under test. System according to one of the preceding claims, wherein the memory device to be tested contact pads for the establishment of a contact with an external control logic and / or having an external DC voltage source. Method for carrying out a data retention test for resistive switching memory devices with a Variety of memory cells (CBJ) operating between a first, high-impedance State and a second, low-impedance state are switchable wherein a bias voltage (Vacc) is applied to at least one memory cell of the is applied to the memory device to be tested. The method of claim 23, wherein the bias voltage (Vacc) during the data retention test to the at least one Memory cell (CBJ) of the memory device is applied. Method according to one of claims 23 or 24, wherein the bias voltage (Vacc) before the data retention test to the at least a memory cell (CBJ) of the memory device is applied. Method according to one of claims 23 to 25, wherein the bias voltage (Vacc) to the at least one memory cell (CBJ) of the storage device is applied before and / or during Test signals to the at least one memory cell (CBJ) of the memory device be created. Method according to one of claims 23 to 26, wherein an anode of the at least one memory cell (CBJ) depends from the used bias conditions with a plate (PL) the memory device or a transistor (Tc) is connected. Method according to one of claims 23 to 27, wherein, when the plurality of memory cells (CBJ) in a number of fields ( 9 ) is arranged with word lines (WL) and bit lines (BL) and a master bit line (MBL) is integrated in the memory device, the master bit line (MBL) at least one field ( 9 ) are contacted by memory cells (CBJ) and individual bit lines (BL) activated in parallel. Method according to the preceding claim, wherein, when a master word line (MWL) and a master bit line (MBL) are integrated in the memory device, the master word line (MWL) and the master bit line (MBL) at least one field ( 9 ) of the memory cells (CBJ) and activate individual word lines (WL) and / or individual bit lines (BL) separately or in parallel. Method according to one of the claims 28 or 29, wherein the data retention test is carried out by activating the corresponding master bit line (MBL) and the corresponding master word line (MWL) to generate individual memory cells (CBJ) or fields (CBJ). 9 ) of memory cells of the memory device. Method according to one of claims 28 to 30, where the bias voltage (Vacc) over the corresponding master Bit line (MBL) to the at least one memory cell (CBJ) output becomes. Method according to one of claims 27 to 31, wherein the bias voltage (Vacc) over the memory cells (CBJ) via the plate (PL) is supplied to the storage device. A method according to any one of claims 28 to 32, wherein the bias voltage (Vacc) corresponds to the equation: V (CBJ) = V (plate) - Vacc - V (Tc) is applied to the memory cell, where V (CBJ) is the bias voltage applied to the memory cell (CBJ), V (Plate) is the memory voltage of the memory device, Vacc is the bias voltage applied to the corresponding master bit line (MBL) which contacts the memory cell (CBJ) to be tested, and V (Tc) is the voltage dropped at the selection transistor (Tc) of the memory cell (CBJ) to be tested. Method according to one of claims 23 to 32, wherein the bias voltage (Vacc) according to the equation: V (CBJ) = Vacc - V (MBL) - V (Tc) is applied to the memory cell (CBJ), where V (CBJ) is the bias voltage applied to the memory cell (CBJ), V (MBL) is the voltage of the corresponding master bitline (MBL) representing the memory cell (CBJ ), Vacc is the bias voltage applied to the plate (PL) of the memory cell (CBJ) to be tested, and V (Tc) is the voltage dropped across the selection transistor (Tc) of the memory cell (CBJ) to be tested. Method according to one of claims 23 to 33, being different via a DC voltage source Biases (Vacc1, Vacc2) to the memory cells (CBJ) of the memory device be created. Method according to one of claims 23 to 35, wherein the data retention test performed on the storage device is controlled by a control logic. Method according to one of claims 28 to 36, wherein different control signals via the corresponding Master bit line (MBL) to the at least one memory cell (CBJ) be issued. A method according to the preceding claim, wherein a programming signal to the at least one memory cell (CBJ) is output to program data into the memory cell (CBJ), and / or a clear signal is output to the memory cell (CBJ) is used to clear data in the memory cell (CBJ). Method according to one of claims 23 to 38, wherein a detection amplifier ( 11 ) Reads out data from the memory cells (CBJ) of the memory device (CBJ). Method according to one of claims 23 to 39, wherein the memory device via contact pads of the to be tested Storage device with an external control logic and / or with an external DC voltage source is brought into contact.