DE102011084024B4 - Method for providing a semiconductor structure with formation of a sacrificial structure - Google Patents

Abstract

A method of providing a semiconductor structure (100, 200) comprising the steps of: forming a sacrificial structure (110, 210) by etching a plurality of trenches (112, 212) from a first major surface (103, 203) of a substrate (102, 202 ), the sacrificial structure (110, 210) having one or more walls between the trenches (112, 212); Covering the plurality of trenches (112, 212) on the first main surface (103, 203) with a cover material (115, 215) to define voids in the substrate (102, 202) such that the cover material (115, 215) substantially at the first major surface (103) of the substrate (102), rather than falling to the bottom of the plurality of trenches (112, 212); Removing a portion of the substrate (102, 202) from a second major surface (104, 204) opposite the first major surface (103, 203) to a depth at which the plurality of trenches (112, 212) are present; and etching away the sacrificial structure (110, 210) by etching away the one or more walls from the second major surface (104, 204) of the substrate (102, 202) to form a recess (120, 220) having a bottom surface covering the covering material (115, 215).

Description

A number of applications in the field of microelectronics require patterning of semiconductor substrates down to deep regions of the substrate. Examples of these applications are in the field of power electronics (high voltage components), the field of sensor devices, electromechanical systems, microelectromechanical systems (MEMS), etc. The deep patterning of the semiconductor substrate is sometimes referred to as "3D integration". Generating cavities and / or recesses in the semiconductor substrate typically requires etching the substrate from one of its major surfaces or depositing new material on the major surface of the semiconductor substrate while masking the location or location of the future cavity or future cavity. In particular, when the cavities are obtained by an etching process, the dimensions of the cavities are subject to restrictions imposed by the etching process. For example, the so-called "deep trench" ("DT") etching process follows a relatively fixed relationship between a width of a trench to be etched and a depth of this trench. In cases where the closed cavity or partial closed cavity is to be obtained within the substrate, the formation of a capping layer to close the cavity typically requires expensive manufacturing processes due to the large dimensions of the cavities which are not satisfactorily closed with conventional semiconductor fabrication technologies can be.

The manufacture of a pressure sensor is intended to represent the problems encountered in an illustrative manner for all types of applications requiring similar 3-D patterning of a semiconductor substrate. Pressure sensors are typically used to control the pressure of a liquid or gas, such as gas. For example, to measure air. Pressure sensors typically provide an output signal that varies based on the pressure sensed by the pressure sensor. A type of pressure sensor includes a stand-alone pressure sensor coupled or connected to a sensor surface, such as a pressure sensor. B. an application specific integrated circuit (ASIC). This pressure sensor type is expensive to produce. The connection of this pressure sensor type with a sensor circuit is also expensive. Another type of pressure sensor is a pressure capsule (eg, a polysilicon plate) connected to a sensor circuit, such as a polysilicon plate. As an ASIC, during a BEOL process (BEOL = back-end-of-line = output side of the production line) is integrated. This type of pressure sensor is also expensive to manufacture because several additional mask levels are required to make the pressure sensor.

The US 2006/0093171 A1 shows a microphone and a manufacturing method thereof, wherein the microphone has a membrane with elastic polymers on the edge thereof.

The US 2008/0038921 A1 shows a method for producing a semiconductor device, in particular a MEMS device.

The DE 10 2007 033 717 A1 shows a method for producing a structure by three-dimensional processing of a flat member.

Furthermore, it is also on the pamphlets US 6,387,772 B1 . DE 10 2009 039106 A1 . US 2008/0178681 A1 . US 7,555,956 B2 such as US 6,012,336 A refer who disclose other semiconductor devices or manufacturing method thereof.

Semiconductor structures fabricated by 3-D integration often require electrical isolation between different parts of the semiconductor structure. This requires generating or providing an insulating region as deep as possible in the semiconductor substrate, so that conventional surface-oriented methods, such. B. doping, are unsuitable.

It is the object of the present invention to provide a method of providing a semiconductor structure, a microelectromechanical sensor structure and a semiconductor structure with improved characteristics.

The object is solved by the features of the independent claims. Further developments can be found in the dependent claims.

An embodiment of the invention addresses a method of providing a semiconductor structure, the method comprising forming a sacrificial pattern by etching a plurality of trenches from a first major surface of a substrate. The method further includes covering the plurality of trenches on the first major surface with a cap material to define voids in the substrate, removing a portion of the substrate from a second major surface opposite the first major surface to a depth at which the plurality of trenches available; and etching away the sacrificial structure from the second major surface of the substrate.

The accompanying drawings are included to provide a further understanding of the embodiments and are in this description contain and form part of it. The drawings illustrate embodiments and together with the description serve to explain principles of the embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale. Like reference numerals designate corresponding like parts.

Preferred embodiments of the present invention will be explained in more detail below with reference to accompanying drawings. Show it:

1A to 1D various stages of an embodiment of a manufacturing process of a semiconductor structure;

2A to 2F various stages of another embodiment of a manufacturing process of a semiconductor structure;

3A a partial perspective top view of a semiconductor structure during a stage of a manufacturing process in which a plurality of trenches were etched at a first major surface;

3B a partial perspective bottom view of a semiconductor structure during a stage of a manufacturing process in which a sacrificial structure has been removed;

4A and 4B Cross sections through cavities and two variants of internal structures in the cavities;

5 a perspective view of a variant of an internal structure;

6A to 6D various stages of an application process and a subsequent etching of a semiconductor substrate;

7A to 7F a process sequence for electrically isolating pressure sensitive structures as currently used by the inventor's employer;

8th a sensor structure implemented using a semiconductor structure;

9 a cross-section through a substrate with cavities with tapered cross sections;

10 a cross-section through a semiconductor structure with cavities and tapered fins between the cavities;

11 a cross-section through a semiconductor substrate to illustrate a relationship of the dimensions of a first cavity and a second cavity;

12 a plan view of a semiconductor substrate having a buried cavity and an adjacent open cavity;

13 a perspective cross-section of a semiconductor structure having an electrical connection to an internal structure in a cavity; and

14 a portion of a semiconductor wafer having a plurality of semiconductor structures prior to a singulation process for obtaining individual semiconductor structures.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such. As "top" and "bottom", "front" and "rear", "front", "rear", etc. used with reference to the orientation of the figure (s) described. Because components of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only and is by no means limiting. It will be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is therefore not to be considered in a limiting sense and the scope of the present invention is defined by the appended claims.

It should be understood that the features of the various exemplary embodiments described herein may be combined with each other unless specifically noted otherwise.

1A to 1D illustrate various stages of a method of providing a semiconductor structure 100 in four part drawings dar. 1A shows a result of an etching process that takes place in a first main surface 103 a semiconductor substrate 102 is carried out. The etching process creates a plurality of trenches 112 extending from the first main surface 103 to a depth d in the substratum 102 extend. The etching of the trenches 112 can be performed by the deep trench (DT) process. The deep trench etching process results in relatively steep walls of the plurality of trenches 112 , The depth d of the majority of trenches 112 can be controlled by selecting a width w from each of the plurality of trenches 112 , Consequently, the majority of trenches 112 approximately the same width w if a substantially uniform depth d of the plurality of trenches is desirable.

The etching on the majority of trenches 112 that leads to a victim structure 110 is formed. The sacrificial structure 110 has substrate material remaining after etching the plurality of trenches 112 between two of the plurality of trenches 112 took place. Typically, the spacing is the majority of trenches 112 relatively narrow, so that the victim structure 110 has one or more thin walls between the trenches. 1A represents the sacrificial structure 110 As a field of silicon fins dar. It should be noted that 1A to 1D at the furthest right trench are broken for illustration purposes. The majority of trenches 112 and the sacrificial structure 110 could continue to the right in the substrate 102 in 1A to 1D extend. A lateral extent (ie in the left-right direction in 1A to 1D ) of the plurality of trenches 112 could be 1 μm, 10 μm, 100 μm or 1000 μm and assume values between the mentioned values or even outside the mentioned range of 1 μm to 1000 μm. The length of the trenches 112 in a direction perpendicular to the plane of the drawing is typically not significantly limited by limitations.

The etching of the plurality of trenches 112 Can be used to the substrate 102 to structure with an array of sacrificial (sub) structures. The shape and dimensions of the array of sacrificial (sub) structures can be relatively accurately controlled in the two lateral directions parallel to the first major surface on the chip of the substrate 102 and even to some extent in the third direction, e.g. B. the direction of the depth d of the plurality of trenches 112 , The sacrificial structure 110 and / or the arrangement of the sacrificial (sub) structures may be considered as an auxiliary or intermediate means for ultimately obtaining a larger structure in the semiconductor substrate 102 , such as B. a cavity or a recess.

1B shows another stage of the method for providing a semiconductor structure. The majority of the trenches 112 was at the first main surface 103 with a cover material 115 covered to voids in the substrate 102 define. The covering of the plurality of trenches 112 can be achieved for example by an epitaxy process or a Venetia process. The cover material 150 may be identical to the material of the substrate 102 , z. As silicon or other semiconductor material. Alternatively, the cover material may be 115 differ from the substrate material, such as. For example, silica, metal, an oxide of a metal or even a polymer. The walls or slats that are part of the sacrificial structure 110 are, wear the cover material 115 so that the cover material 115 essentially at the first main surface 103 of the substrate 102 stays, rather than to the bottom of the majority of trenches 112 collapsing. One of several options for covering the plurality of trenches 112 is the use of a H-burning process (H-bake-Process).

The H-firing process makes it possible, even relatively large trenches with the cover material 115 cover so that the majority of trenches 112 are completely closed at their outermost ends, the previously to the first main surface 103 were open.

1C shows a result of another stage of the method for providing the semiconductor structure. The substrate 102 was processed starting from the second main surface 104 ( 1B ) by removing a portion of the substrate and thus thinning the substrate. Processes leading to thinning of the substrate 102 are typically mechanical grinding of the substrate 102 or a chemical mechanical polishing CMP process). The thinning of the substrate 102 thus results in the generation of a new second major surface 105 ( 1C ). The removal of the part of the substrate 102 typically involves a layer of the substrate 102 having a thickness sufficient to allow the plurality of trenches 112 after completion of the removal appears. In other words, the removal of a substrate material extends at least from the former second major surface 104 to the depth d where most of the trenches are present. The majority of the trenches 112 has extremities ending to the new second major surface 105 are open.

It should be noted that there is typically a standard semiconductor device manufacturing process arranged between the stages passing through 1B and 1C are shown. The standard semiconductor manufacturing process has z. B. structuring the first major surface 103 of the substrate 102 to define differently doped regions and / or layers. For example, the first main surface 103 undergo a CMOS process.

1D shows the semiconductor structure 100 in a schematic way after completing the method of providing the semiconductor structure 100 , The sacrificial structure 110 was removed by Etching away the walls or slats. This etching will be from the side of the new second major surface 105 performed, for example by a wet etching process. Thus, a large opening or recess 120 receive. The shape and dimensions of the cavity 120 can be relatively accurately controlled by the shape and dimensions of the sacrificial structure 110 , The sidewalls of the cavity 120 may be formed to be substantially steep or orthogonal to the new second major surface 105 what is a task that is difficult to fulfill with other voiding methods. Since the sacrificial structure has predominantly thin walls or fins, which provides a large surface area for an etchant, the process of etching away degrades the sacrificial structure 110 the side walls and / or the bottom of the cavity 120 barely. In any case, an effect on the side walls and the bottom of the cavity 120 caused by the etching away of the sacrificial structure 110 be predicted in a relatively accurate manner, so that this effect can be taken into account when measuring the dimensions of the cavity 120 and / or the plurality of trenches 120 to get voted.

This in 1A to 1D The method illustrated and described offers good integration capability and scalability of the geometric dimensions of the cavity 120 , As an example, the cavity 120 be used as a pressure channel for a pressure sensor. The provision of a sufficiently large pressure channel from the gas or liquid to the actual pressure sensing element reduces the risk that the pressure channel will become clogged, e.g. By small particles that may be present in the gas or liquid. Consequently, the sensor device is reliable in terms of pressure measurement, even in contaminated environments.

The method of providing a semiconductor structure 100 as it is in 1A - 1D , does not require a lithography step from the second major surface 104 or other suitable methods for subsequently performing a wet chemical or dry etching process. The step of etching away the sacrificial structure 110 is typically a KOH etching process (KOH = potassium hydroxide) from the new second major surface 105 , The proposed method uses DT etching from the first major surface 103 (Front surface) in front of the 1A illustrated stage.

The proposed method uses a DT etching process from the front surface, which simultaneously creates the cavities for pressure measurement and, fittingly, sacrificial structures. The sacrificial structure (s) include a region of silicon fins that are dissolved by a chemical wet etching step after thinning of the wafer. The lamellae for the pressure chambers are etched less deep, the lamellae for the sacrificial structures are etched "as deeply as possible" - this can be controlled across different widths of the trench openings. The different widths of the etched trenches allow selective closing of the pressure chamber (s) without closing the lamellae of the sacrificial structures.

Phototechnology from the back surface may be omitted. Thus, for a pressure sensor, the benefits of volume access from the back surface are used without having to use more complex and expensive processes. The cavity for volume access and its dimensions can be freely shaped and chosen.

The possibility of omitting a back surface lithography step makes the described method competitive in terms of production cost and complexity. The method provides a low complexity integration scheme compared to existing solutions. Good medium compatibility can be achieved when the cavity 120 certain liquids or gases is exposed, as the sidewalls and the bottom of the cavity 120 typically made of a single material. This also allows the sealing of the side walls and the bottom of the cavity 120 with a protective coating. When the structure is buried or to the new second main surface 120 is open, the semiconductor structure further requires little space at the first main surface 103 of the substrate 102 , If that through the cover material 115 formed layer is sufficiently thick, this layer can be used as a substrate for microelectronic circuits such. As CMOS circuits, are used. In this way, the provision of the cavity requires 120 little additional surface area of the semiconductor structure, if any. Finally, only about two additional mask layers are necessary to perform the proposed method if it is embedded in and concurrently performed with a larger semiconductor device fabrication process.

In summary, this is structured in 1A to 1D The method illustrated in FIG. 1 illustrates a silicon lamella region by a DT etch, appropriately closes the region, and removes the silicon lamination region at a later time, particularly after thinning a silicon wafer on which the semiconductor structure is to be formed. The removal of the silicon fins region results in the opening of a wide trench. The dimension of the trench can be freely configured by the DT etch.

In accordance with some aspects of the teachings disclosed herein, it is proposed To integrate pressure sensor element (or other MEMS components) as a buried structure on an ASIC chip. In the case of a pressure sensor, the pressure information is provided from the back surface (or "second major surface"). Upon completion of the ASIC process, the back surface of the wafer is ground until a channel opens to the pressure cell.

In addition to the integration suitability already mentioned, the teachings disclosed herein offer good scalability of the geometric dimensions of the pressure channel while maintaining the advantages of vertical integration of the pressure cell. Thus, the concept is suitable for applications where clogging of narrow pressure channels due to external fluids would compromise the reliability of the pressure measurement.

2A and 2 B show six stages of an embodiment of a method for providing a semiconductor structure 200 , 2A shows a semiconductor substrate 202 after the majority of trenches 212 was etched, starting at the first major surface 203 of the substrate 202 , The majority of the trenches 212 has trenches of different trench width. The outermost trenches 212 are relatively narrow, while the second trench and the second-last trench (when counted from left to right) are slightly larger in width. Six trenches of the majority of trenches 212 , which are in the middle, have a relatively large width. The different trench widths have an influence on the individual depth of the different trenches 212 , The outermost trenches do not reach that far into the substrate 202 like the second ditch and the second-last ditch. The six central trenches have the greatest depth. The sacrificial structure 210 has most of the walls or fins that have been formed as the majority of trenches 212 was etched, except the outermost walls or slats 211 , As it is in all fields of 2A and 2 B indicated by the break line, could be the substrate 202 and the majority of trenches 212 be extended, so that the victim structure 210 spans a relatively large distance from left to right.

2 B represents the substrate 202 at an intermediate stage of the method of providing a semiconductor structure. Selective portions of the substrate 202 and possibly the side slats 211 were doped to form arrays of differently doped semiconductor regions in the substrate 202 to obtain. For example, a pn junction in the side fins 211 be formed to a part of the side slats 211 from the rest of the substrate 202 electrically isolate. A nitride topcoat 260 was on the sidewall of the majority of trenches 212 applied. Furthermore, a closing material 217 at the opening of the trenches 212 applied. Due to the different widths of the majority of trenches 212 , the first trench, the second trench, the trench next to the rightmost trench, and the rightmost trench are formerly passed through the closure material 217 closed as the six middle ditches. Thus, by timing the application process of the closure material 210 to the moment when the four outer trenches are completely closed, but the six middle trenches are still open, selective closing of at least one trench of smaller dimensions than the other trenches of the plurality of trenches are achieved.

2C shows one stage of the process after the topcoat 216 and the closing material 217 from the open trenches, ie the six central trenches, which have a larger width, were removed. As it is in 2C is apparent, became a part of the closing material 217 also removed from the narrower trenches; however, the narrow trenches are still closed. The removal of the closing material 217 is configured and controlled so that the narrower trenches remain closed. This leads to the cover layer materials 216 remain in the narrow trenches unaffected by the removal of the cover sheet material, as the agent used for this purpose will not be able to penetrate the narrow trenches.

In 2D is the substrate 202 shown after the cover material 215 on a part of the main surface 203 was applied to the larger trenches of the majority of trenches 202 cover. For this purpose, an H-burning process can be used.

The majority of the trenches 212 is now completely closed and thus forms a plurality of cavities in the substrate 202 ,

Between 2D and 2E For example, the method of providing a semiconductor structure may perform a number of method steps typical of the fabrication of semiconductor devices. Typically, a number of layers 230 on the first main surface 203 generated. By way of example, three layers have been produced, namely an insulator layer, a metal layer and e.g. B. a semiconductor layer. The insulator layer may be formed of, for example, silicon oxide while the additional layers 230 z. B. can form a CMOS circuit.

Another step between the in 2D and 2E Stages is a BEOL process and thinning of the semiconductor substrate 202 from the second main surface 204 ( 2D ) to a new second main surface 205 to obtain ( 2E ). The thinning removes the substrate material to a depth in the substrate where there is a portion of the plurality of grains. These trenches 212 are therefore opened as a result of the thinning process. The leftmost trench and the rightmost trench have a smaller depth than the other trenches and therefore will not open during the thinning process. The leftmost trench and the rightmost trench remain as closed cavities or "buried" cavities. It should be noted that it is not necessary to have both the leftmost cavity and the rightmost cavity. The teachings disclosed herein are also valid if only one cavity is provided from the leftmost cavity and the rightmost cavity by the method.

In 2F is the resulting semiconductor structure 200 shown. The sacrificial structure 210 was removed, as well as any topcoat material present in the trenches that during the thinning process to the new second major surface 205 were opened. The removal of the sacrificial structure 210 leads to the formation of a cavity or a recess 220 , This cavity or the recess 220 can be used for a variety of purposes. Examples are the pressure channel in the above-mentioned pressure sensor, a receiving element for example for a narrow rod to measure mechanical forces, a cavity required in a power electronic or high voltage component, etc.

The leftmost and rightmost trench are still in the form of cavities, that of the large cavity or recess 220 through side walls or slats 211 are separated. In an exemplary configuration of the semiconductor structure as a pressure sensor, the cavities formed by the leftmost and rightmost trench provide pressure chambers. When the pressure in the main cavity 220 varies, the sidewall becomes 211 distracted accordingly. This results in a deviation of a width of the leftmost and rightmost trench. Either the deflection of the side wall 212 or the deviation of the trench width can be measured by suitable conversion elements, for example in the additional layers 230 are provided.

The cover layer material 216 serves as a barrier to the etching process through the sacrificial structure 210 was removed. Thus, the overcoat material present in the second trench and in the second-last trench acts as a protection for the sidewalls 211 concerning the etching process performed by the second main surface. Thus, the shape of the sidewalls obtained during DT etching may be that of the first major surface 203 in front 2A was essentially maintained. The side walls 211 can therefore be generated with relatively high accuracy.

As it is in 2F it can be seen is the bottom of the cavity 220 mainly from the cover material 215 composed. Remains of the closing material are still in the corners of the cavity 217 and the cover sheet material 216 which were used to selectively close the former second trench and the former second-last trench selectively. This can for example be exploited as an electrical insulation of the cover material 215 the bottom of the cavity 220 over other parts of the substrate 202 ,

The process according to 2A - 2F solves the problem that etching the silicon between 2E and 2F also a lamella at the borders of the large cavity 220 If this lamella is exposed directly to the etchant. For this reason, an additional sacrificial fin is provided which prevents the fin, which is to be used as a pressure-sensitive membrane, from being affected by the etchant. This process, in an ideal case, requires only one mask layer for molding the pressure sensor element. It thus offers a favorable option for designing the back surface volume access in terms of its dimensions, so that it can not be clogged easily by particles or liquids.

3A shows a perspective view of the semiconductor substrate 202 and its first major surface 203 , 3A corresponds broadly 2A with the exception that for clarity and presentation purposes in 3A only seven trenches are shown instead of 10 trenches. It should be noted that 3A only a schematic representation is and not to scale.

3B shows a perspective view of the semiconductor substrate accordingly 3F , The perspective view shows the new second main surface 205 and the cavity 220 , The closed cavities left and right of the large cavity 220 are shown as a dashed line. As explained above, the closed cavities are from the large cavity 220 through the side walls 211 separated. At the bottom of the large cavity 220 is a strip to watch the closing material 217 and the cover sheet material 216 having.

The method of providing a semiconductor structure as shown in FIG 1 has been illustrated and explained, as well as the semiconductor structure 100 . 200 themselves can be improved by some aspects related to the description of 2A and 2 B and some of the following aspects.

The majority of trenches 112 . 212 may comprise at least one trench of smaller dimension than other trenches of the plurality of trenches.

The method may further include selectively closing the at least one smaller dimension trench at the first major surface 103 . 203 after forming the sacrificial structure 110 . 210 ,

The selective closing may occur before the step of covering the plurality of trenches 112 . 212 and the method may further comprise the steps of: applying a topcoat material 216 in the majority of trenches 112 . 212 prior to selectively closing the at least one trench of smaller dimension; Performing the selective closure of the at least one trench of smaller dimension; and removing the cover sheet material 216 from the other trenches. During the etching of the second main surface 104 can be sacrificial structures 110 . 210 adjacent to trenches in which the top layer material 216 can be etched away, and in structures bounded by trenches in which the cover sheet material has been retained, can be retained.

The method may further comprise the steps of: etching another trench adjacent to the array of sacrificial structures 110 . 210 , simultaneously with the etching of the plurality of trenches 112 . 212 , The further trench and the at least one cavity 120 . 220 can a wall 211 form between themselves, after etching away the structure of sacrifice 110 . 210 ,

With reference to 14 the method may further comprise the steps of: etching a chip singulation trench 1420 in the substrate 102 . 202 to a slat 211 between the chip singulation trench 1420 and a cavity 120 . 220 . 1400 to define by etching away the sacrificial structures 110 . 210 from the second main surface 104 . 204 is formed; and singulating the semiconductor structure at the chip singulation trench 1420 ,

With reference to 4A and 4B can be a cavity 120 . 220 . 412 . 442 . 1112 . 1400 by etching away the sacrificial structures from the second major surface 104 . 204 is formed, have a tapered cross-section.

The method may further comprise the steps of: forming a circumferential trench 413 . 443 that has an internal structure 413 . 443 surrounds, adjacent to a region of the plurality of trenches 112 . 212 ; and covering the circumferential trench with a cover material.

The method may further comprise, prior to forming the sacrificial structure, the steps of: forming an electrically insulating layer on the first major surface of the substrate; and applying an outer layer of substrate material to the electrically insulating layer. The etching of the plurality of trenches may be performed from a surface of the outer layer and may extend at least to the electrically insulating layer.

• • Bilden einer Opferstruktur 110, 210 durch Ätzen einer Mehrzahl von Gräben 112, 212 von der ersten Hauptoberfläche 102, 202 der Sensorstruktur;
• • Abdecken der Mehrzahl von Gräben an der ersten Hauptoberfläche 102, 202 mit einem Abdeckungsmaterial 115, 215, um Hohlräume in der Sensorstruktur zu definieren;
• • Entfernen eines Teils der Sensorstruktur von einer zweiten Hauptoberfläche 104, 204 gegenüber der ersten Hauptoberfläche 102, 202 zu einer Tiefe, in der (zumindest einige) der Mehrzahl von Gräben 112, 212 vorliegen;
• • Wegätzen der Opferstrukturen 110, 210 von der zweiten Hauptoberfläche 104, 204 der Sensorstruktur; und
• • Bereitstellen eines Wandelelements zum Wandeln der mechanischen Größe zu der elektrischen Größe an einer Wand 211 eines Hohlraums 120, 220, 1400, der durch Wegätzen der Opferstruktur 110, 210 gebildet wird.

Concentrating on the sensor structures, a method of providing a sensor structure for converting a mechanical quantity to an electrical quantity may include the steps of

• • forming a sacrificial structure 110 . 210 by etching a plurality of trenches 112 . 212 from the first main surface 102 . 202 the sensor structure;
• Covering the plurality of trenches at the first major surface 102 . 202 with a cover material 115 . 215 to define cavities in the sensor structure;
• • removing part of the sensor structure from a second major surface 104 . 204 opposite the first main surface 102 . 202 to a depth in which (at least some) of the plurality of trenches 112 . 212 available;
• • etching away the sacrificial structures 110 . 210 from the second main surface 104 . 204 the sensor structure; and
• Providing a conversion element for converting the mechanical quantity to the electrical quantity on a wall 211 a cavity 120 . 220 . 1400 by etching away the sacrificial structure 110 . 210 is formed.

• • Das Ätzen er Mehrzahl von Gräben 112, 212 kann ein Strukturieren der Sensorstruktur mit einer Anordnung von Opferstrukturen 110, 210 aufweisen, wobei die Anordnung eine Abmessung des Hohlraums 120, 220, 1400 definiert.
• • Das Abdecken der Mehrzahl von Gräben 112, 212 kann zumindest entweder einen Epitaxie-Prozess oder einen Venetia-Prozess aufweisen.
• • Das Verfahren kann ferner ein Erzeugen von Halbleiterstrukturen auf der ersten Hauptoberfläche nach dem Abdecken der Mehrzahl von Gräben 112, 212 aufweisen.
• • Die Mehrzahl von Gräben kann zumindest einen Graben mit einer kleineren Abmessung als andere Gräben der Mehrzahl von Gräben 112, 212 aufweisen, und das Verfahren kann ferner folgenden Schritt aufweisen: selektives Schließen des zumindest einen Grabens mit der kleineren Abmessung an der ersten Hauptoberfläche nach dem Bilden der Opferstruktur 110, 2120.
• • Das selektive Schließen kann vor dem Schritt des Abdeckens der Mehrzahl von Gräben 112, 212 sein, wobei das Verfahren ferner vor dem Schritt des Abdeckens folgende Schritte aufweisen kann: Aufbringen eines Deckschichtmaterials 216 in der Mehrzahl von Gräben 112, 212 vor dem selektiven Schließen des zumindest einen Grabens mit der kleineren Abmessung; Entfernen des Deckschichtmaterials 216 von den anderen Gräben; wobei während des Ätzens von der zweiten Hauptoberfläche Opferstrukturen 110, 210 benachbart zu den anderen Gräben, in denen das Deckschichtmaterial 216 entfernt wurde, weggeätzt werden können und Strukturen, die durch die Gräben begrenzt sind, in denen das Deckschichtmaterial 216 beibehalten wurde, können beibehalten werden (d. h. werden nicht weggeätzt).
• • Das Verfahren kann ferner folgenden Schritt aufweisen: Ätzen eines weiteren Grabens benachbart zu dem Feld der Opferstrukturen; wobei die Wand 211, die das Wandelelement aufweist, zwischen dem weiteren Graben und dem zumindest einen Hohlraum gebildet werden kann nach dem Ätzen der Opferstruktur.

The sensor structure is or typically includes a type of semiconductor substrate. The provision of the conversion element on the wall of the cavity means that the conversion element is arranged to detect and possibly quantify effects on the wall caused by the mechanical size. Therefore, the term "on a wall of a cavity" mainly refers to a functional relationship between the wall element and the walls, not necessarily a spatial relationship.

• • The etching of a plurality of trenches 112 . 212 can be a structuring of the sensor structure with an array of sacrificial structures 110 . 210 , wherein the arrangement has a dimension of the cavity 120 . 220 . 1400 Are defined.
• • Covering the majority of trenches 112 . 212 may have at least either an epitaxy process or a Venetia process.
• The method may further include generating semiconductor structures on the first major surface after covering the plurality of trenches 112 . 212 exhibit.
• The plurality of trenches may include at least one trench having a smaller dimension than other trenches of the plurality of trenches 112 . 212 and the method may further comprise the step of: selectively closing the at least one trench of smaller dimension on the first major surface after forming the sacrificial structure 110 . 2120 ,
• The selective closing may be performed before the step of covering the plurality of trenches 112 . 212 and the method may further comprise, prior to the capping step, the steps of: applying a topcoat material 216 in the majority of trenches 112 . 212 before selectively closing the at least one trench of the smaller dimension; Removing the cover sheet material 216 from the other trenches; wherein during the etching of the second main surface sacrificial structures 110 . 210 adjacent to the other trenches in which the cover sheet material 216 was removed, can be etched away and structures that are bounded by the trenches in which the covering material 216 can be maintained (ie not etched away).
• The method may further comprise the step of: etching another trench adjacent to the array of sacrificial structures; being the wall 211 having the conversion element, can be formed between the further trench and the at least one cavity after the etching of the sacrificial structure.

• • ein Substrat 102, 202 mit einer Hauptoberfläche 103, 203;
• • einen ersten Hohlraum 120, 220, 1400, der in dem Substrat 102, 202 gebildet ist;
• • einen zweiten Hohlraum, der in dem Substrat nahe dem ersten Hohlraum gebildet ist und durch eine Lamelle 211, 1311, 1411 von dem ersten Hohlraum getrennt ist.
• • Der erste Hohlraum kann eine erste Hohlraumabmessung aufweisen und der zweite Hohlraum kann eine zweite Hohlraumabmessung aufweisen. Die erste Hohlraumabmessung und die zweite Hohlraumabmessung können sich in einer Richtung parallel zu der Hauptoberfläche erstrecken und ein Verhältnis zwischen der ersten Hohlraumabmessung und der zweiten Hohlraumabmessung kann gleich oder größer 10 sein.
• • Der erste Hohlraum kann eine Breite zwischen 1 μm und 1 mm aufweisen und der zweite Hohlraum kann eine Breite zwischen 10 nm bis 800 nm aufweisen, um ein beispielhaftes Verständnis der Größenordnung der Abmessung zu geben.
• • Der erste Hohlraum kann ein Druckeinlass sein und der zweite Hohlraum kann ein geschlossenes Druckreferenzvolumen sein.
• • Der erste Hohlraum kann zu der Hauptoberfläche des Substrats offen sein und kann einen Öffnungswinkel aufweisen, der in dem Bereich von 60 Grad bis 110 Grad enthalten ist (z. B. 70 Grad, 80 Grad, 85 Grad, 90, Grad, 95 Grad, 100 Grad sowie Werte zwischen diesen ausgewählten Werten).
• • Der zweite Hohlraum kann mit einem Deckschichtmaterial 216 überzogen sein.

A microelectromechanical sensor structure may be obtained by a method in accordance with one or more of the aspects according to the teachings disclosed herein. The microelectromechanical sensor structure may be adapted to convert a mechanical quantity to an electrical quantity and having the following features;

• • a substrate 102 . 202 with a main surface 103 . 203 ;
• • a first cavity 120 . 220 . 1400 in the substrate 102 . 202 is formed;
• A second cavity formed in the substrate near the first cavity and through a fin 211 . 1311 . 1411 is separated from the first cavity.
• The first cavity may have a first cavity dimension and the second cavity may have a second cavity dimension. The first cavity dimension and the second cavity dimension may extend in a direction parallel to the main surface, and a ratio between the first cavity dimension and the second cavity dimension may be equal to or greater than 10.
• The first cavity may have a width between 1 μm and 1 mm, and the second cavity may have a width between 10 nm and 800 nm, to give an exemplary understanding of the magnitude of the dimension.
• The first cavity may be a pressure inlet and the second cavity may be a closed pressure reference volume.
• The first cavity may be open to the main surface of the substrate and may have an aperture angle comprised in the range of 60 degrees to 110 degrees (eg, 70 degrees, 80 degrees, 85 degrees, 90 degrees, 95 degrees , 100 degrees and values between these selected values).
• • The second cavity can be covered with a cover material 216 be covered.

With respect to a semiconductor structure, it may include a semiconductor substrate and a cavity in the semiconductor substrate bounded by a bottom and a side wall. The bottom may have a portion adjacent to a transition between the bottom and the side wall. The portion may include a film material different from the substrate material of the semiconductor substrate.

In order for there to be a difference between the film material and the substrate material, it may be enough for the second one to be distinguishable from the rest of the bottom surface, even if the same material is similar in the chemical sense. For example, the portion could have a different crystal structure or orientation than the bottom of the cavity. The transition between the bottom and the side wall can be a corner. The portion of the other material is typically a remainder of one of the plurality of trenches 312 or 212 that could be exploited to perform some functions in the completed semiconductor structure, such as: B. an electrical installation.

The present document also teaches a method of fabricating a semiconductor structure, the method comprising the steps of: forming an electrically insulating layer on a first major surface of a semiconductor substrate; Providing semiconductor material on the electrically insulating layer; Etching a first opening into the provided semiconductor material and the semiconductor substrate; and etching a second opening into the provided semiconductor material and the semiconductor substrate to define a fin between the first opening and the second opening. The method may further comprise the steps of: producing a detection element for detecting a deflection on the fin. The two etching steps may be performed during a single step of the process. The semiconductor substrate may be doped with a first doping type. The formation of the electrically insulating layer may then include doping the first main surface of the semiconductor substrate with a second doping type. Another option is to implant or otherwise inject z. B. oxygen atoms on the first main surface of the semiconductor substrate and performing an annealing step to produce an oxide layer on the first main surface of the semiconductor substrate. The provision of the additional semiconductor material can be achieved by an epitaxial process or a Venezia process. The technical features of this method may be combined with one or more of the other methods disclosed in this document.

A corresponding semiconductor structure has the following features: a semiconductor substrate having a base substrate, an applied or additional (upper) layer, and an electrically insulating layer between the base substrate and the deposited (or additional) layer; a first cavity in the deposited (or additional) layer, the electrically insulating layer and the base substrate; and a second cavity in the deposited (or additional) layer, wherein the second cavity is open to atmosphere and defines a first fin between the first cavity and the second cavity, wherein the first fin intersects the electrically insulating layer. The semiconductor may also include a sensing element configured to detect a deflection of the first blade. The base substrate and the deposited (additional) layer may be of a first doping type and the electrically insulating layer may be of a second doping type, the second doping type being opposite in polarity to the first doping type. As in the context of the method, the electrically insulating layer may have been obtained by an annealing process. The technical features of the semiconductor structure just described may be combined with features of other embodiments of a semiconductor structure disclosed herein.

4A and 4B represent cross sections through cavities where the cutting plane is substantially parallel to the major surfaces 103 . 104 . 203 . 204 of the substrate 102 . 202 , With reference to 4A has the substrate 202 three similar cavities or trenches 412 on. The cavities 412 are in the form of circumferential cavities that have an internal structure 413 surround. The inner structure 413 can with the substrate 202 be connected at a position above and / or below the plane of the drawing. Sidewalls of the inner structure 413 , in the 4A and 4B represented by their cross-sections are typically not in contact with the sidewalls of the cavity 412 as it is in 4A and 4B is apparent. Therefore, the inner structure 413 as being substantially freestanding in the cavity 412 be considered. For the purposes of this disclosure, the term "freestanding" may refer to an internal structure 413 have, at two of their outermost ends with the substrate 202 is connected, typically the upper and the lower extremity. The term "freestanding" also includes internal structures 413 which is at a single extremity with the substrate 202 regardless of a spatial relationship of the connection between the internal structure 413 and the substrate 202 (top, bottom or side).

4B similar 4A but the cavity 442 is bigger. Besides, the inner structure is 434 bigger and has a different configuration.

In both 4A and 4B are the internal structures 413 . 443 configured as tubes with reinforcing members, to ensure the stability of internal structures 413 . 443 to improve. Especially if the internal structures 413 . 443 with a single of its outermost ends to the substrate 202 are connected, is sufficient stability of the internal structure 413 . 443 required. The configuration as a tube with reinforcing members or reinforcing walls is capable of providing the required level of stability.

The internal structures 413 . 443 may be used as one of the electrodes, for example a capacitor. With reference to 4A can the lower cavity 412 the three cavities shown adjacent to a side wall or a lamella 411 be. The slat 411 can distract as a function of a pressure difference between the cavity 412 and a volume on the other side of the lamella 411 , As a result, the gap between the lamella changes 411 and the inner structure 413 its width, which leads to a variation in the capacitance of a capacitor passing through the lamella 411 and the inner structure 413 is formed. Because the inner structure 413 is relatively stable and / or rigid, causing neither the pressure difference nor the deflection of the blade 411 that is the inner structure 413 moved significantly. If the inner structure 413 . 443 It is used as an electrode of a capacitor or the like typically necessary, an electrical connection device 460 to be provided (shown schematically as the position where the electrical connection is arranged) between the internal structures 413 . 443 and a kind of evaluation circuitry. The slat 411 . 441 is typically close to a large cavity 220 , or even an edge of a semiconductor chip. The substrate 202 is relatively sensitive in the vicinity of the large cavity or the chip edge; ie the substrate can have reduced rigidity in this region. Therefore, it may be advantageous for the electrical connection device 460 at a certain distance from the lamella 411 . 441 to position. In particular with the in 4B shown inner structure 443 can the electrical connection device 460 sufficiently far away from the lamella 441 be provided because the internal structure 443 is relatively large. The electrical connection device can be provided, for example, at the position which is defined by the circle in FIG 4B is displayed.

5 shows a perspective view of an embodiment of an internal structure 543 similar to the one in 4B shown inner structure 443 , As an alternative to the above-mentioned use as a relatively rigid structure, the in 5 shown inner structure 543 Also configured to be the deflecting section (s) on the sidewalls of the internal structure 543 provided. To illustrate this, shows 5 how much different sections of the internal structure distract attention to the occupancy with a pressure (or pressure difference) of 1 bar. 5 shows the result of a simulation of a finite element model (FEM). The minimum deflection caused by the FEM simulation is 0.1 nm (indicated by a wide hatching in the drawing), the maximum deflection is 4.6 nm (indicated by cross-hatching). Interleaving levels are displayed, usually in alternating fashion, through non-hatched areas or different narrow hatched areas. In these ranges, deflection values may be observed, depending on their distance from the minimum deflection range (s) and the maximum deflection range (s). In the 4A . 4B and 5 The inner structures shown are configured to provide sufficient process capability over sufficient rigidity. During operation at a later time, a sufficiently large deflection occurs at the long portions of the fins, as can be seen at the portion shown in crosshatch, where a deflection of 4.6 nm was given by the FEM simulation. A sufficiently large deflection ensures a desired level of sensitivity. It should be noted that the internal structure 543 at its upper end is not necessarily open as it is in 5 is shown. It is equally possible that the internal structure 543 is closed at its upper end, so that four closed cavities (or any other number of closed cavities) are formed. The closed cavity may take on the role of a pressure reference volume while the pressure to be measured is applied by the circumferential trench, which is the internal structure 543 surrounds. It is also possible that the circumferential trench constitutes the reference volume and is therefore closed by a cover material. The pressure to be measured is then applied to the four or more cavities acting as pressure channels.

6A to 6D show four stages of a process by which an electrically insulating layer in a semiconductor substrate 602 can be provided. The substrate 602 is typically a semiconductor material having a fundamental doping of a first polarity, e.g. B. n ^- or p ^- . In a first step, the substrate becomes 602 doped on one surface with an opposite polarity to an oppositely doped layer 632 to create. Subsequently, an epitaxy process is performed to form a layer 634 on the oppositely doped layer 632 to build. 6D shows how a plurality of trenches 612 in the layer 634 , the oppositely doped layer 632 and the (original) substrate 602 was etched. At the opposite doped layer 632 For example, two pn junctions are formed, one of which is typically in reverse mode when there is a voltage between, for example, the top and bottom major surfaces of the substrate 602 is created. Since one of the two pn junctions is in reverse mode, the opposite doped layer acts 632 as an insulator. On the other hand, the substrate 602 in one embodiment, a homogeneous material. The opposite doped layer 632 can have different electrical properties compared to the rest of the substrate 602 but their chemical properties are essentially identical. Therefore, the majority of trenches 612 in essentially the same way through all three layers 634 . 632 and 602 etched, for example by a DT etching process.

The in 6A to 6D presented process can be before the in 1 . 2A and 2 B be performed procedures shown. The in 6A to 6D The process shown can also be combined with the arrangement of circumferential cavities and internal structures that are in 4A . 4B and 5 are shown. With reference to 6D It can be seen that the thin walls have portions that extend from the lower part of the substrate 602 through the oppositely doped layers 632 are electrically isolated. In particular, when the trenches are formed as a circumferential trench, as in 4A shown is the inner one Structure of the lower part of the substrate 602 completely electrically isolated, exclusively by the oppositely doped layer 632 , Thus, no additional measures must be taken to provide electrical insulation of the internal structure 413 to reach ( 4A ).

Pressure sensors having a vertical configuration formed in a semiconductor substrate (as shown in FIG 8th and illustrated below) have been developed by the inventors in the past. With some of these pressure sensors, it is a challenge to apply doping to trenches that have extreme aspect ratios, with the doping providing electrical isolation of the pressure sensitive fins. Furthermore, a lateral doping of opposite polarity must be provided at the ends of the trenches. If possible, the process step sequence used for this purpose should be mask-free and robust.

• • Aufbringen des Hartmaskehaufens für Grabenätzen (7A)
• • Grabenätzen und Hartmaskenhaufenentfernung (Nitridschicht bleibt an der Oberfläche und blockiert die zukünftige Arsenglasbeschichtung und Borimplantation an den betreffenden Stellen) (7B)
• • Arsenglasbeschichtung und Eindringen des Arsens (7C)
• • Borimplantation und Aktivierung des Bors (7D)
• • Aufbringen von Oxynitrid (dünne Anschlussfläche Oxid darunter), Ausnehmung des Oxynitrids (das oberflächliche Nitrid wird gleichzeitig entfernt) (7E)
• • Metallisierung (7F)

So far, proposals have been made in the company where the inventors are concerned to realize the lamella doping by arsenic glass coating on and subsequently providing the electrical insulation of the lamellae at the bottom and the sides by two angled boron implantations. A currently used process sequence for electrically isolating the pressure sensitive structures is shown in FIG 7A to 7F and includes the following steps:

• • application of the grindstone grain for trench etching ( 7A )
• • Graben etch and hard mask stack removal (nitride layer remains on the surface and blocks the future arsenic glass coating and boron implantation at the sites involved) ( 7B )
• Arsenic glass coating and arsenic penetration ( 7C )
• Boron implantation and activation of the boron ( 7D )
• • Application of oxynitride (thin pad oxide underneath), recess of oxynitride (the surface nitride is simultaneously removed) ( 7E )
• • metallization ( 7F )

In 7D For example, boron implantation is rotated 180 degrees rotated at an angle of 45 degrees with respect to the plane of the drawing and a second boron implantation to simultaneously ensure the opposite polarity doping for the bottom (layer at height indicated by "p +") and at the trench end. Typical setting accuracies in the implantation equipment are about 1 degree. Depending on the aspect ratio of the trench, higher accuracies are required so that, for example, implantation has been done several times to get a hit. This can lead to a relatively large variance of the implanted dose. Even though several implantations have been performed, it is challenging to achieve a sufficiently high doping of opposite polarity to isolate the lamellae.

In accordance with teachings disclosed herein, a combination of structural modifications and a modified integration scheme or doping sequence for electrically isolating the structure is proposed. First, the pressure-sensitive structures are adjusted in a manner that insulation at the fin end can be omitted, the result being, for example, in FIG 4A . 4B and 5 to see. An angled implantation for doping the fin ends is no longer necessary. To completely isolate the pressure fins from the substrate, it is sufficient to dope the inner structure (s) at the bottom of the trench. This introduces new integration options. A simple variation is an epitaxy of the substrate in a way that the doping of opposite polarity can be made on the wafer even before the trenches are etched. This sequence is in 6A to 6D outlined.

The implanted dose can be controlled relatively accurately and sufficiently high doping can be achieved with a few implants or even a single implant.

The teachings disclosed herein may be combined or implemented with a silicon on insulator (SOI) technology. This technology relates to the use of a layered silicon-insulator-silicon substrate rather than conventional silicon substrates in semiconductor manufacturing, particularly microelectronics, to reduce parasitic device capacitance and thereby improve performance. The insulator is typically silicon dioxide or sometimes sapphire. Instead of doping, for example, before 6B has been performed, the insulator layer of an SOI structure may be deposited or formed by processes known in the art of SOI technology.

A non-angled implantation in the bottom of the trench is also conceivable. This typically results in a simpler process compared to the angled implant. Depending on the depth of the structures, ultra high energy implantation is also possible - with a high temperature annealing step that sufficiently disperses and activates the dopants (eg, 3 MeV phosphorus and 240 minutes at 1200 degrees Celsius). The latter combination would be somewhat more favorable than a sequence with an epitaxy step, as suggested above.

8th FIG. 12 illustrates a cross section through a semiconductor structure used as a pressure sensor. The cavity 706 is a pressure channel and the cavity 707 is a pressure chamber that serves as a reference for pressure measurement. A slat 711 is between the pressure channel 706 and the pressure chamber 707 intended. The two slats 711 that the pressure chamber 707 enclose, are able to under the influence of a pressure difference between the pressure channel 706 and the pressure chamber 707 distract. The left lamella forms a first electrode of a capacitor, the right lamella 711 forms a second electrode of the capacitor and the pressure chamber 707 forms the gap of the capacitor. To be electrically conductive, each of the two fins 711 acting as a capacitor electrode, n ⁺ doped, at least on the surface of the fin. The two electrodes are electrically connected to an evaluation circuitry arranged in one or more layers 730 is provided. In the 8th The structure shown also has a second major surface 704 to which the pressure channels 706 are open. The width of the gap of the capacitor is indicated by the letter s, while the width of the louver 711 in 8th is indicated with the letter w. Around the slats 711 with respect to each other at their lower ends to electrically isolate, the p ⁺ -doped portion is provided, which acts as an insulating layer, in a similar manner as that with reference to FIG 6A to 6D is described.

The design of the pressure sensors (either standalone or integrated into an ASIC) is typically very similar to currently available models: a cavity is bounded on one or more sides by a louver. The blade is exposed to external media so that it deflects upon a change in external pressure. This mechanical information is then converted into an electrical signal by piezoresistive capacitors or other suitable methods and processes.

In the case of capacitive information conversion, the fin forms a capacitor with a sidewall of the cavity facing the fin. In order to achieve high sensitivity of this arrangement, the lamella must be thinned and the cavity must be narrow. In this way, a large change in the electrode gap relative to a starting distance is achieved. At the same time, the measuring range of the device is limited because a further increase in pressure will not cause any further change in the capacitance signal once the two electrodes are in contact.

This problem can be circumvented by a manufacturer of capacitance-based pressure sensors offering a number of different sized sensors (in terms of fin thickness and / or cavity width). A user may then select a suitable sensor for the intended application. It is possible that pressure fluctuations over a very large area must be detected by using multiple sensors, each optimized for a subarea. Alternatively, a single sensor may cover the entire area, but at the expense of lower sensitivity due to the use of a thicker fin and / or a wider cavity.

The problem of a limited range of measurement can be solved by placing the fin in a tapered relationship with respect to the opposite cavity sidewall rather than a parallel relationship. Alternatively, the blade itself may be formed in a tapered shape. As a further alternative, a combination of these variants can be used. The provision of a tapered cavity, a tapered blade, or both, results in an arrangement in which a highly sensitive conversion of the pressure signal in the first portion can be observed, while in other portions a sufficient distance remains between the blade and an opposing wall. in order to be able to capture a much larger pressure range. In other words, the tapered cavity, the tapered gap and / or the tapered blade may impart progressive sensitivity to the sensor (measured value small → sensitivity high and vice versa).

With a deep trench etching process, the dimensions and shape of the cavities (or etch trenches) and lamellae (silicon mesa) can be defined by lithography and process parameters. For example, an etching trench for a lamella having a wedge-shaped lateral cross-section can be obtained by lithography. By controlling the etching process, a wedge-shaped cross section in the vertical direction can be generated. Furthermore, the etch depth varies with the width of the trench opening and the process parameters. Varying the process parameters during the etching allows a more or less pronounced effect, so that a further degree of freedom in forming the cavities and / or the lamellae is available.

According to the teachings disclosed herein, the cavity and / or louver of a pressure sensor are arranged so that surfaces defining the plates of a capacitor are not parallel to one another but exhibit a tapered or wedge-like geometry. The term "rejuvenating" means that the cavity or lamella has a varying thickness or width. The variation in thickness or width is not limited to linear variation, but may take other forms of variations, such as variations in thickness and width. B. curved or stepped.

9 shows a first variation where the lithography mask defines a trapezoidal cross section of the cavities. 9 is a cross-section through the substrate at about the position indicated by VIII-VIII in FIG 8th is displayed.

10 shows another variant in which the lithography mask defines a trapezoidal cross section for the lamella. The arrows in 9 and 10 indicate which of the cavities to the back of the second major surface 704 are open (see 8th ).

Many other implementations are possible. Not shown in the drawings, for example, is an etching depth that varies across the cavity, which can be obtained by combining a lithography of 9 with an etching process that is strongly influenced by the trench width (shallow regions for narrow trench width, deep etches for wider trench widths). Furthermore, it is not necessary to increase the widths linearly.

11 FIG. 12 illustrates a schematic cross section through the substrate having a first cavity and a second cavity. The first cavity has a width s ₁ and the second cavity has a width s ₂ . As it is in 11 is seen, the width s _{1 of} the first cavity is greater than the width s _{2 of} the second cavity, by a factor of more than 10. Nevertheless, the lamella 1011 , which separates the first cavity from the second cavity, is relatively thin and accurately measured, which is important for sensor structures to obtain the desired measurement range and measurement sensitivity.

12 and 13 FIG. 2 illustrates a schematic top view of a semiconductor structure and a schematic perspective view of a cross section of the same structure. FIG 13 how electrical connection to an internal structure can be provided when the internal structure is electrically isolated from the surrounding substrate. The big cavity 220 is adjacent to another cavity 442 which has a tapered cross-section. The big cavity 220 was obtained for example by the related 2A and 2 B illustrated and explained method. As it is in 13 5 trenches shown in the right part of the drawing were used to make the large cavity 220 and then were with the closing material 217 closed. 12 and 13 show the closed remnants of these earlier five trenches. The first and third trenches of the plurality of trenches (when counted from the left) were used to form the other cavity 442 define. Except the fact that the cavity 442 has a tapered cross-section, it is similar to the cavity 442 in 4A and 4B , The slat 411 separates the big cavity 220 from the cavity 442 , The slat 411 also has a tapered cross-section, for example, for the reasons associated with 9 and 10 were explained.

At the in 12 and 13 the embodiment shown is the cavity 442 a circumferential trench. The inner structure 442 has seen from above substantially a flat-tube configuration, as in the plan view of 12 (It should be noted that a front part of the internal structure 443 in 12 not shown). A direct connection between the inner structure 443 and the substrate is only at a lower end of the inner structure 443 intended. At an upper end is the inner structure 443 only in contact with the housing material 217 , except for an electrical connection 426 at the top of the inner structure 443 is provided (electrical connection is in 12 Not shown). The closing material 217 acts as an electrical insulator between the internal structure 443 and the substrate. To the inner structure 443 at its lower end to completely electrically insulate against the substrate can be an insulating layer 632 at the lower end of the inner structure 443 be provided, close to a transition of the internal structure 443 and the substrate. For details about the insulating layer 632 and their generation is referred to 6A - 7F and the corresponding description.

14 represents how a semiconductor structure 1400 on a wafer 1401 can be arranged. In a schematic way, the semiconductor structure 1400 a cavity 1412 which may be a closed cavity or an open cavity. The cavity 1412 is near a chip ditch 1420 positioned so that only the slat 1411 the cavity 1412 from the chip-input trench 1420 separates. At the end of a manufacturing process, the semiconductor structure becomes 1400 at the chip-input trench 1420 singulated as indicated by the dashed rectangle. As a result, the cavity 1412 near an edge of the semiconductor structure 1400 , z. B. near a chip edge. Thus, the space around the semiconductor structure takes 1400 around, for example, the role of the pressure channel. In the case of a pressure sensor, no additional cavity is required to fulfill the role of the pressure channel. The semiconductor structure 1400 Can be fixed so that the chip edge near the cavity 1412 exposed to the medium whose pressure is to be measured. The cavity 1412 serves as a reference volume. The cavity 1412 may go to another side of the surface of the semiconductor structure 1400 be open so that a differential pressure can be measured.

Embodiments provide sensors that are inexpensive and integrated on a single chip with logic devices. Embodiments of the sensors are combined using CMOS manufacturing processes. The sensor cavities and sensing elements can be defined for the desired sensitivity and working range.

While specific embodiments are illustrated and described herein, it will be understood by those of ordinary skill in the art that a variety of corresponding and / or equivalent implementations will be employed for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of these specific embodiments discussed herein.

Claims (12)

Method for providing a semiconductor structure ( 100 . 200 ) comprising the steps of: forming a sacrificial structure ( 110 . 210 ) by etching a plurality of trenches ( 112 . 212 ) from a first main surface ( 103 . 203 ) of a substrate ( 102 . 202 ), whereby the victim structure ( 110 . 210 ) one or more walls between the trenches ( 112 . 212 ) having; Covering the plurality of trenches ( 112 . 212 ) at the first main surface ( 103 . 203 ) with a cover material ( 115 . 215 ) to cavities in the substrate ( 102 . 202 ) so that the cover material ( 115 . 215 ) substantially at the first main surface ( 103 ) of the substrate ( 102 ), rather than to the bottom of the plurality of trenches ( 112 . 212 ) to fall; Removing a part of the substrate ( 102 . 202 ) from a second main surface ( 104 . 204 ) opposite the first main surface ( 103 . 203 ) to a depth at which the plurality of trenches ( 112 . 212 ) are present; and etching away the victim structure ( 110 . 210 by etching away the one or more walls from the second major surface ( 104 . 204 ) of the substrate ( 102 . 202 ), so that a recess ( 120 . 220 ) is created with a bottom that covers the cover material ( 115 . 215 ). The method of claim 1, wherein the etching of the plurality of trenches ( 112 . 212 ) structuring the substrate ( 102 . 202 ) with an arrangement of a sacrificial structure ( 110 . 210 ), wherein the arrangement dimensions of the recess ( 220 ) by etching away the sacrificial structures ( 110 . 210 ) is formed by the second main surface. Method according to claim 1 or 2, wherein the covering of the plurality of trenches ( 112 . 212 ) forming a layer over at least a portion of the first major surface ( 103 . 203 ) of the plurality of trenches ( 112 . 212 ) using at least one of an epitaxy process and a Venetia process. Method according to one of claims 1 to 3, further comprising the step of: generating semiconductor structures on the first main surface ( 103 . 203 ) after covering the plurality of trenches ( 112 . 212 ). Method according to one of claims 1 to 4, wherein the plurality of trenches ( 112 . 212 ) at least one trench with a smaller trench width than other trenches ( 112 . 212 ) of the plurality of trenches ( 112 . 212 ), the method further comprising the steps of: selectively closing the at least one trench having the smaller trench width at the first major surface ( 103 . 203 ) after forming the sacrificial structure ( 110 . 210 ). Method according to claim 5, wherein the selective closing prior to covering the plurality of trenches ( 112 . 212 ), wherein the method further comprises the following steps: applying a cover layer material ( 216 ) in the plurality of trenches ( 112 . 212 ) prior to selectively closing the at least one trench having the smaller dimension; Performing the selective closure of the at least one trench having the smaller dimension; Removing the cover sheet material from the other trenches ( 112 . 212 ) that do not have the smaller dimension; wherein during the etching of the second main surface area ( 104 . 204 ) Victim structures ( 110 . 210 ) adjacent to trenches ( 112 . 212 ) in which the cover layer material ( 216 ), are etched away, and structures buried by trenches ( 112 . 212 ), in which the cover layer material ( 216 ) was not etched away. Method according to one of claims 1 to 6, wherein the recess ( 120 . 220 ) by etching away the sacrificial structures ( 110 . 210 ) from the second main surface ( 104 . 204 ) is formed, has a tapered cross-section. The method of claim 1, further comprising the steps of: forming a circumferential trench having an internal structure adjacent to a region of the plurality of trenches; 112 . 212 ), wherein between the circumferential trench and the region of the plurality of trenches ( 112 . 212 ) a lamella ( 411 ) is formed; and covering the circumferential trench before covering the plurality of trenches. Method according to one of claims 1 to 8, further comprising prior to forming the sacrificial structure ( 110 . 210 ) comprises the following steps: producing an electrically insulating layer on a first main surface ( 103 ) of the substrate ( 102 . 202 ); and applying an outer layer of substrate material on the electrically insulating layer so that a surface of the outer layer has the first major surface ( 103 ); wherein the etching of the plurality of trenches ( 112 . 212 ) is performed from the surface of the outer layer and extends at least to the electrically insulating layer. The method of claim 1, wherein the method provides a sensor structure for converting a mechanical quantity to an electrical quantity, the method further comprising: providing a conversion element for converting the mechanical quantity to the electrical quantity at a wall of the device Recess ( 220 ) by etching away the sacrificial structure ( 110 . 210 ) is formed. Method according to one of claims 1 to 10, further comprising the step of: etching a further trench adjacent to the sacrificial structures ( 110 . 210 ); wherein a wall is formed between the further trench and at least the recess ( 220 ) obtained by etching the sacrificial structure ( 110 . 210 ) is defined. Method for providing a semiconductor structure ( 200 ) comprising the steps of: forming a sacrificial structure ( 210 ) by etching a plurality of trenches ( 212 ) from a first main surface ( 203 ) of a substrate ( 202 ), whereby the victim structure ( 210 ) one or more walls between the trenches ( 212 ) having; Covering the plurality of trenches ( 212 ) at the first main surface ( 203 ) with a cover material ( 215 ) to cavities in the substrate ( 202 ) define; Removing a part of the substrate ( 202 ) from a second main surface ( 204 ) opposite the first main surface ( 203 ) to a depth at which the plurality of trenches ( 212 ) are present; and etching away the victim structure ( 210 ) from the second main surface ( 204 ) of the substrate ( 202 ), wherein the plurality of trenches ( 212 ) at least one trench with a smaller trench width than other trenches ( 212 ) of the plurality of trenches ( 212 and wherein the method further comprises the step of selectively closing the at least one trench having the smaller trench width at the first major surface (FIG. 203 ) after forming the sacrificial structure ( 210 ).

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